Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘MEMS’

Next Page »

Silicon Photonics Technology Developments

Thursday, April 6th, 2017

thumbnail

By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.

—E.K.

Silicon as Disruptive Platform for IoT Applications

Monday, August 29th, 2016

thumbnail

By Ed Korczynski, Sr. Technical Editor

Marie Semeria, chief executive officer of CEA-Leti (http://www.leti.fr/en), sat down with SemiMD during SEMICON West to discuss how the French R&D and pilot manufacturing campus—located at the foot of the beautiful French alps near Grenoble—is expanding the scope of it’s activities to develop systems solutions for the Internet-of-Things (IoT). Part-1 on hardware/software co-development was published last month.

Korczynski: Regarding ‘IoT’ applications, we expect that chips must be very low cost to be successful, and at the same time the ultimately winning solutions will be those that combine the best functionalities from different technology spaces each in a ‘sweet spot’ of cost to performance. It seems that being able to do it on SOI wafers could produce the right volumes.

Semeria: Yes. It could be enough.

Korczynski: Do you have any feel in advance for how much area of silicon is needed? Some small ADC, an 8-bit micro-controller, and RF components may be done in different processes and then integrated. Is it possible that the total area of silicon needed could be less than a square millimeter?

Semeria: Yes.

Korczynski: Well, if they are that small then we have to remember how many units we’d get from just a single wafer, and there are 24 wafers in a batch…

Semeria: One batch can be enough for one market, depending upon the application.

Korczynski: If this is the case, then even though the concept of purely-additive roll-to-roll processes are attractive, oddly they may be too efficient and produce more units than the world can absorb. If we can do all that we need to do with established silicon wafer fab technology creating ICs smaller than a square millimeter then it will be very cost-effective.

Semeria: Leti’s strategy is to keep the performance of solid-state devices, so not to go to organic electronics. Use silicon as the differentiator to lower the cost, add more functions, and then miniaturize all that can be miniaturized. In this way we are achieving integration of MEMS with small electronics in arrays as small as one millimeter square. When you deal with such small die you can put them inside of flexible materials, inside of a t-shirt and it’s no problem. So that’s our strategy to keep small silicon and put it in clothes, in shoes, in windows, in glasses, and all sorts of flexible materials. When you are thinning substrates for bonding, then the thinned silicon is very flexible.

Korczynski: In 1999 I worked for one of the first companies selling through-silicon via technology, and it was all about backside thinning so I’ve played with flexible wafers.

Semeria: So you know what I mean.

Korczynski: Around 50 microns and below as long as you etch away any grinding defects from the backside it is very strong and very flexible (Fig. 1). At 50 microns the chip is still thick enough to be easily picked-and-placed, but it’s flexible. Below 10 microns the wafer is difficult to handle.

FIGURE 1: 50 micron thin silicon wafers can be strong and very flexible. (Source: Virginia Semiconductor)

Semeria: To maintain the advantage of cost for different applications spaces, we are developing the ‘chiplet’ approach which means a network of chips. It starts with a digital platform, then you add an active interposer to connect different dice. For example you could have 28nm-node on the bottom and a 14nm-node chip on top for some specific function. Then you can put embedded memory and RF connected through the interposer, and it’s the approach that we promote for the first generation of multi-functional integration on digital. Very flexible, cost-effective.

Korczynski: This is using some sort of bus to move information?

Semeria: Yes, this will be an electronic bus for the first generation, as we recently announced. Then a photonics interposer could be used for higher-speed data rate in a future generation. We have a full roadmap with different types of integration schemes. So it’s a way to combine all with silicon. Everything is intended to be integrated into existing 300mm silicon facilities. Some weeks ago we presented the first results showing silicon quantum bits built on 300mm substrates, and fully compatible with CMOS processing. So it’s the way we are going, taking a very disruptive approach using the foundation of proven 300mm silicon processing.

Korczynski: Interesting.

Semeria: For example, regarding driving assistance applications we have to consider fusion integration of different sensors, and complete coverage of the environment with low power-consumption. For computing capacity we developed a completely disruptive approach, very different from Intel and very different from nVidia which use consumer products as the basis for automotive application products. Specifically for automotive we developed a new probabilistic methodology to avoid all of the calculations based on floating-point. In this way we can divide the computing needs of the device by 100, so it’s another example of developing just the right device for the right application adapted for the right environment. So the approach is very different in development for IoT instead of mainstream CMOS.

Korczynski: For automotive there’s such a requirement for reliability, with billions of dollars at stake in product recalls and potential lawsuits, the auto industry is very risk-averse for very good reasons. So historically they’ve always used trailing-edge nodes, and if you want to supply to them you have to commit to 10 or maybe 20 years of manufacturing, and yet we still want to add in advance functionalities. The impression I’ve gotten is that the 28nm FD-SOI platform is fairly ideal here.

Semeria: FD-SOI is very reliable and very efficient. That’s why when we showed our demonstrator at the recent DAC it’s based on the STMicroelectronics micro-controller. It’s very reliable and adaptable for automotive applications.

Korczynski: Is it at 28nm?

Semeria: No, about 40nm now. The latest generation is not needed, because we changed the algorithms so we didn’t need so much capacity in computing. In IoT there is space to use 40nm or 32nm down to 28nm. It’s a great space to use ‘old technologies’ and optimize them with the right algorithms, the right signal-processing, and the right security. So it’s very exciting for Leti because we have all of the key competencies to be able to handle the IoT challenge, and there is a great ability to make various integration schemes depending upon the application. There is a very large space to demonstrate, and to develop new materials.

Korczynski: Does this relate to some recent work I’ve seen from Leti with micro-cantilevers?

Semeria: Yes, this is the work we are doing with CalTech on micro-resonators (Fig. 2).

FIGURE 2: MEMS/NEMS silicon cantilever resonator capable of detecting individual adhered molecules, for integration with digital CMOS in a complete IoT sensing system. (Source: Leti)

Korczynski: Thank you very much for taking the time to discuss these important trends.

Semeria: It is a pleasure.

—E.K.

IoT Demands Part 2: Test and Packaging

Friday, April 15th, 2016

By Ed Korczynski, Senior Technical Editor, Solid State Technology, SemiMD

The Internet-of-Things (IoT) adds new sensing and communications to improve the functionality of all manner of things in the world. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT applications will have to be extremely small and low-cost. To understand the state of technology preparedness to meet the anticipated needs of the different application spaces, experts from GLOBALFOUNDRIES, Cadence, Mentor Graphics and Presto Engineering gave detailed answers to questions about IoT chip needs in EDA and fab nodes, as published in “IoT Demands:  EDA and Fab Nodes.” We continue with the conversation below.

Korczynski: For test of IoT devices which may use ultra-low threshold voltage transistors, what changes are needed compared to logic test of a typical “low-power” chip?

Steve Carlson, product management group director, Cadence

Susceptibility to process corners and operating conditions becomes heightened at near-threshold voltage levels. This translates into either more conservative design sign-off criteria, or the need for higher levels of manufacturing screening/tests. Either way, it has an impact on cost, be it hidden by over-design, or overtly through more costly qualification and test processes.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

We need to make sure that the testability has also been designed to be functional structurally in this mode. In addition, sub-threshold voltage operation must account for non-linear transistor characteristics and the strong impact of local process variation, for which the conventional testability arsenal is still very poor. Automotive screening used low voltage operation (VLV) to detect latent defects, but at very low voltage close to the transistor threshold, digital becomes analog, and therefore if the usual concept still works for defect detection, functional test and @speed tests require additional expertise to be both meaningful and efficient from a test coverage perspective.

Korczynski:  Do we have sufficient specifications within “5G” to handle IoT device interoperability for all market segments?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

The estimated timeline for standardization availability of 5G is around 2020. 5G is being designed keeping three classes of applications in mind:  Enhanced Mobile Broadband, Massive IoT, and Mission-Critical Control. Specifically for IoT, the focus is on efficient, low-cost communication with deep coverage. We will start to see early 5G technologies start to appear around 2018, and device connectivity,

interoperability and marshaling the data they generate that can apply to multiple IoT sub-segments and markets is still very much in development.

Korczynski:  Will the 1st-generation of IoT devices likely include wide varieties of solution for different market-segments such as industrial vs. retail vs. consumer, or will most device use similar form-factors and underlying technologies?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

If we use CES 2016 as a showcase, we are seeing IoT “Things” that are becoming use-case or application-centric as they apply to specific sub-segments such as Connected Home, Automotive, Medical, Security, etc. There is definitely more variety on the consumer front vs. industrial. Vendors / OEMs / System houses are differentiating at the user-interface design and form-factor levels while the “under-the-hood” IC capabilities and component technologies that provide the atomic intelligence are fairly common. ​

Steve Carlson, product management group director, Cadence

Right now it seems like everyone is swinging for the fence. Everyone wants the home-run product that will reach a billion devices sold. Generality generally leads to sub-optimality, so a single device usually fails to meet the needs and expectations of many. Devices that are optimized for more specific use cases and elements of purchasing criteria will win out. The question of interface is an interesting one.

Korczynski:  Will there be different product life-cycles for different IoT market-segments, such as 1-3 years for consumer but 5-10 years for industrial?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

That certainly seems to be the case. According to Gartner’s market analysis for IoT, Consumer is expected to grow at a faster pace in terms of units compared to Enterprise, while Enterprise is expected to lead in revenue. Also the churn-cycle in Consumer is higher / faster compared to Enterprise. Today’s wearables or smart-phones are good reference examples. This will however vary by the type of “Thing” and sub-segment. For example, you expect to have your smart refrigerator for a longer time period compared to smart clothing or eyewear. As ASPs of the “Things”come down over time and new classes of products such as disposables hit the market, we can expect even larger volumes.​

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

The market segments continue to be driven by the same use cases. In consumer wearables, short cycles are linked to fashion trends and rapid obsolescence, where consumer home use has longer cycles closer to industrial market requirements. We believe that the lifecycle norms will hold true for IoT devices.

Korczynski:  For the IoT application of infrastructure monitoring (e.g. bridges, pipelines, etc.) long-term (10-20 year) reliability will be essential, while consumer applications may be best served by 3-5 year reliability devices which cost less; how well can we quantify the trade-off between cost and chip reliability?

Steve Carlson, product management group director, Cadence

Conceptually we know very well how to make devices more reliable. We can lower current densities with bigger wires, we can run at cooler temperatures, and so on.  The difficulty is always in finding optimality for a given criterion across the, for practical purposes, infinite tradeoffs to be made.

Korczynski:  Why is the talk of IoT not just another “Dot Com” hype cycle?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

​​I participated in a panel at SEMICON China in Shanghai last month that discussed a similar question. If we think of IoT as a “brand new thing” (no pun intended), then we can think of it as hype. However if we look at the IoT as as set of use-cases that can take advantage of an evolution of Machine-to-Machine (M2M) going towards broader connectivity, huge amounts of data generated and exchanged, and a generational increase in internet and communication network bandwidths (i.e. 5G), then it seems a more down-to-earth technological progression.

Nicolas Williams, product marketing manager, Mentor Graphics

Unlike the Dot Com hype, which was built upon hope and dreams of future solutions that may or may not have been based in reality, IoT is real business. For example, in a 2016 IC Insights report, we see that last year $63.4 billion in revenue was generated for IoT systems and the market is growing at about 20% CAGR. This same report also shows IoT semiconductor sales of over $15 billion in 2015 with a CAGR of 21.1%.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

It is the investment needed up front to create sensing agents and an infrastructure for the hardware foundation of the IoT that will lead to big data and ultimately value creation.

Steve Carlson, product management group director, Cadence

There will be plenty of hype cycles for products and product categories along the way. However, the foundational shift of the connection of things is a diode through which civilization will only pass through in one direction.

IoT Demands Part 1: EDA and Fab Nodes

Thursday, April 14th, 2016

The Internet-of-Things (IoT) is expected to add new sensing and communications to improve the functionality of all manner of things in the world:  bridges sensing and reporting when repairs are needed, parts automatically informing where they are in storage and transport, human health monitoring, etc. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT applications will have to be assembled at low-cost and small-size in High Volume Manufacturing (HVM). Micro-Electro-Mechanical Systems (MEMS) and other sensors are being combined with Radio-Frequency (RF) ICs in miniaturized packages for the first wave of growth in major sub-markets.

To meet the anticipated needs of the different IoT application spaces, SemiMD asked leading companies within critical industry segments about the state of technology preparedness:

*  Commercial IC HVM – GLOBALFOUNDRIES,

*  Electronic Design Automation (EDA) – Cadence and Mentor Graphics,

*  IC and complex system test – Presto Engineering.

Korczynski:  Today, ICs for IoT applications typically use 45nm/65nm-node which are “Node -3″ (N-3) compared to sub-20nm-node chips in HVM. Five years from now, when the bleeding-edge will use 10nm node technology, will IoT chips still use N-3 of 28nm-node (considered a “long-lived node”) or will 45nm-node remain the likely sweet-spot of price:performance?

Timothy Dry, product marketing manager, GLOBALFOUNDRIES

In 5 years time, there will be a spread of technology solutions addressing low, middle, and high ends of IoT applications. At the low end, IoT end nodes for applications like connected smoke

detectors, security sensors will be at 55, 40nm ULP and ULL for lowest system power, and low cost. These applications will be typically served by MCUs <50DMIPs. Integrated radios (BLE, 802.15.4), security, Power Management Unit (PMU), and eFlash or MRAM will be common features. Connected LED lighting is forecasted to be a high volume IoT application. The LED drivers will use BCD extensions of 130nm—40nm—that can also support the radio and protocol-MCU with Flash.

In the mid-range, applications like smart-meters and fitness/medical monitoring will need systems that have more processing power <300DMIPS. These products will be implemented in 40nm, 28nm and GLOBALFOUNDRIES’ new 22nm FDSOI technology that uses software-controlled body-biasing to tune SoC operation for lowest dynamic power. Multiple wireless (BLE/802.15.4, WiFi, LPWAN) and wired connectivity (Ethernet, PLC) protocols with security will be integrated for gateway products.

High-end products like smart-watches, learning thermostats, home security/monitoring cameras, and drones will require MPU-class IC products (~2000DMIPs) and run high-order operating systems (e.g. Linux, Android). These products will be made in leading-edge nodes starting at 22FDX, 14FF and migrating to 7FF and beyond. Design for lowest dynamic power for longest battery life will be the key driver, and these products typically require human machine Interface (HMI) with animated graphics on a high resolution displays. Connectivity will include BLE, WiFi and cellular with strong security.

Steve Carlson, product management group director, Cadence

We have seen recent announcements of IoT targeted devices at 14nm. The value created by Moore’s Law integration should hold, and with that, there will be inherent advantages to those who leverage next generation process nodes. Still, other product categories may reach functionality saturation points where there is simply no more value obtained by adding more capability. We anticipate that there will be more “live” process nodes than ever in history.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

It is fair to say that most IoT devices will be a heterogeneous aggregation of analog functions rather than high power digital processors. Therefore, and by similarity with Bluetooth and RFID devices, 90nm and 65nm will remain the mainstream nodes for many sub-vertical markets, enabling the integration of RF and analog front-end functions with digital gate density. By default, sensors will stay out of the monolithic path for both design and cost reasons. The best answer would be that the IoT ASIC will follow eventually the same scaling as the MCU products, with embedded non-volatile memories, which today is 55-40nm centric and will move to 28nm with industry maturity and volumes.

Korczynski:  If most IoT devices will include some manner of sensor which must be integrated with CMOS logic and memory, then do we need new capabilities in EDA-flows and burn-in/test protocols to ensure meeting time-to-market goals?

Nicolas Williams, product marketing manager, Mentor Graphics

If we define a typical IoT device as a product that contains a MEMS sensor, A/D, digital processing, and a RF-connection to the internet, we can see that the fundamental challenge of IoT design is that teams working on this product need to master the analog, digital, MEMS, and RF domains. Often, these four domains require different experience and knowledge and sometimes design in these domains is accomplished by separate teams. IoT design requires that all four domains are designed and work together, especially if they are going on the same die. Even if the components are targeting separate dice that will be bonded together, they still need to work together during the layout and verification process. Therefore, a unified design flow is required.

Stephen Pateras, product marketing director, Mentor Graphics

Being able to quickly debug and create test patterns for various embedded sensor IP can be addressed with the adoption of the new IEEE 1687 IP plug-and-play standard. If a sensor IP block’s digital interface adheres to the standard, then any vendor-provided data required to initialize or operate the embedded sensor can be easily and quickly mapped to chip pins. Data sequences for multiple sensor IP blocks can also be merged to create optimized sequences that will minimize debug and test times.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

From a testing standpoint, widely used ATEs are generally focused on a few purposes, but don’t necessarily cover all elements in a system. We think that IoT devices are likely to require complex testing flows using multiple ATEs to assure adequate coverage. This is likely to prevail for some time as short run volumes characteristic of IoT demands are unlikely to drive ATE suppliers to invest R&D dollars in creating new purpose-built machines.

Korczynski:  For the EDA of IoT devices, can all sensors be modeled as analog inputs within established flows or do we need new modeling capability at the circuit level?

Steve Carlson, product management group director, Cadence

Typically, the interface to the physical world has been partitioned at the electrical boundary. But as more mechanical and electro-mechanical sensors are more deeply integrated, there has been growing value in co-design, co-analysis, and co-optimization. We should see more multi-domain analysis over time.

Nicolas Williams, product marketing manager, Mentor Graphics

Designers of IoT devices that contain MEMS sensors need quality models in order to simulate their behavior under physical conditions such as motion and temperature. Unlike CMOS IC design, there are few standardized MEMS models for system-level simulation. State of the art MEMS modeling requires automatic generation of behavioral models based on the results of Finite Element Analysis (FEA) using reduced-order modeling (ROM). ROM is a numerical methodology that reduces the analysis results to create Verilog-A models for use in AMS simulations for co-simulation of the MEMS device in the context of the IoT system.

New MEMS Design Contest Encourages Advances in MEMS Technology

Wednesday, March 16th, 2016

Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks. To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge.

The contest seeks companies, entrepreneurs, researchers and students from around the globe. Design teams are encouraged to propose imaginative design concepts that combine MEMS and mixed-signal technologies. The organizers will provide free training workshops to familiarize the participating teams with the design tools, design methodologies and process technologies involved.

A panel of highly experienced industry professionals and respected academics will undertake appraisal of the submissions. Each submission will be judged on the degree of innovation demonstrated in hardware and methodology, the novelty of the application and the value the design provides. Awards for the top three submissions will be presented at Cadence’s annual user conference, CDNLive EMEA 2018, in Munich and the winning team’s solution will be manufactured at X-FAB’s wafer production facilities.

“Supporting innovation and advancement in electronic design is fundamental to what this contest is all about,” said Alexander Duesener, Corporate VP EMEA of Cadence Design Systems. “Creating mixed-signal logic and MEMS designs requires a new process flow and totally new thinking. By enabling the winning design team to turn their concepts into manufactured designs, we highlight the value of MEMS and mixed-signal designs in today’s products.”

“The MEMS Design Contest calls attention to the increasing integration of MEMS and mixed-signal technologies in phones, cars and Internet of Things (IoT) devices,” said Dr. Stephen Breit, Vice President of Engineering at Coventor. “By offering design teams state-of-the-art Cadence and Coventor tools in combination with X-FAB’s latest MEMS and CMOS design kits, we hope to inspire new applications of our combined solution for efficiently designing, integrating and manufacturing MEMS and mixed-signal CMOS technologies.”

“By enabling the winning design team to turn their ideas into manufactured designs, X-FAB is highlighting the value of proven MEMS process technology and design enablement through our design kits,” added Joerg Doblaski, Director Design Support at X-FAB. “We look forward to seeing innovative designs from around the world and helping bring the best of them to life.”

For complete information on the contest and how to enter visit: http://www.cadence.com/MEMS_Design_Contest_2018

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016

thumbnail

By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

Identifying the Prime Challenge of IoT Design

Friday, December 18th, 2015

thumbnail

By Jeff Miller, Product Marketing Manager, Mentor Graphics Corporation

Introduction

In his blog post for Semiconductor Manufacturing & Design, Pete Singer shared how the acquisition of Tanner EDA by Mentor Graphics provides a solution to meeting the design challenge of Internet of Things (IoT). Low-cost IoT designs, which interface the edge of the real world to the Internet, mesh together several design domains. Individually, these design domains are challenging for today’s engineers. Bringing them all together to create an IoT product can place extreme pressure on design teams. For example, let’s look at the elements of a typical IoT device (Figure 1).

Figure 1: A typical IoT device.

This IoT device contains a sensor and an actuator that interface to the Internet. The sensor signal is sent to an analog signal processing device in the form of an amplifier or a low-pass filter. The output connects to an A/D converter to digitize the signal. That signal is sent to a digital logic block that contains a microcontroller or a microprocessor. Conversely, the actuator is controlled by an analog driver through a D/A converter. The sensor telemetry is sent and control signals are received by a radio module that uses a standard protocol such as WiFi, Bluetooth, or ZigBee, or a custom protocol. The radio transmits data to the Cloud or through a smartphone or PC.

This device points out the prime challenge to IoT design: analog, digital, RF, and MEMS design domains all live together in one device. IoT design requires that all four design domains are designed and work together, especially if they are going on the same die. Even if the components are targeting separate dies that will be bonded together, designers still need to work together during the integration and verification process. In this design, there are several components in multiple domains, such as the A/D converter, digital logic, a RF radio, a MEMS sensor, and an analog driver that connects to an external mechanical actuator. The design team needs to capture a mixed analog and digital, RF, and MEMS design, perform both component and top-level simulation, layout the chip, and verify the components within the complete system.

The Tanner Solution

The Tanner solution delivers a top-down design flow for IoT design, unifying the four design domains (Figure 2).

Figure 2: The Tanner IoT design flow.

Whether you are designing a single die or multiple die IoT device, you can use this design flow for creating and simulating this device:

  • Capturing and simulating the design. S-Edit captures the design at multiple levels of abstraction for any given cell. Each cell can have multiple views such as a schematic, RTL, or SPICE and then you choose which view to use for simulation. T-Spice simulates SPICE and Verilog-A representations of the design while ModelSim simulates the digital, Verilog-D/RTL portions of your design.
  • Simulating the mixed-signal design. S-Edit creates the complete Verilog-AMS netlist and passes it to T-Spice. T-Spice automatically adds Analog/Digital connection modules and then partitions the design for simulation. T-Spice simulates the analog (SPICE and Verilog-A) and sends the RTL to ModelSim for digital simulation. Both simulators are invoked automatically and during simulation the signal values are passed back and forth between the simulators whenever there is a signal change at the analog/digital boundary. This means, that regardless of the design implementation language, you drive the simulation from S-Edit and the design is automatically partitioned across the simulators. Then, you can interact with the results using the ModelSim and T-Spice waveform viewers. Behavioral models of MEMS devices can be created in Verilog-A or as equivalent lumped SPICE elements that are simulated along with the digital models for system-level verification.
  • Laying out the design. The physical design is completed using L-Edit which allows you to create the layout of the analog and MEMS components for the IoT design. The parameterized layout library of common MEMS elements and true curve support simplify the MEMS layout.
  • Completing the flow. Of course, there are other steps in the flow, such as digital synthesis, digital place and route, chip assembly, physical verification, static timing analysis, and full system verification. However, these steps are beyond the scope of this discussion.

Implementing the MEMS Device

One of the most challenging aspects of IoT design is implementing the MEMS device. So, in this article we focus on the physical design flow for this device. Let’s say that the MEMS device in our design is a magnetic actuator. A magnetic actuator is comprised of a coil and a moving paddle. The paddle is suspended by a spring. When current is sent through the coil, a magnetic field is created which moves the paddle in and out of the coil field (Figure 3).

Figure 3: MEMS magnetic actuator.

You could create a 3D model of the magnetic actuator using a 3D analysis tool and then analyze its dynamic response to different currents. To fabricate the actuator you need a 2D layout mask and deriving a 2D mask from a 3D model is error-prone and difficult to validate. A better approach is to follow the mask-forward flow that Figure 4 shows, that results in more confidence that the actuator will not only work correctly but that it can be successfully fabricated.

Figure 4: The mask-forward MEMS design flow.

The mask-forward MEMS design flow starts by creating the 2D mask layout in L-Edit. Then, use the SoftMEMS 3D Solid Modeler (integrated within L-Edit) to automatically generate the 3D model from those masks and a set of specified fabrication steps. Perform 3D analysis using your favorite finite element tool and then iterate if you find any issues. Make the appropriate changes to the 2D mask layout and then repeat the flow. Using this mask-forward design flow, you can converge on a MEMS device that you are confident can be fabricated correctly because you creating the 3D model directly from the masks that will eventually be used for fabrication, rather than trying to work backwards from the 3D model.

Conclusion

The prime challenge of IoT design is working in four design domains: analog, digital, RF, and MEMS. The Tanner design flow is architected to seamlessly work across all of these design domains by employing an integrated design flow for design, simulation, layout, and verification.
For more information about the IoT design flow, see: www.mentor.com/tannereda/mems-design?cmpid=10167

InvenSense CEO touts the Internet of Sensors

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

InvenSense president and chief executive officer Behrooz Abdi sees the Internet of Things as an Internet of Sensors, a theme he explored Tuesday afternoon (November 17) at the opening of the fourth annual InvenSense Developers Conference.

“To enable the Internet of Things, we need a community,” he told the developers in attendance. “How do we make this a much stronger community?”

InvenSense has a “very selfish” reason for supporting the 30,000 developers in that community, Abdi added. Many InvenSense developers of hardware and software applications spread out to many companies, he noted.

The company reported earlier this year that 78 percent of its fiscal 2015 revenue came from mobile sensors. Optical image stabilization accounted for 12 percent of the year’s revenue, while gaming and other applications represented 10 percent.

For its fiscal second quarter ended September 27, InvenSense’s IoT-related business accounted for 20 percent of revenue, “double what it was,” Abdi said.

In its history, InvenSense has seen many functions incorporated into smartphones, the CEO said. “The phone has become a mobile server,” he observed.

Abdi commented, “The road to the Internet of Sensors is fraught with many challenges. We’re really tackling a lot of things.”

InvenSense has reduced the typical time-to-market for new sensor products, especially with its new fingerprint sensor, Abdi asserted. The company has opened up its InvenSense Fabrication Platform to more parties in the interest of inspiring more designs incorporating InvenSense sensors, he said.

“We’re giving you a platform you can build from,” Abdi said.

Eitan Medina, InvenSense’s vice president of marketing and product development, revealed some of the company’s news on Tuesday, such as the new CoursaSports.com software-as-a-service, with a software development kit for sensor-assisted fitness tracking applications, and improvements in the graphical user interface of the company’s SensorStudio development tool and the InvenSense FireFly development kit, a sensor prototyping and development platform for IoT applications.

“Create your own custom sensors,” Medina urged. “Design your own sensor fusion.”

CoursaSports supports app development for the iOS, Android, and Android Wear operating systems, according to Medina.

InvenSense also announced it is partnering with Intrinsic-ID for the TrustedSensor offering, “enabling secure sensor-based systems,” Medina said.

The conference also heard from Amit Shah of Artiman Ventures. “What is IoT?” Shah asked rhetorically. “It sort of became a buzzword that means nothing.”

As a venture-capital firm, Artiman is interested in startups that can field a product or service within two years, Shah said.

“We’re focused on revenue models” when it comes to the Internet of Things and sensors, Shah said – specifically, health care and industrial uses. Artiman isn’t interested in areas that are “crowded” with startups, namely consumer wearables and robotics, he added.

InvenSense Developers Conference Tackles Sensor Security, New Technologies

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.

There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.

The conference also featured two developer tracks in parallel, providing five InvenSense presentations on its FireFly hardware and software, SensorStudio, and other offerings.

One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.

TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.

The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.

Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.

Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”

It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.

While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.

PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”

Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.

Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”

Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.

“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.

“That’s data that can be monetized,” he said.

InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”

The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.

“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.

InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.

Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.

GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.

The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.

STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.

Meeting the IoT Design Challenge

Monday, November 2nd, 2015

thumbnail

By Pete Singer, Editor-in-Chief

Mentor Graphics acquired Tanner EDA in March of 2015, in an effort to better address the design, layout and verification of analog/mixed-signal (AMS) and MEMS ICs, key building blocks in Internet of Things (IoT).

Since then, the Tanner team has moved offices and successfully been integrated into Mentor’s corporate structure.

We recently caught up with Jeff Miller, product marketing manager for the Tanner Group at Mentor Graphics. “We’ve kept the team together and we’re continuing to work as a business unit within Mentor Graphics with the same team under the same leadership,” he said. “Greg Lebsack, who was the president of Tanner EDA is now the general manager of the Tanner Group. We have the same basic org chart.” He noted that the same people who were with Tanner for a long time are still there. “We tried to preserve that and we’ve done a good job of that,” Miller said.

With the explosion of IoT devices – some estimate 70 billion devices will be connected to the internet by 2020 – the Tanner acquisition seems particularly prescient in that many if not most IoT devices are analog/mixed signal devices, and many involve the use of MEMS.

“We’ve been involved in various IoT-type designs for a long time,” Miller explained. He defined an IoT device as a sensor and an actuator — that’s the “thing” part – plus some amount of readout or control circuitry, and some digital logic in order to control that and interface to a radio which then communicates to your cell phone or you WiFi network and then on to the internet. “You need to have all those four pieces to make your IoT device,” he said.

The microcontroller or microprocessor component and the radio component have been traditionally been done outside of the Tanner EDA tools, but Miller said they group has been making a big effort in the last couple of years to bring some of that into their design flow in terms of enabling a greater degree of integration. “The cost, size pressures and power pressures are going to force some integration there,” Miller said.

In other words, sensors are being integrated with more and more of intelligence. “Instead of just having a raw MEMS accelerometer, they’ll have a 3-axis accelerometer with a 3-axis gyro and a read-out circuit and enough digital logic to do some processing,” said Miller. “These sensors are becoming a lot smarter and more integrated in order to support these kinds of applications.”

Miller said he’s seen a lot of new entrants into the IoT market. Typically design teams have5 to 20 people. Tanner’s market historically has been the smaller companies with relatively focused products.

“I’m expecting the needs of this market to be diverse enough that we’re going to see a proliferation of small interesting designs that enable a particular class of IoT device,” Miller predicts. “This proliferation across the market will lead to small design teams doing something innovative in a smaller scale environment, trying to make these things as small and efficient as they can possibly be. “

Since the acquisition, a big focus of the Tanner Group has been on how to best integrate Mentor’s tools such as Calibre, ModelSim and AFS with existing Tanner products. “More so than ever before, we have a complete design flow, start to finish, for analog design flow, mixed signal design and for MEMS design, and any integration across those things,” Miller said. “We’re keeping our basic ways of doing things and leveraging the incredible resources that are available being part of a large company like Mentor Graphics. It’s really good for us to part of this new, larger team.”

The first major integration was with Calibre, followed by ModelSim as the digital simulator in their mixed signal flow. “We can integrate our SPICE simulator with ModelSim and do mixed signal simulations and communicate the signals across the boundary between analog and digital,” Miller said. He adds that expects to have more and tighter integrations with other Mentor Graphic tools moving forward.

“I’ve been really encouraged that Mentor has been investing us and making sure we’re going to be around and still doing business in a Tanner kind of way going into the future,” Miller said.

Next Page »