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Posts Tagged ‘memristor’

Memristor Variants and Models from Knowm

Friday, January 22nd, 2016

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By Ed Korczynski, Sr. Technical Editor

Knowm Inc. (www.knowm.org), a start-up pioneering next-generation advanced computing architectures and technology, recently announced the availability of two new variations of memristors targeting different neuromorphic applications. The company also announced raw device data available for purchase to help researchers develop and improve memristor models. These new Knowm offerings enable the next step in the R&D of radically new chips for pattern-recognition, machine-learning, and artificial intelligence (AI) in general.

There is general consensus between industry and academia and government that future improvements in computing are now severely limited by the amount of energy it takes to use Von Neumann architectures. Consequently, the US Whitehouse has issued a grand challenge with the Energy-Efficient Computing: from Devices to Architectures (E2CDA) program (http://www.nsf.gov/pubs/2016/nsf16526/nsf16526.htm) actively soliciting proposals through March 28, 2016.

The Figure shows a schematic cross-section of Knowm’s memristor devices—with Tin (Sn) and Chromium (Cr) metal layers as the new options to tungsten (W)—along with the device I/V curves for each. “They differ in their activation threshold,” explained Knowm CEO and co-founder Alex Nugent in an exclusive interview with Solid State Technology. “As the activation thresholds become smaller you get reduced data retention, but higher cycle endurance. As that threshold increases you have to dissipate more energy per event, and the more energy you dissipate the faster it will burn-out.” Knowm’s two new memristors, as well as the company’s previously announced device, are now available as unpackaged raw dice with masks designed for research probe stations.

Figure: Schematic cross-section of Knowm’s memristor devices using Tin (Sn) or Chromium (Cr) or tungsten (W) metal layers, along with the device I/V curves for each. (Source: Knowm)

Knowm is working on the simultaneous co-optimization of the entire “stack” from memristors to circuit architectures to application-specific algorithms. “The potential of memristors is so huge that we are seeing exponential growth in the literature, a sort of gold rush as engineers race to design new circuits and re-envision old circuits,” commented Knowm CEO and co-founder Alex Nugent. “The problem is that in the race to publish, circuit designers are adopting models that do not adequately describe real devices.” Knowm’s raw data includes AC, DC, pulse response, and retention for different memristors.

Additional memristors are being developed by Knowm’s R&D lab partner Dr. Kris Campbell of  Boise State University (http://coen.boisestate.edu/kriscampbell/), using different metal layers to achieve different activation thresholds beyond the three shown to date. “She has discovered an algorithm for creating memristors along this dimension,” said Nugent. “From a physics perspective it makes sense that there would be devices with high cycle endurance but reduced data retention.”

“In the future what I image is a single chip with multiple memristors on it. Some will be volatile and very fast, while others will be slow,” continued Nugent. “Just like analog design today uses different capacitors, future neuromophic chips would likely use memristors optimized for different changes in adaptation threshhold. If you think about memristors as fundamental elements—as per Leon Chua (https://en.wikipedia.org/wiki/Leon_O._Chua)—then it makes sense that we’ll need different memristors.”

The applications spaces for these devices have intrinsically different requirements for speed and retention. For example, to exploit these devices for pattern recognition and/or anomaly detection (keeping track of confidence in making temporal predictions) it seems best to choose relatively high activation thresholds because the number of operations is unlikely to burn-out devices. Conversely, for circuits that constantly solve optimization problems the best memristors would require low burn-out and thus low activation thresholds. However, analog applications are generally problematic because the existing memristors leak current, such that stored values degrade over time.

Knowm is shipping devices today, mostly to university researchers, and has tested thousands of devices itself. The Knowm memristors can be fabricated at <500°C using industry-standard unit-process steps, allowing for eventual integration with silicon CMOS “back-end” metallization layers. While still in early R&D, this technology could provide much of the foundation for post-Moore’s-Law silicon ICs.

—E.K.

Knowm First to Deliver Configurable Artificial Neural Networks using Bi-Directional Learning Memristors

Wednesday, September 2nd, 2015

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By Ed Korczynski, Sr. Technical Editor

Knowm Inc., a start-up pioneering next-generation advanced computing architectures and technology, today announced the availability of artificial neural-network (ANN) chips built using memristors with bi-directional incremental learning capability. “We have been dreaming about this device and developing the theory for how to apply them to best maximize their potential for more than a decade,” said Alex Nugent, CEO and co-founder of Knowm. “The problem I set out to solve in 2001 was the massive discrepancy between how computers model brains and how neurons function. This result is truly a monumental technical milestone.”

Memristors with the bi-directional incremental resistance change property are the foundation for developing ANN such as Knowm’s recently announced Thermodynamic RAM (kT-RAM). Intended for high computing power jobs like machine learning (ML), autonomous robotics, and intelligent internet assistants, kT-RAM radically increases the efficiency of synaptic integration and adaptation operations such as pattern recognition and inference. The company has released an API for organizations and individual developers.

The Figure shows how Knowm’s architecture is adaptive, and based on the principle of Anti-Hebbian and Hebbian (AHaH) learning in neurons—following Hebb’s famous observation that “neurons that fire together wire together.” Hebbian learning reduces the synaptic resistance, while anti-Hebbian learning increases the resistance. The adaptive architecture means that thousands of memristors could be connected in parallel to do large-scale pattern recognition, or individual memristors could be mapped into a decision-tree to produce combinatorial optimization.

New “thermodynamic RAM” (kT-RAM) artificial neural network (ANN) architecture from Knowm is inherent adaptive, and built with memristors capable of bi-directional incremental resistance changes for efficient learning. (Source: Knowm)

The most famous ANN chip had been True North, but IBM could not develop memristors technology so that chip uses a fixed architecture with digital SRAM transistor arrays. The use of SRAM arrays means that True North chips require 21 pJ energy per synaptic integration, while Knowm’s memristor arrays can perform the same function with less than a thousandth of the energy (1-10 fJ).

Since the principle of Hebbian-learning is well known, many R&D teams around the world have tried and failed to find a material stack that allows for controlled incremental increase and decrease in resistance. An ideal memristor with the following properties would allow a single 2-terminal device to provide both Anti-Hebbian and Hebbian learning in artificial synapses:

  • BEOL CMOS compatible fabrication,
  • Voltage dependent  and low voltage thresholds of adaptation,
  • Non-Volatile with high cycle endurance,
  • Resistance ranges from ~100kΩ to ~100MΩ, and
  • Bi-directional incremental changes in resistance.

Fortunately, Dr. Kris Campbell of Boise State University had been researching the electronic properties of chalcogenide compounds, and her group was able to find the right material. Working with Knowm on this patent-pending technology, Campbell can create memristors that adjust resistance in incremental steps in both directions, instead of being limited to incremental change in only one direction alternating with a non-incremental “re-set” step. Using voltage pulses nominally 100 ns allows for learning (though shorter pulse lengths also work) using 0.6V to decrease resistance or -0.3V to increase resistance, and then a 20 mV pulse can easily read the learning level. The memristor stack of materials—including a silver layer as source of ions to diffuse through and alter the resistance of the calchogenide layer (still secret)—is only a few tens of nanometers thick, and can be formed in a single physical-vapor deposition (PVD) chamber in a time-scale of minutes.

Knowm has cycled these memristors billions of times, so reliability has been shown and the company is confident that it now has the building blocks in place for the creation of powerful and efficient ANN chips. “This is a low-level resource for adaptive learning,” explained Nugent to Solid State Technology. “It’s important to say that we’re not trying to do what others are doing with digital non-volatile memory. What we started out to do is to use memristors as synaptic connectors.” Earlier this year, Knowm announced the commercial availability of the first kT-RAM products:  discrete memristor chips, a Back End of Line (BEOL) CMOS+memristor service at Boise State, and the first “Knowm Anomaly” application.

Non-Volatile Memory (NVM) using memristors in cross-point arrays for digital Resistance RAM (ReRAM) has been pursued by many companies for many years. While there are inherent specification differences between digital NVM and analog ANN, in general it is more difficult to meet the device requirements for ANN. “In terms of the NVM, I feel pretty good about it already,” said Campbell to Solid State Technology. “Work I had been doing with Air Force Research Lab starting in about 2008 had been studying NVM and cross-point arrays.”

EMC2015 – New Devices, Old Tricks

Tuesday, June 30th, 2015

By Ed Korczynski, Sr. Technical Editor

The 57th annual Electronic Materials Conference (http://www.mrs.org/57th-emc/), held June 24-26 in Columbus, Ohio, showcased research and development (R&D) of new device structures, as well as new insights into the process-structure-properties relationships of electronic devices now running in high-volume manufacturing (HVM) lines globally. A plethora of papers on compound-semiconductor quantum-dots and nanorods, LEDs and quantum-dot detectors, power electronics, and flexible and bio-compatible devices all show that innovation will not slow down despite the limitations of Dennard Scaling and Moore’s Law. With 3D stacking of existing devices on novel substrates an ongoing integration challenge for HVM, the conference also explored substrate engineering and 3D stacking technologies.

CEA-Leti’s “Smart-cut” technology has been used for over 20 years to cleave crystalline layers for transfer and bonding to stack substrate functionalities, such as Silicon-On-Insulator (SOI) wafers. Researchers from Leti looked at the discrete steps involved in the hydrogen implantation, annealing to create the buried plane of micro-bubbles within the crystal, and then the acoustic wave that travels through the plane to complete the cleave. A periodic wave pattern is dynamically generation during cleaving, with the evolving wavefront dependent upon the contribution of all the past fracture fronts to any particular point. The cleaved roughness is related to the speed of the fracture wave moving through the wafer plane, and that depends on the micro-cracks the are originally present due to the micro-bubbles.

Leti researchers also reported on “Copper grain-size effects on direct metallic bonding mechanisms” such as will be used in 3D chip-stacking. The main limitation on the density of 3D copper (Cu) connections between chips is the micro-bump pitch, with Cu-Cu bonds providing both electrical and mechanical connections. Since the grain-size of annealed Cu thin-films depends on film thickness, they used electro-chemical deposition (ECD) to grow two different thicknesses, annealed each at 400°C for 10 hours to allow for maximum grain growth, and then used CMP to get all samples to the same final thickness. The result was fine-grain Cu bumps with 0.6 micron diameter grains, and large-grain bumps with ~2.1 micron diameter grains. With no post-bond-anneal there was significant improvement in bonding strength with fine-grain-structure Cu compared to large-grains, but with post-bond-anneals up to 300°C the grain-size effect was reduced such that all samples approaching the same high levels of bond strength. However, 400°C annealing resulted in a newly observed voiding phenomenon between the Cu and TiN barrier layers, with more voids associated with finer-grains.

Artificial Neural Networks

Researchers from Sandia Labs showed data on multi-level data storage using memristors. Lacking repeatable processes to manufacture memristors, people have used SRAM arrays to build the first Artificial Neural Networks (ANN) such as those commercialized by NeuroMem Inc. However, models indicate that changing from SRAM- to memristor-arrays would reduce power by 16x and chip area by 6x (assuming 25,600 elements). Sandia has been working with TaOx (where 3 < x < 5) as the memristor switching layer, and has been able to show up to 5 discrete High Resistance States (HRS) to be able to do multi-bit storage in a single cell. For multilevel switching, the standard deviation of a target resistance increases with increasing resistance (not with the magnitude of the resistance change). However, each cell was only cycled 25-50 times, so reliability/wear-out has not yet been explored.

IBM Almaden Labs began work on Phase-Change Memory (PCM) with Macronix and Qimonda in 2004, and recently have explored PCM to build ANN. They sacrifice density and double up the artificial synapses to separately encode excitory and inhibitory functions. In PCM it is easy to slowly step up the High-Resistance State (HRS) levels since a crystalline plug is the Low Resistance State (LRS) and gradual crystallization of the edges of the plug gradually increases resistance, while reset back to LRS either happens on doesn’t across the entire plug so there is an inherently asymmetrical response. For Resistance RAM (ReRAM) structures there is opposite asymmetry in that the conductive filament either forms or doesn’t, while reset to LRS can happen gradually. These asymmetries  in the inherent dynamic responses of artificial synapses result in problems for learning/programming of ANN since ideal learning calls for slight increases and decreases in resistances.

—E.K.