by Ed Korczynski
Lithography is where design meets manufacturing, and so the SPIE Advanced Lithography (AL) conference this year was where Applied Materials and Magma Design Automation chose to launch their new collaborative solution to the problem of managing yield data when ramping the most complex ICs in high-volume manufacturing (HVM). As device features continue to shrink ever smaller than the 193nm of ArF steppers, process windows continue to shrink to reveal complex interdependent yield loss mechanisms. Add in new materials and evolving device structures, and the industry must be able to learn quickly about new yield-loss mechanisms and then efficiently pass that learning back to designers.
In an exclusive meeting with SemiMD during SPIE, representatives of the two companies explained that this new effort is not directed toward solving random yield defects—due to particles for example—but systematic defects due to intrinsic process-design interactions. With ever smaller process windows and interdependencies, maintaining past yields with established design-rule check (DRC) software, “isn’t possible without new methodology,” explained Erez Paran, Applied Materials’ Integrated Solutions Manager, Process Diagnostics and Control. “This solution is intended to enable manufacturing below the 20nm node.”
The companies report seeing a growing gap between simulation and actual manufacturing data. Even with the best optical-proximity correction (OPC) and other reticle-enhancement techniques (RET), masks still have yield-loss “hot spots” when printed into resist in real fabs. Consequently, unlike the traditional way of doing pre-tapeout simulation, this simulation is post-tapeout to be closer to real fab results. GlobalFoundries has reportedly been working with this for over a year now.
Yield management in deep-sub-micron IC fabs only gets more challenging. The traditional method of “binning” yield loss mechanisms starts to fail when the number of bins explodes, and just because a bin appears more frequently does not mean it will be the most critical. As an almost trivial example, post-OPC masks today include “dummy structures” that can short together without loosing any yield. Not all functional paths can be considered to be critical paths, and sorting the critical from the non-critical is one of the key filters to manage the data volume. The software dashboard provides automated visualization tools to overlay inspection data on design information (figure).
Applied and Magma use the Knights Data Base (KGD) as the foundation for managing yield in 20nm node and beyond ICs (source: Applied Materials)
The inspection data shows geometries where there are particular process window limits. Since the limit is systematic and the process is necessarily inflexible, the only possible fix must come from the design using something like additional OPC. With proper data management, the information can be fed further backward within the EDA flow to modify the library level for additional designs. “So it’s sort of short-loop for immediate work, and helps designs go faster for future products in the same process node,” explained Paran.
Knights Data Base (KDB)—part of Magma since the 2006 acquisition of Knights Technology—is the foundation of this new yield management solution. “It’s not only a depository, but a well mined and well correlated data base at the bottom of it all,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit, “and that’s what makes our solution unique. There’s a lot of input from Applied Materials to this, it’s not just cobbling the two companies’ stuff together.”
The smallest pixel in the inspection tool is ~100nm today, and since some fabs are engaged with 20nm node pilot work, Erez explained that, “if you look at the number of structures you have today there can be five. So it becomes a matter of image processing, algorithms, search-engines, correlation-engines.”
The data base can compare inspection information to more than just a GDSII mask layout, including netlist levels. “Today, there is no single-pattern that can reflect the whole design, so it’s becoming more and more difficult,” said Oberai. “We can overlay the defect map on the layout map, and the layout map is now hierarchical and enriched with critcal path information.”
New fabless business models
When is a design closed? It used to be that passing DRC for a given process-design kit (PDK) meant that a chip should yield. Now the industry faces a time of complexities when designs to be modeled rely on multi-variate simulations based on statistics with varying degrees of confidence.
If following the PDK is necessary but not sufficient, then how can a small team of fabless designers get their chip to yield in a fab? “You can see a new market emerging of small and medium sized companies taking new designs and mediating or cleaning them for manufacturing,” explained Oberai. “You see many more starts ups at the chip level, the entry barrier is becoming lower.” However, the cost to get a lithography mask-set written for advanced IC manufacturing is still probably a million dollars.
Once all these changes have been absorbed, it will invariably be time for yet additional methodology innovation to manage ever increasing yield complexity. “Geometries are not going to stop shrinking, says Oberai, and expects only more data streams to be managed since, “Insitu sensor technologies will take a greater role so we can have predictive data.”