By Ed Sperling

Synopsys signed a definitive agreement to buy Magma Design Automation for $507 million, or $7.35 per Magma share, strengthening its hand in both the analog and digital tools and yield management markets.

Magma had been struggling for years, but over the past several years had expanded its portfolio to include advanced digital tools,analog design automation, one of the thorniest issues for shrinking features at each new process node, and into the manufacturing yield arena, where it struck an alliance with Applied Materials involving CAD and inspection systems for faster yield ramp.

John Chilton, senior vice president of marketing and strategic development at Synopsys, said that the real benefit of this acquisition is faster time to market for customers. “What we get is the ability to accelerate development,” he said. “We really are getting more requests for more technology. Deep-submicron CMOS is very complex in terms of materials, the number of transistor and the parasitics. Tools have to do more.”

He noted that Synopsys could have developed these capabilities internally, but it would have taken longer and cost more money than what it will achieve by buying Magma.

Phil Bishop, corporate vice president of worldwide marketing at Magma, said the combination makes a lot of sense. “On the digital side, we have both been working to advance customers to 28nm. The second piece is analog, and we have products that are extremely complementary to Synopsys and which have been doing very well in the market.”

Interestingly, Magma was the last completed IPO before the 2001 recession. Apache Design filed for an IPO in May, but was purchased by ANSYS before the actual public offering.

Both companies will continue to operate independently until the deal is finalized.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president of marketing at Kilopass. What follows are excerpts of that conversation.

SMD: Does a multi-foundry strategy work? And are there problems moving a design from one foundry to the next?
Murphy: There are definitely problems moving from one foundry to another. You need to look at where the handoff makes sense. Is it the ASIC model, or is it an implementation path into each one? If it’s the implementation path, then there is the ability to multisource to different manufacturing lines. When you try to do that at the GDS II level it becomes much more difficult because there’s differentiation in the foundries at the process level, which gets reflected in the GDS II.
Ng: It is difficult to multisource if you’re using those foundries that don’t want you to multisource. If you look at the reasons companies want to multisource, it typically involves assurance of supply. Those are usually the large customers. What’s required is a common process, a common DRC deck and common tech files with regard to design enablement, and then you need common IP. You build your design and come out with one GDS II. It’s not just a common process, though. It’s a fab-sync program. You need to make sure you’re within a certain level of tolerance. We’ve done this in the Common Platform. When you look at customers dictating their own process spec, it kind of works in the same way. But it certainly requires a lot more work on the part of the fabless companies to try to align manufacturers that are not naturally aligned. That requires a lot more work and coordination.
Buehler-Garcia: I would argue those customers aren’t really fabless. They’re IDMs without a fab, or fab-lite. When I was at Chartered we had a couple customers with more device engineers than we had at Chartered. They were looking for capital coverage by the foundry.
Ng: There are fewer and fewer of those customers. That’s a custom development. The ROI that a foundry has to get on the special custom development has to be quite significant.

SMD: Is there any change on the IP?
Hong: That’s one of the unique changes. You have to be a large IDM to have all the IP port from one foundry to another. But ecosystems are being built—GlobalFoundries has its Global Solutions and TSMC has its ecosystem. IP has been enabled where it’s pin-compatible. The internals of the GDS has to be the same to enable going from the Common Platform to other baseline manufacturing.
Ng: That’s a different level of multi-sourcing effort. That effort introduces risk, time-to-market challenges, and additional cost. It also was more common at the older nodes—180nm and 130nm—where you could do that without too much risk. At the newer nodes, the level of difficulty of doing this ‘rip and replace’ is not easy and it’s riskier. The process technologies are much more different at the leading edge. To rip and replace at 28nm is not realistic.
Hong: Up to 40nm, they have looked similar. At 28nm, with high k/metal gate, there is a divergence into two camps. But I believe there will be a convergence again.
Smith: We certainly see a big effort to not get too reliant on one supplier, especially where you’re looking at volumes in the millions. You may have the market and the know-how, but if you’re at the mercy of one supplier you can be in trouble. And it may not be just because of business. Look at what happened recently in Japan. There are no major foundries in northern Japan, but the supply chain for automobiles, for example, has really been impacted. But I’m also skeptical that one size fits all and that you can move stuff around because business dictates that the foundries differentiate. Maybe that’s the platform, but most companies will gravitate toward a secret sauce, whether it’s design rules, IP or something else.
Ng: I have been in a forum where someone accused GlobalFoundries of differentiating just because it can differentiate. That’s not even close to the case. If you look at the 28nm technology today and the development alliance we’re in with seven other companies, we came out with a statement about high k/metal gate even before others in the industry such as TSMC. They kept saying high k/metal gate was not necessary and exotic, and now they’re trying to rewrite history. We still believe our 32/28nm decision on gate first was the right decision for that technology node. There’s a 10% density advantage and there are some power advantages. When customers move from 40LP to 28LP, their design style is not impacted nearly to the degree that a gate-last process requires. The decision we’ve made on 20nm is a node-by-node decision. We’ve saved the customer the impact of one technology node.
Buehler-Garcia: Multi-sourcing depends on who you are and where you are. If you look at the ecosystem, our solutions have to consider all the different options. That’s all the way from a fab-lite company that can drive its own processes to a startup. You need a flow and design process that takes them there step by step. Plus, you have to look at what multi-sourcing means. Everything isn’t a single chip. The big guys are going to tape out 40 or 50 designs. They’re going to give 10 to one foundry and 10 to another foundry. That’s not all bad because too much of any one company is not a good thing for a foundry. The company can move somewhere else. What’s changed is that differentiation is no longer in tweaking the process. People now have to differentiate with the design, and that’s good for the ecosystem. There’s no canned answer of how you do this. If you put 10 customers in a room, their perception of what is multi-sourcing would be different. But they do want a system, a flow, the tools and the IP to let them do this.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general manager of the Fab Analysis Business Unit at Magma Design Automation. What follows are excerpts of that conversation.

SMD: Does a shortened time-to-market deadline require more DFM or less?
Tabery: If it’s so short, then the ramp is just as important. The ramp is usually proportional to peak yield.
Benware: That’s why we’re addressing the cycle time for implementing DFM. It’s real-time verification while you’re drawing the polygons. But when we implemented that, the customers used the extra time to do more DFM. They didn’t change the tapeout time. As you improve DFM, you see people doing more within that window. The other challenge is that you have all these rules, but it’s hard to quantify which ones you should do. How much will your yield change if you follow a particular rule?
Tabery: It’s expensive to do it. So it comes back to the same cost question. There is uncertainty in DFM rules. The base rule is 20 and we’re debating for the DFM rule to be 26 or 28. We’re thinking about characterizing that slope of yield versus closure. But you’re talking about parts-per-billion failure rates, so you need to make billions and billions of these vias to check whether that adds 1% yield and it isn’t worth it or whether it adds 10% yield and it is worth it. Characterizing that roll-off curve is fundamental. But how do you bring those all together to have a useful model and to be able to synthesize that into a design rule. Uncertainty is expensive, but it’s also expensive if you can’t get your yield up faster. Both inspection and the EDA community can help us determine whether it should be 26 or 28 for that recommended rule.

SMD: From the equipment side, is there more influence from the design side or the foundries as we move to advanced nodes?
Conley: I’m not sure it changes. The restrictive design rules today involve the pitches in logic to make them more uniform. These are gridded design rules. This helps inspection because everything becomes uniform. The tools can find the defects more easily. The challenge we see is the complexity of recipe creation, which is why we are bringing design into the fabs. The foundries have a huge number of products and they do need to inspect every product because each product is from a different fabless company. They need to create a recipe for every product. They have numerous memory areas, and these can be identified ahead of time if we have the design built. This is what we’re doing with Magma.
Oberai: The users don’t want recipe creation as a manual process anymore. It’s too complex. They want some correlation to design geometries for incoming designs. They have to create hundreds and hundreds of recipes.

SMD: How does 3D stacking affect yield?
Conley: It’s a totally new game. You invest all the cost in working die, and you have two or more working die, and in the process of stacking you can encounter problems and lose everything.
Benware: The biggest challenge in 3D stacking is in test. How are you going to test these devices and make sure that two devices that were tested independently will work when you bring them together? And once you bring them together, how do you test each device individually. The challenge isn’t yield. It’s test to get to yield.
Tabery: We have packaging yield. We have models for that to know how it works. Putting two chips together is another process step and you have to understand the yield for that, but the yield targets would be very high because it’s using die that are already qualified and tested. The testability of that is interesting. How many TSVs do you need to test?
Oberai: We are seeing more and more of that. We are moving from die- or wafer-level navigation to board-level navigation. We put the whole board in a TM. Customers want to test the whole board. You test what the interconnectivity is. There are software capabilities to model this. It includes leakage and durability of connectors and what are the other effects of powering up the whole board or stacked die. But there isn’t anywhere near the level of tools for stacked die that we have on a single die.

SMD: There’s also a push to thin out the wafers in stacked die. How do you deal with that?
Tabery: It’s thinned out after the processing, so the impact on wafer processing is small. But there are additional mechanical and packaging challenges.
Oberai: It’s more the mechanical aspects.

SMD: Doesn’t that create more defects?
Tabery: It certainly could. You polish on the back side so that’s less risky, but if you induce a crack or there’s new stress that isn’t modeled, you need to understand that. The TSVs cause huge stress fields around the transistors. If the ones to the right of the TSV are slow but the ones just above the TSVs are fast, that’s no good.

SMD: 3D also blurs the lines across the supply chain. Who’s responsible for problems in complex chips and how do you deal with these problems?
Conley: The partnership between Applied Materials and Magma is part of this answer. There needs to be more partnerships between companies to solve critical issues. You need to take the advantages of each company and try to creation solution that is greater than the sum of both parts.
Oberai: In our partnership we are the ones creating the framework for the data depository and correlation and creating recipes and then sending it to the tool. The onus is on us to make sure the recipe generation has taken into account all the different elements. But we are heavily reliant on the tool providing all the parameters. Hopefully, when that happens there is alignment. We build a golden-case model to run sample recipes. If the recipe works we need to calibrate how long before we need to model again. The collaboration between companies is critical. The timekeeper is the customer or the fab. There are a lot of metrology tools and they are signaling these things. You never saw this kind of cooperation before. The onus is on all sides. There is enough harmony in this business to make this work. This is going to be an incremental process, though.
Benware: There’s a requirement for more interaction. We have to partner with our customers to be successful. While we see that test, manufacturing and design need to be linked, where we see the biggest challenge is in ownership of data. Somebody owns the data and someone else needs that data. Between the fabless company and the foundry, on the design side you have all this data and that needs to go to the fab somehow so they can do their process tuning and inspection based on the design. And it’s no longer just GDS. There are parametric and timing issues, so there’s more design data that has to go. At test you collect a whole bunch of failure data. Who owns that data? Someone had to take the wafer and scrap the wafer. Who owns that scrap wafer? Once you have the test data, you have to do yield analysis and that’s design information again. The fabless company owns the design information but it’s the fab that has the result. Where the data exists and how to transfer it between companies between exists today.

SMD: Isn’t that a mindset change?
Benware: Yes. There are IP concerns, too. Even if the data is encrypted, people don’t trust the encryption. And it’s multinational, so there are concerns with that. Even though vendors are providing these kinds of capabilities, one of the biggest challenges to the industry adopting it are overcoming IP and data-sharing hurdles that people are slow to solve.
Oberai: Even if there is a defect the foundry won’t give us the defect. You have to go down and look at it. They think, ‘What if it has something to do with a design customer?’ There’s not much you can do with a defect. But there are a lot of constraints on data.
Benware: A few years back we were seeing a lot of resistance to adopting diagnosis and volume at fabless customers because they couldn’t figure out who would pay for the tools and who would use the data. Over the past few years we’ve seen that perception of an IP issue completely evaporate when there is a yield problem. These companies are sending the foundry absolutely everything. They don’t want to put anything in place ahead of time, but when the problem comes it’s like grease. People have experienced that enough that they’re starting to overcome their issues. That’s a testament that yield is a big problem and the foundry and the fabless companies are in this together.
Oberai: It’s all about yield.

What makes one semiconductor design yield better than another. And what issues are we likely to face going forward. Semiconductor Manufacturing & Design questions Amiad Conley from Applied Materials; Cyrus Tabery from GlobalFoundries; Brady Benware from Mentor Graphics, and Ankush Oberai from Magma.

by Ed Korczynski

Lithography is where design meets manufacturing, and so the SPIE Advanced Lithography (AL) conference this year was where Applied Materials and Magma Design Automation chose to launch their new collaborative solution to the problem of managing yield data when ramping the most complex ICs in high-volume manufacturing (HVM). As device features continue to shrink ever smaller than the 193nm of ArF steppers, process windows continue to shrink to reveal complex interdependent yield loss mechanisms. Add in new materials and evolving device structures, and the industry must be able to learn quickly about new yield-loss mechanisms and then efficiently pass that learning back to designers.

In an exclusive meeting with SemiMD during SPIE, representatives of the two companies explained that this new effort is not directed toward solving random yield defects—due to particles for example—but systematic defects due to intrinsic process-design interactions. With ever smaller process windows and interdependencies, maintaining past yields with established design-rule check (DRC) software, “isn’t possible without new methodology,” explained Erez Paran, Applied Materials’ Integrated Solutions Manager, Process Diagnostics and Control. “This solution is intended to enable manufacturing below the 20nm node.”

The companies report seeing a growing gap between simulation and actual manufacturing data. Even with the best optical-proximity correction (OPC) and other reticle-enhancement techniques (RET), masks still have yield-loss “hot spots” when printed into resist in real fabs. Consequently, unlike the traditional way of doing pre-tapeout simulation, this simulation is post-tapeout to be closer to real fab results. GlobalFoundries has reportedly been working with this for over a year now.

Yield management in deep-sub-micron IC fabs only gets more challenging. The traditional method of “binning” yield loss mechanisms starts to fail when the number of bins explodes, and just because a bin appears more frequently does not mean it will be the most critical. As an almost trivial example, post-OPC masks today include “dummy structures” that can short together without loosing any yield. Not all functional paths can be considered to be critical paths, and sorting the critical from the non-critical is one of the key filters to manage the data volume. The software dashboard provides automated visualization tools to overlay inspection data on design information (figure).

Applied and Magma use the Knights Data Base (KGD) as the foundation for managing yield in 20nm node and beyond ICs (source: Applied Materials)

The inspection data shows geometries where there are particular process window limits. Since the limit is systematic and the process is necessarily inflexible, the only possible fix must come from the design using something like additional OPC. With proper data management, the information can be fed further backward within the EDA flow to modify the library level for additional designs. “So it’s sort of short-loop for immediate work, and helps designs go faster for future products in the same process node,” explained Paran.

Knights Data Base (KDB)—part of Magma since the 2006 acquisition of Knights Technology—is the foundation of this new yield management solution. “It’s not only a depository, but a well mined and well correlated data base at the bottom of it all,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit, “and that’s what makes our solution unique. There’s a lot of input from Applied Materials to this, it’s not just cobbling the two companies’ stuff together.”

The smallest pixel in the inspection tool is ~100nm today, and since some fabs are engaged with 20nm node pilot work, Erez explained that, “if you look at the number of structures you have today there can be five. So it becomes a matter of image processing, algorithms, search-engines, correlation-engines.”

The data base can compare inspection information to more than just a GDSII mask layout, including netlist levels. “Today, there is no single-pattern that can reflect the whole design, so it’s becoming more and more difficult,” said Oberai. “We can overlay the defect map on the layout map, and the layout map is now hierarchical and enriched with critcal path information.”

New fabless business models

When is a design closed? It used to be that passing DRC for a given process-design kit (PDK) meant that a chip should yield. Now the industry faces a time of complexities when designs to be modeled rely on multi-variate simulations based on statistics with varying degrees of confidence.

If following the PDK is necessary but not sufficient, then how can a small team of fabless designers get their chip to yield in a fab? “You can see a new market emerging of small and medium sized companies taking new designs and mediating or cleaning them for manufacturing,” explained Oberai. “You see many more starts ups at the chip level, the entry barrier is becoming lower.” However, the cost to get a lithography mask-set written for advanced IC manufacturing is still probably a million dollars.

Once all these changes have been absorbed, it will invariably be time for yet additional methodology innovation to manage ever increasing yield complexity. “Geometries are not going to stop shrinking, says Oberai, and expects only more data streams to be managed since, “Insitu sensor technologies will take a greater role so we can have predictive data.”