By David Lammers

Soitec (Bernin, France) announced that ST-Ericsson will use planar fully depleted silicon on insulator (FD-SOI) technology in future mobile platforms, including the NovaThor SoCs used in smart phones. Compared with conventional bulk CMOS, 28nm FD-SOI technology provides 35 percent lower power consumption at maximum performance, resulting in mobile systems with four additional hours of Web browsing or as much as a day of additional battery life, Soitec said.

ST-Ericsson has delivered its NovaThor mobile platform solutions to Nvidia and other smart phone providers. Louis Tannyeres, chief chip architect at ST-Ericsson, said “together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with STMicroelectronics on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions.”

Soitec COO Paul Boudre said ST-Ericsson’s decision represents the industry’s “first step toward fully depleted planar CMOS technology, years ahead of when alternative processes will be available from foundries.”

FD-SOI allows semiconductor vendors to deliver power and performance advantages similar to those achieved with vertical, finFET transistors, with less manufacturing complexity. While foundries have plans to move to finFETs at the 14nm node, the FD-SOI technology is available now, at the 28nm generation, with minimal design changes from bulk CMOS technology.

With wafer production facilities in Bernin, France, and Singapore, Boudre said Soitec can meet the high-volume SOI wafer needs of the mobile market. To support fully depleted technology, the active silicon layer must be kept to 10 nm or less, on top of a thicker buried oxide layer which prevents current from leaking out. Other wafer manufacturers, including MEMC and SEH, have licensed Soitec’s Smart Cut technique for creating the SOI wafers.

Processors built on a fully depleted SOI technology can achieve 60 percent higher peak performance. Relatively high performance also is possible at very low operating voltages in the sub-0.7V regime, he said.

STMicroelectronics said at the International Electron Devices Meeting (IEDM) last December that it is implementing mobile applications processors in a FD-SOI technology, using 28nm design rules. It has developed back bias techniques which allow the chip to switch between power-saving and performance modes which are not available with FinFETs.

Joël Hartmann, STMicroelectronics assistant general manager of technology R&D, said STMicroelectronics and partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology. “ST has recently demonstrated the strong differentiation of this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28nm and below,” Hartmann said.

(Source: Symposium on VLSI Technology).

By David Lammers

The late September news of the G450C collaborative effort swept over the Atlantic like a tsunami, starting in Albany, N.Y., and washing up on the Semicon Europa conference, where speakers questioned how European suppliers would be linked in to the Albany-based effort. With a vibrant equipment and materials industry, Europe seeks to play an active role in a transition being managed far from its shores. The issue is complicated by the lack of a single Europe-based IC vendor ready to embrace the larger wafers.

The Global 450 Consortium based in Albany, N.Y. (G450C) plans to have 50 tool types installed at its pilot line in the next few years, said Tom Jefferson, in charge of the ISMI 450 program which is being rolled into the G450C consortium. The G450C pilot line will swing into action in the second half of 2013 and 2014, with demonstrations targeted at “the 1X node.”

(Source: ISMI presentation at 2011 Semicon Europa)

At Semicon Europa, held in mid-October in Dresden, Germany, Jefferson said G450C  will provide “centrally aligned requirements” to suppliers, including a “well-defined method of testing tools and data sharing with the device makers which avoids duplication of data generation.”  (The following week, during ISMI Manufacturing Week in Austin, Texas, the 450mm equipment testing parameters were described at an all-day seminar.) The initial patterning will be performed by an EV Group 770 nanoimprint tool, now being modified at the EVG engineering center in Austria to handle the larger wafers.

Tom Jefferson

While stopping short of saying suppliers would be shut out from purchase orders if they fail to participate in the G450C effort, he said those vendors would receive “a lower priority.” With Jefferson holding out several carrots to the equipment and materials providers to participate, the equipment makers are still looking for assurances on timing as well as financial support.

Asked whether EUV would be a gating factor for 450mm development, Kirk Hasserjian, vice president of strategic programs at Applied Materials, said a successful transition to 450mm “has more to do with the sharing of risk” than whether 450-capable EUV tools are available. “The seeds are in place in New York for better collaboration. Hopefully, there will be some sort of cost sharing and risk sharing going forward.”

He said wafer fab equipment sales are “whiplashed by GDP fluctuations,” and called for “a synchronized transition to 450mm in terms of high-volume manufacturing,” and “a clear, published strategy by the litho suppliers.”

The 450mm progress review sessions at Semicon Europa, organized by Lothar Pfitzner of the Fraunhofer IISB, included 21 presentations over two full days. Jefferson kicked things off by telling the largely European audience that G450C welcomes participation by the European equipment and materials (E&M) industry, which accounts for a surprising 20-25 percent of the worldwide market (led by ASML). “I want to encourage equipment suppliers to participate,” Jefferson told the Semicon Europa audience, adding that they would have access to patterned and unpatterned wafers, shared metrology tools, shipping containers called MACs, and access to the engineers assigned to the G450C by the five device makers – IBM, Intel, GlobalFoundries, Samsung, and TSMC. For European equipment makers not able to ship a tool to Albany, Jefferson said that “participation does not necessarily mean that a tool must be on-site. We need to work out the details” on remote links.

Georg Kelm

Georg Kelm, head of the nanoelectronics sector at the European Commission, summed up the bifurcated European attitude to the 450mm transition: “The (European) materials suppliers are ready to join. The equipment suppliers are equally active, with a proactive attitude. But the IC manufacturers have made no commitments – not yet.”

While much of the EU’s research has gone towards the “More Than Moore” sectors of MEMS, LEDs, photonics, and related subjects, Kelm warned that a successful More Than Moore strategy depends on leading-edge fabs being started for “More Moore” device scaling.

“It would be a mistake to separate More Than Moore and More Moore,” Kelm said, adding that More Than Moore “will not provide a long holiday” for the European semiconductor industry. Much of the effort to link devices with 3D interconnects will end up being done on 450mm wafers, for example.

Kelm said that tool vendors at some point will stop developing new technologies on 300mm platforms. “The 8nm node likely will be for 450mm equipment the equivalent of 65nm for the 300mm equipment. That is when new technologies were 300mm only,” he said. And he predicted that all “post CMOS” manufacturing will be on 450mm tools.

“In 15 to 20 years even the mature technologies will be on 450mm,” Kelm said, adding that “it is possible that some product categories may never be produced in 450mm; however, provided volumes are there, even MEMS, specialized technologies and power could be made on 450mm wafers.”

However, public funding from the European Union cannot be divided long between 300mm and 450mm platforms – there is not sufficient money for that. And he noted that the European equipment and materials vendors – eager to remain competitive with 450mm offerings – employ more people in Europe than the European device makers, including STMicroelectronics, Infineon, and NXP Semiconductors.

“One of the three indigenous IC vendors definitely has to go to 450. The other possibility is that one of the inward investors – Intel or GlobalFoundries — will go to 450 millimeters,” Kelm said.

Hans Lebon, Imec’s vice president in charge of fab and process step development, said “all innovation will move to 450mm, though not in the next two nodes. Ten nanometer technology and beyond will largely be developed on 450, and 300mm will no longer be cost effective.”

Imec will develop the main 450mm process modules at an expanded cleanroom in Leuven, Belgium. Epitaxial deposition, atomic layer deposition, front-end-of-the line critical cleaning, lithography, and dry etching steps all will be developed on 450mm equipment at Imec, Lebon said. “We have a tremendous amount of work to do in a reasonable time frame to keep costs under control,” he told the Semicon Europa audience.

Michel Brillouet, senior advisor at CEA-Leti, predicted that by the 8nm node that some logic vendors will adopt a heterogeneous CMOS technology, in which a III-V material is used in the NFET channel and perhaps germanium in the PFET channel. By the 8nm node the MPU makers, for example, will not be using the same toolset employed today, he said.

Predicting that 450mm would reach volumes in 2018, Brillouet said it is likely that the semiconductor industry will be spread out over various technology generations then. One possible scenario, he said, is that MPU makers would be at the 8nm generation, foundries at 14nm, flash at 11nm and DRAM at 16nm. Leti will continue to work closely with Soitec, Mapper, and other vendors, cooperating closely with Imec on 450mm modules not available at the Leti research facilities in Grenoble.

Heinz Kundert, president of SEMI Europe, said about 40 European suppliers have participated in the EU-based EEMI 450 Initiative. A March 2011 SEMI Europe survey showed that half of the equipment and materials respondents said 450mm was “very important to my company.”

Synopsys, Inc. has joined the IMAGINE program based at CEA-Leti designed to develop maskless lithography for IC manufacturing, becoming the tenth industrial partner to join the program.

CEA-Leti and MAPPER Lithography launched the program in July 2009 with the delivery of MAPPER’s Massively Parallel Electron Beam Platform to Leti. The program provides the world’s major chip manufacturers with the opportunity to assess maskless lithography technology in a real manufacturing environment. In addition, it will develop and qualify the complete infrastructure, from data preparation to process integration, in preparation for its industrial introduction in 2015.

“Maskless lithography has emerged as a contender for extending IC manufacturing to technology nodes below 15 nanometers,” said Fabio Angelillis, vice president engineering of the Silicon Engineering Group at Synopsys. “Synopsys is pleased to contribute its technology in mask tools, including mask synthesis and mask data preparation, to help drive effective software solutions for the IMAGINE program.”

“One of the key points for the ML2 technology is the ability to handle very large data files, and we will need to quickly establish the proper data format standard,” said Serge Tedesco, CEA-Leti program manager. “Having Synopsys’ extensive experience in helping define data format and solutions to related issues will be essential to our success.”

CEA-Leti (Grenoble, France) said a team of European researchers and companies has demonstrated a silicon-based 40-Gbit/s optical modulator with a record extinction ratio of 10dB (the power difference between the 1 and 0 data levels).

The Helios project members are continuing to design and fabricate the entire chain of silicon photonics devices, including a 16×10 Gb/s transceiver, a photonic QAM-10Gb/s wireless transmission system, and a mixed-analog and digital-transceiver module for multifunction antennas.

Designed and characterized by staff in the Silicon Photonics Group at the Advanced Technology Institute, University of Surrey, UK, the modulator circuit was fabricated in a CMOS-compatible process by Leti, which is coordinating the project. The Helios partners will present the results at the 8th International Conference on Group IV Photonics in London, Sept. 14-16.

‘This result is a major step towards high-bandwidth optical systems on silicon because it makes 40Gb/s modulators viable for commercial applications,” said Graham Reed, professor of silicon photonics at the University of Surrey.

Silicon photonics has generated growing interest for optical telecommunications or for optical interconnects in microelectronic circuits. CMOS photonics may lead to low-cost solutions for a range of applications such as optical communications, optical interconnections between semiconductor chips and circuit boards, optical signal processing, optical sensing, and biological applications.

The 22^nd IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2011) will feature a panel discussion on “Models for Successful Partnerships in Semiconductor Manufacturing” April 17 in Saratoga Springs, N.Y.

The panel session will highlight the vital role of partnerships in furthering semiconductor manufacturing innovation and advancements.

Panelists will examine how to collaborate across the semiconductor development and manufacturing supply chain. The panel includes:

• Dr. Walid Ali, Advanced Technology Investment Company (ATIC)
• Olivier Demolliens, CEA-Leti
• Prof. Michael M. Fancher, College of Nanoscale Science and Engineering (CNSE)
• Ari Komeran, Intel Corporation

CEA-Leti and InfiniScale S.A. will jointly tackly issues related to process-variability management in SOI sub-28nm devices. InfiniScale, a provider of model-based parametrical yield analysis and optimization for analog and mixed-signal designs, will provide its Lysis platform for modeling and yield optimization of design-kit libraries. The Grenoble-based company also brings its know-how on development of a next-generation global solution dedicated to overcoming process variability challenges from front end to back end.

The partnership will tap Leti’s design and technological expertise and provide InfiniScale access to Leti’s fully depleted silicon on insulator (FD SOI) technology to validate InfiniScale tools with measurements on silicon.

“This collaboration stems from CEA-Leti’s recent decision to offer the design community access to our FD SOI technology,” said Ahmed Jerraya, Leti’s program manager for hardware/software integration. “Working with InfiniScale is an opportunity for us to enrich our design-tools offer by providing our partners with design kit libraries of yield- optimized circuit blocks.”

“Collaborating with Leti’s design and technology teams will be decisive in the development of our next-generation solution for the most aggressive sub-28nm technologies,” said Firas Mohamed, founder and CEO of InfiniScale. “With those technologies, process variability becomes critical at different levels, and it is especially important to focus on FD SOI, whose importance for major semiconductor companies is growing constantly.”