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Posts Tagged ‘LER’

Edge Placement Error Control in Multi-Patterning

Thursday, March 2nd, 2017


By Ed Korczynski, Sr. Technical Editor

SPIE Advanced Lithography remains the technical conference where the leading edge of minimum resolution patterning is explored, even though photolithography is now only part of the story. Leading OEMs continue to impress the industry with more productive ArFi steppers, but the photoresist suppliers and the purveyors of vacuum deposition and etch tools now provide most of the new value-add. Tri-layer-resist (TLR) stacks, specialty hard-masks and anti-reflective coatings (ARC), and complex thin-film depositions and etches all combine to create application-specific lithography solutions tuned to each critical mask.

Multi-patterning using complementary lithography—using argon-fluoride immersion (ArFi) steppers to pattern 1D line arrays plus extreme ultra-violet (EUV) tools to do line cuts—is under development at all leading edge fabs today. Figure 1 shows that edge placement error (EPE) in lines, cut layers, and vias/contacts between two orthogonal patterned layers can result in shorts and opens. Consequently, EPE control is critical for yield within any multi-patterning process flow, including litho-etch-litho-etch (LELE), self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

Fig.1: Plan view schematic of 10nm half-pitch vertical lines overlaid with lower horizontal lines, showing the potential for edge-placement error (EPE). (Source: Y. Borodovsky, SPIE)

Happening the day before the official start of SPIE-AL, Nikon’s LithoVision event featured a talk by Intel Fellow and director of lithography hardware solutions Mark Phillips on the big picture of how the industry may continue to pattern smaller IC device features. Regarding the timing of Intel’s planned use of EUV litho technology, Phillips re-iterated that, “It’s highly desirable for the 7nm node, but we’ll only use it when it’s ready. However, EUVL will remain expensive even at full productivity, so 193i and multi-patterning will continue to be used. In particular we’ll need continued improvement in the 193i tools to meet overlay.”

Yuichi Shibazaki— Nikon Fellow and the main architect of the current generation of Nikon steppers—explained that the current generation of 193i steppers, featuring throughputs of >200 wafers per hour, have already been optimized to the point of diminishing returns. “In order to improve a small amount of performance it requires a lot of expense. So just improving tool performance may not decrease chip costs.” Nikon’s latest productivity offering is a converted alignment station as a stand-alone tool, intended to measure every product wafer before lithography to allow for feed-forward tuning of any stepper; cost and cost-of-ownership may be disclosed after the first beta-site tool reaches a customer by the end of this year.

“The 193 immersion technology continues to make steady progress, but there are not as many new game-changing developments,” confided Michael Lercel, Director of Strategic Marketing for ASML in an exclusive interview with SemiMD. “A major theme of several SPIE papers is on EPE, which traditionally we looked at as dependent upon CD and overlay. Now we’re looking at EPE in patterning more holistically, with need to control the complexity with different error-variables. The more information we can get the more we can control.”

At LithoVision this year, John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—discussed the challenges of controlling variability in multi-layer patterning. “A key challenge is predicting and then mitigating total EPE control,” reminded Sturtevant. “We’ve always paid attention to it, but the budgets that are available today are smaller than ever. Edge-placement is very important ” At the leading edge, there are multiple steps within the basic litho flow that induce proximity/local-neighbor effects which must be accounted for in EDA:  mask making, photoresist exposure, post-exposure bake (PEB), pattern development, and CD-SEM inspection (wherein there is non-zero resist shrinkage).

Due to the inherent physics of EUV lithography, as well as the atomic-scale non-uniformities in the reflective mirrors focusing onto the wafer, EUV exposure tools show significant variation in exposure uniformities. “For any given slit position there can be significant differences between tools. In practice we have used a single model of OPC for all slit locations in all scanners in the fab, and that paradigm may have to change,” said Sturtevant. “It’s possible that because the variation across the scanner is as much as the variation across the slit, it could mean we’ll need scanner-specific cross-slit computational lithography.” More than 3nm variation has been seen across 4 EUVL steppers, and the possible need for tool-specific optical proximity correction (OPC) and source-mask optimization (SMO) would be horrible for managing masks in HVM.

Thin Films Extend Patterning Resolution

Applied Materials has led the industry in thin-film depositions and etches for decades, and the company’s production proven processing platforms are being used more and more to extend the resolution of lithography. For SADP and SAQP MP, there are tunable unit-processes established for sidewall-spacer depositions, and chemical downstream etching chambers for mandrel pull with extreme material selectivity. CVD of dielectric and metallic hard-masks when combined with highly anisotropic plasma etching allows for device-specific and mask-specific pattern transfers that can reduce the line width/edge roughness (LWR/LER) originally present in the photoresist. Figure 2 from the SPIE-AL presentation “Impact of Materials Engineering on Edge Placement Error” by Regina Freed, Ying Zhang, and Uday Mitra of Applied Materials, shows LER reduction from 3.4 to 1.3 nm is possible after etch. The company’s Sym3 chamber features very high gas conductance to prevent etch byproducts from dissociation and re-deposition on resist sidewalls.

Fig.2: 3D schematics (top) and plan view SEM images (bottom) showing that control of plasma parameters can tune the byproducts of etch processes to significantly reduce the line-width roughness (LWR) of minimally scaled lines. (Source: Applied Materials)

TEL’s new SAQP spacer-on-spacer process builds on the work shown last year, using oxide as first spacer and TiO2 as second spacer. Now TEL is exploring silicon as the mandrel, then silicon-nitride as the first spacer, and titanium-oxide as second spacer. This new flow can be tuned so that all-dry etch in a single plasma etch chamber can be used for the final mandrel pull and pattern transfer steps.

Coventor’s 3D modeling software allows companies to do process integration experiments in virtual space, allowing for estimation of yield-losses in pattern transfer due to variations in side-wall profiles and LER. A simulation of 9 SRAM cells with 54 transistors shows that photoresist sidewall taper angle determines both the size and the variability of the final fins. The final capacitance of low-k dielectric in dual-damascene copper metal interconnects can be simulated as a function of the initial photoresist profile in a SAQP flow.


Foundry, EDA partnership eases move to advanced process nodes

Monday, September 15th, 2014

By Dr. Lianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc., San Jose, Calif.

Partnerships are the lifeblood of the semiconductor industry, and when moving to new advanced nodes, industry trends show closer partnerships and deeper collaborations between foundries, EDA vendors and design companies to ease the transition.

It’s fitting, then, for me to pay homage in this blog post to a successful and long-term partnership between a foundry and an EDA tool supplier.

A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement. The goals were to improve SRAM yield and provide faster turnaround of a new process platform development.

The foundry used the EDA firm’s high-sigma DFY solution to optimize its SRAM yield for 28nm processes development. Early this year, it announced 28nm readiness for multi-project wafer (MPW) customers. One of the reasons it was able to release the 28nm process with acceptable SRAM yield in a short time was due to a new methodology for SRAM yield ramping that deployed a DFY engine.

During advanced technology development, the time spent on SRAM yield ramping is significant because statistical process variation, particularly local variation between two identical neighboring devices sometimes called mismatch, limits SRAM parametric yield. The impact of local process variation increases when moving to smaller CMOS technology nodes.

In the meantime, supply voltage is reduced, so operating regions are smaller. The difficulty achieving high yield for SRAM is greater because smaller nodes require higher SRAM density. Such challenges require very high sigma robustness or high SRAM bitcell yield. Statistically, the analysis for the SRAM bitcell at 28nm needs to be at around 6 σ, while FinFET technology at 16/14nm sets even higher sigma requirements for SRAM bitcell yield.

During technology development, foundry engineers improve the process to solve defect-related yield issues first. Design-for-manufacturing methodologies can be used to eliminate some systematic process variations. However, many random process variations, such as random dopant fluctuations (RDF), line edge and width roughness (LER, LWR), are fundamental limiting factors for parametric yield particular to SRAM.

Traditionally, foundry engineers rely on experience and know-how from previous node development efforts to analyze and decide how to run different process splits for different process improvement scenarios to optimize SRAM yield. These efforts are often time-consuming and less effective at advanced nodes like 28nm because the optimization margin is much smaller.

The fab’s new SRAM yielding flow used a high sigma statistical simulator as the core engine. It provided fast and accurate 3-7+σ yield prediction and optimization functions for memory, logic and analog circuit designs. During process development, the tool proved its technology advantages in both accuracy and performance, and was validated by silicon in several rounds of tape outs throughout the development process. It required no additional tuning on technology or special settings on the tool usage, so even process engineers who are not familiar with EDA tools could run them to get reliable results to guide their process tuning for SRAM yield improvement.

The flow was able to predict SRAM yield for different process and operating conditions. It simulated SRAM yield improvement trends and provided process improvement direction and guidelines within hours. A methodology such as this becomes necessary for advanced nodes where the remaining optimization margin is small. A simulation-based methodology can run through all possible combinations that process engineers want to explore, providing better yield results and faster yield ramping. Comparatively, the traditional way of exploration based on experiences and running large amount of process splits is limited and may not yield optimum results. It also is time consuming as the engineer would need to wait for tape out results then run another set of trials that could consume months.

The flow saved months ramping up SRAM yield for the 28nm process node. It reduced iteration time and saved wafer cost. Process engineers now only need to fabricate selective wafers to validate simulation results. They know which direction is optimal and have guidelines to run process splits that will help them identify the best conditions and converge on the best yield. They gained greater certainty as they saw more simulation-to-silicon correlation data as the project progressed.

A well-established methodology and flow brings value to process engineers because they can rely on DFY high sigma simulations to lay the foundation for their process improvement strategies to reach certain SRAM yield targets. They can run selective process splits to verify the results for lower wafer costs, fewer process tuning iterations and faster time to market.

Overall, this is a highly successful and mutually beneficial partnership, and the value of DFY to process technology development, is obvious. The same DFY methodology can be used for memory designers as SRAM yield is their primary target as well. The only difference is it tunes design variables using the same methodology, flow and tool solutions.

It’s easy to see the value of a tight collaboration between the foundry, EDA vendor and design companies and why it will be a trend on top of the “foundry-fabless” business model.

About Dr. Lianfeng Yang

Lianfeng Yang, ProPlus Solutions, Inc.

Dr. Lianfeng Yang currently serves as the Vice President of Marketing at ProPlus Design Solutions, Inc. Prior to co-founding ProPlus, he was a senior product engineer at Cadence Design Systems leading the product engineering and technical support effort for the modeling product line in Asia. Dr. Yang has over 40 publications and holds a Ph.D. degree in Electrical Engineering from the University of Glasgow in the U.K.

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