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Posts Tagged ‘ITRS’

ITRS 2.0: Top-Down System Integration

Wednesday, April 22nd, 2015

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By Andrew B. Kahng, Professor of CSE and ECE, University of California, San Diego, Juan-Antonio Carballo, Senior Manager, Embedded Solutions, AMD, and Paolo Gargini, Chairman, ITRS.

The mission of the System Integration (SI) focus team in ITRS2.0 is to establish a top-down, system-driven roadmapping framework for key market drivers of the semiconductor industry drivers in the 2015-2030 period. The SI focus team is currently developing and constructing roadmaps of relevant system metrics for Mobility, Internet of Things (IoT) and Big Data drivers. Mobility, embodied by the smartphone product, has redefined the existing ITRS SOC-CP (consumer portable system-on-chip) driver with richer feature requirements. IoT, as one of the fastest-growing market segments of electronic devices, imposes significantly different design considerations from conventional electronics design due to low-power and ubiquitous deployment requirements. As a fast-growing aspect of the datacenter, microservers have been separated out from the conventional server market segment. For these new drivers, the SI focus team seeks to identify and roadmap new system-level metrics (e.g., energy efficiency) as functionalities expand, architectures evolve, and heterogeneous integration soars.

Changes in the semiconductor industry supply chain

The 1980s and 1990s saw a semiconductor industry dominated by integrated device manufacturers (IDMs). During this period, the architecture of the main driver in the ITRS, the microprocessor unit (MPU), was not application-driven. Standard components in PC and server systems, e.g., memories and microprocessors, scaled their densities and operating frequencies continuously to meet aggressive performance and cost requirements. Applications had to be designed based on these components. However, in the past ten years, fabless design houses have changed the industry landscape. Design teams have been building customized system-on-chip (SoC) and system-in-package (SIP) products, rather than building standard components, to address specific application requirements. As applications evolve, they drive further requirements for heterogeneous integration, outside system connectivity, etc. A key goal of the SI focus team is to extract the technology requirements hidden behind the evolution of end products such as smartphones and microservers. The IoT is recognized as another driving market and application for the semiconductor industry; system metrics and semiconductor technology requirements pertaining to IoT are still in the preliminary stages of roadmapping.

Motivations and distinctions of system drivers

Historically, the ITRS has used metrics such as transistor density, number of cores, power, etc., to roadmap technology evolution of ICs. These metrics are essentially driven by the physical-dimension scaling as predicted by Moore’s Law. However, new requirements from applications such as mobility, datacenters, etc. require a new, system-level roadmapping approach, as these applications imply roadmaps for system-level metrics (e.g., the number of sensors, memory bandwidth, etc.). The ITRS roadmapping process as previously seen in the System Drivers Chapter has not explicitly incorporated these system-level product requirements. Therefore, a crucial goal of “ITRS 2.0” is to connect emerging system product drivers, along with corresponding metrics, into the ITRS’s semiconductor roadmapping methodology.

Initial driver roadmapping methodology used by system integration

The roadmap process in ITRS2.0 is summarized in Figure 1.  (i) Calibration data comes from sources such as published data from web searches, specification documents, datasheets and whitepapers from IC companies, teardown reports, and high-level comments from industry collaborators. (ii) Function categories are obtained by clustering analysis of IC components. Based on the categorization, we create abstract block diagrams as system models. We also analyze the components and project how metrics such as maximum operating frequency, die area, number of antennas, number of sensors, etc. evolve over the roadmap’s 15-year horizon. Finally, we produce a roadmap for system-level metrics based on the projected metrics and the abstract block diagrams.

Figure 1. Flow of data collection, analysis, and metric projection in the ITRS 2.0 roadmapping methodology.

Smartphone driver

In recent years, mobile devices, notably smartphones, have shown significant expansion of their computing capabilities. Since smartphone systems are built with multiple heterogeneous ICs (e.g., logic, memory, microelectromechanical systems (MEMS), and radio-frequency (RF)), we must understand tradeoffs at the system level. Beyond the current ITRS SOC-CP roadmap, ITRS 2.0 introduces a new smartphone driver to comprehend and roadmap metrics at a higher, system level for mobility applications. Figure 2, based on the Qualcomm Snapdragon family of SOCs [1], illustrates the growth of features and degree of integration in recent application processors (APs). Each new technology generation (aka “node”), which enables reduced computation power (e.g., new instruction set architecture (ISA), new devices, new low-power techniques) or the introduction of new features (e.g., graphic processing unit (GPU) or 1080p video), brings an increased number of vertically-stacked bars in the plot. Figure 2 shows that the degree of integration after 2008 keeps increasing to meet the demands of (i) higher computation performance, (ii) faster wireless connections, and (iii) richer multimedia capabilities. The increasing number of heterogeneous components (RF, logic, memory and MEMS) complicates the system design and blocks form factor reductions, while increasing the smartphone design cost and power budget.

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Figure 2. Increasing degree of integration in mobile application processors (Qualcomm SnapdragonTM family) [1

A system (board-level) power projection (5% growth in power per year) is shown in Figure 3(a). A 4.5W power management gap, relative to a system maximum power requirement of 4W, is projected to exist at the 15-year horizon. The power management gap for board-level power leads to a number of design challenges (heat and thermal/thermomechanical design, battery life, etc.). We expect that extremely aggressive low-power design techniques will need to be applied to IC components in smartphones to address power management challenges.  Figure 3(b) shows a projection for a second output metric, namely, board area. An area gap of up to 46cm2 (relative to a 60cm2 limit) is seen by the end of the roadmap, suggesting footprint reduction via vertical integration.

Figure 3. Implied requirements for smartphone board area and system power.

Fig. 4(a) shows the scaling of the number of pixels in smartphone displays. Display pixels of smartphones are driven by high-definition standards (e.g., 720p, 1080p, 4K, etc.). Increase in the display size increases the memory bandwidth requirement as shown in Figure 4(b). By 2029, ultra HD resolutions of 7680 × 4320 could potentially increase memory BW requirements to 148Gb/s. The rapid growth of bandwidth demands for system-level interconnects and off-device interconnects is considered to be a challenge for smartphone design.

Figure 4. Scaling of display size and memory bandwidth.

Key challenges and promising solutions

Several challenges exist in the development of the smartphone driver, based on the projection of system metrics.

The form factor challenge . As sizes of smartphones shrink, especially their thickness, adding new functionalities within compact form factors becomes very challenging. Two obvious challenges for technology development are:

  • The PCB footprint occupied by connectors and components should keep shrinking even though the memory bandwidth requirement and #components increase.
  • The degree of integration of heterogeneous components, such as logic, memories, non-volatile memories (NVMs), MEMs, RF/analog/mixed-signal (RF/AMS), should keep increasing to reduce the required footprint.

The system-level power management challenge. Since the projected board power of smartphones will be well beyond the 3-4W product limitation even by 2018, system-level power management is a clear challenge. The roadblocks to address this challenge are as follows.

  • The increasing memory bandwidth requirement relies on faster signaling and wider system buses, which will increase the board-level power consumption.
  • Increasing the number of sensors and other IC components implies more PCB traces. Shrinking smartphone form factors are expected to worsen this problem since routing traces will be more complicated, with added costs stemming from mitigation of interference as well as power implications of inter-chip communication.

The system-wide bandwidth challenge. System-wide bandwidth refers to the bandwidth between application processors and memories or application processors and other peripherals. As requirements for compute performance, #functionalities and display bandwidth keep growing (as indicated by the scaling of #APs, #GPUs, #sensors,  #pixels, and the communication bandwidth), delivering (energy-)proportionate system-wide bandwidth will become challenging. Another aspect of this challenge will be the tradeoffs between power management and bandwidth.

The communication bandwidth scaling challenge. A further challenge is implicit in the gaps between projections of required cellular data rate or WiFi data rate and achievable data rates. As the required communication standards supported by a single RF module proliferate, cost-feasible process and device technologies must enable smartphones to integrate more bands and communication standards within a fixed PCB footprint budget.

Microserver driver and metrics

In this section, we describe the main features, key metrics, key challenges, and potential solutions for the microserver driver.

Recent studies of datacenters (e.g., by Doller et al. [2]) suggest that high-performance MPU (MPU-HP) and networking SOC (SOC-NW) products are the main components in datacenters. These products may be implemented either in a single chip or in a multichip module (MCM). An optimized datacenter architecture cannot be achieved with a single chip as its key building block; rather a, co-optimization of storage, interconnects and software is required. Since the raw data stored in datacenters is usually sparse, pre-processing that is typically executed in traditional server cores is precluded, due to energy budget. Besides integration of power-efficient cores within an energy budget, datacenters require high bandwidth and accessibility for local memories (mostly non-volatile memories) to execute data-intensive operations. Due to datacenter-specific optimizations and system-level design requirements such as high rack density and cooling capacity, the metrics of servers in datacenters are different from those of server chips in existing products which are comprehended by ITRS.

Some new design challenges to microserver driver are introduced by their deployment in datacenters. Big data computing requires a drastic reduction in communication latencies to meet an under-100ms requirement, that is, data must be increasingly localized. The collected data suggest that the microserver driver addresses the cost issue by limiting the number of cores per rack unit and the latency issue by localizing user-specific search data. The volume of information in datacenters is anticipated to grow at a very high rate (every two years, or even faster). When users search for specific information, latencies can be on the order of tens of milliseconds because datacenters typically store information in a highly distributed manner. As datacenters grow in size, communication latencies increase along with power consumption (e.g., 75MW). To limit power and temperature of datacenters, companies are forced to invest huge amounts of money to establish and maintain power plants adjacent to datacenters, and to construct datacenters in geographies with “natural refrigeration”. There is a limit to such investment in power plants and cooling. Cooling costs, which can reach over 35% of electricity costs, continue to rise in server farms and datacenters; this creates a need to reduce the number of cores and operating frequencies to limit this cost.

To reduce operation cost, microservers must maximize the number of cores in a rack unit subject to power and thermal constraints. Form factor, energy efficiency, and networking throughput are important for this driver. As a consequence, demand for reduced form factor and system design effort drives the integration of the MPU and the chipset. Compared to a 1U server (MPU-HP in the 2013 ITRS), a microserver has a higher degree of integration as it includes on-chip Ethernet and peripheral hubs. Recent MPUs for microservers integrate application-specific accelerators to improve energy efficiency. Hence, high integration of functionalities is another potential challenge.

Key challenges and promising solutions

For the microserver driver, we identify the following challenges.

The service latency challenge. A growing challenge is posed by the crucial requirement for service latency.  Reference [3] proposes much more pessimistic metrics (from 50 percentile to 99 percentile latency) to ensure service quality could be guaranteed when Big Data are hosted. To address this application requirement, the solutions are expected to draw from a wide range of source technologies.

  • Since network performance is a key determinant of service latency, high-radix photonic switching networks are expected to be introduced to address the internode bandwidth requirement.
  • Conventional memory architectures will be unable to address access time requirements in hosting of Big Data; spindle-based hard drives will be replaced by non-volatile memories.
  • To improve the intra-node communication performance (e.g., MPU to memories or memories to NVMs), better heterogeneous integration solutions are expected.

The node density/cooling/power management challenge. To ease the cost of datacenter deployment, the following challenges are inherent in the enablement of sufficient computing resource with MPU cores and application-specific accelerators.

  • Moore’s Law should continue transistor scaling so that more functionalities can be integrated in the same die area, and to avoid power increases that result in too much demand for cooling.
  • Better memory integration (e.g., memory-over-logic) within each compute node is expected to ease the power management challenge by reducing the power impact.
  • Advanced power management techniques such as adaptive power management with on-die power sensors [6] are expected to be developed to address the power management issue.

The electro-optical integration challenge. Since the power and performance requirements of datacenter are both crucial, highly-integrated photonics inter-node networking is expected by 2020 [3]. Since the electro-optical interfaces are distributed all over the datacenter, it is necessary to develop on-chip photonic modulators and detectors to reduce the power, space, and performance overhead due to off-chip converters for electro-optical interfaces.

Conclusions

ITRS2.0 will, for the first time, via its system integration (SI) focus team, drive a top-down system-driven roadmap framework for key semiconductor industry drivers in the 2015-2030 period. The SI focus team is working to complete a roadmap of relevant metrics for Mobility (smartphone), Internet of Things (IoT), Big Data (microserver) drivers, and possibly other product segments that will be critical top-down drivers in the semiconductor industry of the next 15 years.

Acknowledgments

This overview draws from our recent paper [4]; we thank our coauthors Wei-ting Jonas Chan and Siddhartha Nath for their invaluable contributions.  We also thank members of the ITRS community, and other focus team leaders, for their feedback during the course of this work.

References

[1]. http://en.wikipedia.org/wiki/Qualcomm_Snapdragon

[2]. E. Doller et al., “DataCenter 2020: Near-memory Acceleration for Data-oriented Applications”, Proc. Symposium on VLSI Circuits, 2014

[3]. https://www.usenix.org/sites/default/files/conference/protected-files/fast14_asanovic.pdf

[4]. J.-A. Carballo, W.-T. J. Chan, P. A. Gargini, A. B. Kahng and S. Nath, “ITRS 2.0: Toward a Re-Framing of the Semiconductor Technology Roadmap”, Proc. Intl. Conf. on Computer Design, 2014.

Blog review March 9, 2015

Monday, March 9th, 2015

Pete Singer is delighted to announce the keynotes and other speakers for The ConFab 2015, to be held May 19-22 at The Encore at The Wynn in Las Vegas. The line-up includes Ali Sebt, President and CEO of Renesas America, Paolo Gargini, Chairman of the ITRS and Subramani Kengeri, Vice President, Global Design Solutions at GLOBALFOUNDRIES.

Mark Simmons, Product Marketing Manager, Calibre Manufacturing Group, Mentor Graphics writes about cutting fab costs and turn-around time with smart, automated resource management. He notes that the competition for market share is brutal for both the pure-play and independent device manufacturer (IDM) foundries. Success involves tuning a lot of knobs and dials. One of the important knobs is the ability to continually meet or exceed aggressive time-to-market schedules.

Paul Stockman, Commercialization Manager, Linde Electronics blogs that there is an increasing demand for and focus on sustainable manufacturing that will contribute to a greening of semiconductors. This greening must be robust and responsive to change and cannot constrain the individual processes or operation of a fab.

Applied Materials’ Max McDaniel writes on the quest for more durable displays. He says the same innovators who created such amazingly thin, light and highly functional smartphones (with the help of Applied Materials display technology) are already developing durability improvements that may eliminate the need for protective covers.

Batteries? We don’t need no stinking batteries, says Ed Korczynski. We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources.

With the 2015 SPIE Advanced Lithography (AL) conference around the corner, some people have asked me what remaining EUVL challenges need to be addressed to ensure it will be ready for mass production later this year or next.  Vivek Bakshi of EUV Litho, Inc. provides thoughts on this topic and what he expects to hear at the conference.

Phil Garrou continues his look at presentations from the Grenoble SEMI 3D Summit which took place in January, focusing on an interesting presentation by ATREG consultants on the future of Assembly & Test.

On Tuesday, January 20, President Obama once again stood before a joint session of Congress to deliver a State of the Union Address.  With the newly seated Republican-controlled Congress and his Cabinet present, the President discussed topics ranging from the current state of the economy to foreign affairs and his ideas on how to move the nation forward.  Jamie Girard of SEMI was pleased to hear that the President supported multiple policy goals including expansion of free trade, corporate tax reform, support for basic science research and development and others.

Scouting report for materials at end of the road: 2013 ITRS

Monday, May 12th, 2014

Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The IC fabrication industry is approaching the end of the road for device miniaturization, with both atomic and economic limits looming on the horizon. New materials are widely considered as key to the future of profitable innovation in ICs, so everyone from process engineers to business pundits needs to examine the Emerging Research Materials (ERM) chapter of the just published 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).

The 2013 ITRS covers both near-term (2014-2020) and long-term (2020 onward) perspectives on what materials and processes would be desired to build ideal ICs (Fig. 1, Table ERM15). However, to properly understand the information in the current edition we need to consider the changes in the IC fab industry since 1992 when the first edition of the ITRS’s predecessor was published as the U.S. National Technology Roadmap for Semiconductors (NTRS).

Fig. 1

Twenty-two years ago, the industry had dozens of fabs working on next-generation technology, and with lithographic scaling dominating innovation there was broad consensus on gradual materials evolutions. Today, the industry has 3 logic fabs and about as many memory lines pushing processes to smaller geometries, and each fab may use significantly different revolutionary materials. The result today is that there is little consensus on direction for new materials, and at best we can quantify the relative benefits of choosing one or another of the many options available.

In fact, with just a few players left in the game, there is much to lose for any one player to disclose strategic plans such as the use of revolutionary materials. Mark Thirsk, managing partner with specialty materials analysts Linx Consulting, commented, “We built our business based on anonymizing and generalizing the world, and then predicting the future based on big categorical buckets. But now there are a very few number of people pushing the boundaries and we’re being asked to model specific fab processes such as those for Intel or TSMC.”

For all of the above reasons, the current ITRS might be better understood as a scouting report that quantifies the roughness of the terrain when our current roads end. Exotic materials such as graphene and indium-gallium-phosphide may be used as alternate materials for the Si channels in transistors, novel stacks of atomic-layers may be used as electrical contacts, and spintronics and single-electron devices may one day replace DRAM and Flash chips for solid-state memory chips. However,  “significant challenges” exist in integrating any of these new technologies into high-volume manufacturing.

In the near-term, Cu wires clad with various metal barriers are projected to provide the best overall performance for on-chip interconnects.  As stated in the 2013 Executive Summary, “Unfortunately no new breakthroughs are reported for interconnections since no viable materials with resistivity below copper exist. However, progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations etc.) offer the promise of ‘ballistic conductors,’ which may emerge in the next decade.”

Specialty Materials Suppliers

Fig. 2

Figure 2 (Figure ERM5) shows the inherent complexity involved in the stages of developing a new chemical precursor for use in commercial IC production. The chapter summarizes the intrinsic difficulty of atomic-scale R&D for future chips as follows:

A critical ERM factor for improving emerging devices, interconnects, and package technologies is the ability to characterize and control embedded interface properties. As features approach the nanometer scale, fundamental thermodynamic stability considerations and fluctuations may limit the ability to fabricate materials with tight dimensional distributions and controlled useful material properties.

In addition to daunting technical issues with pre-cursor R&D, the business model for chemical suppliers is being strained by industry consolidation and by dimensional shrinks. Consolidation means that each fab has unique pre-cursor requirements, so there may be just one customer for a requested chemistry and no ability to get a return on the investment if the customer decides to use a different approach.

Shrinks down to atomic dimensions means that just milliliters instead of liters of chemistry may be needed. For example, atomic-layer deposition (ALD) precursor R&D requires expertise and investment in molecular- and chemical-engineering, and so significant sunk costs to create any specialty molecule in research quantities. “We’ll have an explosion of precursors required based on proprietary IP held by different companies,” reminds Thirsk. “The people who are being asked to develop the supply-chain of ever increasing specifications are simultaneously being squeezed on margin and volumes.”

For materials such as Co, Ru, La, and Ti-alloys to be used in fabs we need to develop more than just deposition and metrology steps. We will also likely require atomic-level processes for cleaning and etch/CMP, which can trigger a need for yet another custom material solution.

Established chemical suppliers—such as Air Liquide, Dow, DuPont, Linde, Praxair, and SAFC—run international businesses serving many industries. IC manufacturing is just a small portion of their businesses, and they can afford to simply walk-away from the industry if the ROI seems unattractive. “We’re finding more and more that, for example in wet cleaning chemistry, the top line of the market is flat,” cautioned Thirsk. “You can find some specialty chemistries that provide better profits, but the dynamics of the market are such that there’s reduced volume and reduced profitability. So where will the innovation come from?”

Alternate Channel Materials

With finFETs and SOI now both capable of running in fully-depleted mode, alternative materials to strained silicon are being extensively explored to provide higher MOSFET performance at reduced power. Examples include III-V semiconductors, Ge, graphene, carbon nanotubes, and other semiconductor nanowires (NW). To achieve complimentary MOS high performance, co-integration of different materials (i.e. III-V and Ge) on Si may be necessary. Significant materials issues such as defect reduction, interface chemistry, metal contact resistivity, and process integration must be addressed before such improvements can be achieved.

Nano-wire transistors

Top down fabricated nanowires (NW) are one-dimensional structures that can be derived from two-dimensional finFETs. Patterned and etched <5nm Si NW have been reported to have room temperature quantum oscillatory behavior with back-gate voltage with a peak mobility approaching ∼900 cm2/Vs. Despite extensive R&D, grown Si NW demonstrate no performance improvements over patterned-and-etched NW, and controlled growth in desired locations remains extraordinarily challenging. Overall, significant challenges must be overcome for NW to be integrated in high density, particularly when targeting laterally placed NW with surround gates and low resistance contacts.

—E.K.

Blog review May 5, 2014

Monday, May 5th, 2014

Jeremy Read of Applied Materials writes that while some consumer IoT applications will require semiconductors manufactured using cutting-edge technologies the vast majority of chips will be used in client-side applications. These chips, such as a sensor monitoring room temperature in a connected HVAC system, require processing capabilities that can be met using legacy process (90 and 45nm) technologies manufactured on 200mm wafers.

Ali Khakifirooz of Spansion notes that body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.

Frank Feng of Mentor Graphics blogs that transistor and gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic discharge (ESD), latch-up, electrical overstress (EOS), and dielectric breakdown. However, when designers assemble transistors and gates into intellectual property (IP), blocks, or whole chip designs, they encounter a variety of reliability problems generated across interconnect layers or across device regions of PSUB and NWELL bodies.

Phil Garrou has not been predicting the end of the world, but rather the end of electronics as we know it, i.e.,relying on CMOS scaling. He blogs that it was with great anticipation that he perused the 2013 ITRS roadmap that was released a few weeks ago. He is happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

Pete Singer writes that the newly revamped International Technology Roadmap for Semiconductors was released in early April. It’s actually called the 2013 ITRS, which makes it seem already out of date, but that’s the way the numbering has always been. The latest ITRS highlights 3D power scaling, system level integration and a new chapter on big data.


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