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InvenSense Developers Conference Tackles Sensor Security, New Technologies

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.

There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.

The conference also featured two developer tracks in parallel, providing five InvenSense presentations on its FireFly hardware and software, SensorStudio, and other offerings.

One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.

TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.

The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.

Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.

Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”

It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.

While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.

PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”

Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.

Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”

Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.

“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.

“That’s data that can be monetized,” he said.

InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”

The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.

“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.

InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.

Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.

GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.

The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.

STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.

IoT Security, Software Are Highlighted at ARM TechCon

Friday, November 13th, 2015


By Jeff Dorsch, Contributing Editor

Many people are aware of the Internet of Things concept. What they want to know now is how to secure the IoT and how to develop code for it.

Plenty of vendors on hand for the ARM TechCon conference and exposition in Santa Clara, Calif. this week were offering solutions on both counts. And there were multiple presentations in the three-day conference program devoted to both subjects.

Mentor Graphics, for instance, spoke about “Use Cases for ARM TrustZone Benefits of HW-Enforced Partitioning and OS Separation.” MediaTek presented on “Secured Communication Between Devices and Clouds with LinkIt ONE and mbedTLS.” And so on.

ARM CEO Simon Segars said in his keynote address that security and trust are one of the key principles in the Internet of Things (the others being connectivity and partnership across the ecosystem). Security and trust, he asserted, must be “at every level baked into the hardware, before you start layering software on top.”

James Bruce, ARM’s director of mobile solutions, addressed the security topic at length in an interview at the conference. ARM is taking a holistic approach to security through its TrustZone technology, he said, describing it as “a great place to put [network] keys.”

With microcontrollers, the chips often used in IoT devices, TrustZone makes sure sensitive data is “inaccessible to normal software,” Bruce said. At the same time, “you want to make devices easy to update,” he added.

ARM wants to enable its worldwide ecosystem of partners to stay ahead of cyberattacks and other online dangers, according to Bruce. “That’s why we’re doing the groundwork now,” he said.

The reaction of ARM partners to the introduction of TrustZone CryptoCells and the new ARMv8-M architecture for embedded devices has been “very positive,” Bruce said, adding, “Security can’t be an afterthought.”

Ron Ih, senior manager of marketing and business development in the Security Products Group at Atmel, described standard encryption as “only a piece” of security measures. “Authentication is a key part,” he said.

Atmel was touting its Certified-ID platform at ARM TechCon, featuring the ATECC508A cryptographic co-processor. Ih cited the “made for iPhone” chips that Apple requires of its partners developing products to complement the smartphone, ensuring ecosystem control. “You either have the chip or you don’t,” he said.

“People don’t care about the devices,” Ih concluded. “They care about who the devices are connected to.”

Simon Davidmann, president and chief executive officer of Imperas Software, is a veteran of the electronic design automation field, and he brings his experience to bear in the area of embedded software development.

Software, especially for the IoT, is “getting so complex, you can’t do what you used to do,” he said. “The software world has to change. Nobody should build software without simulation.”

At the same time, simulation is “necessary but not sufficient” in software development, he said. Code developers should be paying attention to abstractions, assertions, verification, and other aspects, according to Davidmann.

“Our customers are starting to adopt virtual platforms,” he added.

Jean Labrosse, president and CEO of MIcrium, a leading provider of real-time operating system kernels and other software components, said “the industry is changing” with the onset of the Internet of Things. Multiple-core chips are entering into the mix – not only for their low-power attributes, but for the safety and security they can provide, he noted.

Jeffrey Fortin, director of product management at Wind River and a specialist in IoT platforms, spoke on the last day of the conference on “Designing for the Internet of Things: The Technology Behind the Hype.”

Wind River, now an Intel subsidiary, has been around for more than three decades, developing “an embedded operating system that could be connected to other systems,” he said.

There are two business interests driving IoT demand, according to Fortin – business optimization and business transformation. He described the IoT as “using data to feed actionable analytics.”

The foundation of the IoT is hardware and software that provides safety and security, Fortin said.

Colt McAnlis of Google (Photo by Jeff Dorsch)

In the final keynote of ARM TechCon, Google developer advocate Colt McAnlis spoke on “The Hard Things About the Internet of Things.”

IoT technology, at present, is “not optimizing the user,” he said in a frequently funny and witty presentation. Networking and battery issues are bedeviling the IoT ecosystem, he asserted.

By draining the batteries of mobile devices with near-constant signals, such as setting location via GPS, companies are imposing “a taxation system for every single thing [IoT] does,” McAnlis said. “We’re talking about how often we’re sampling. People are already realizing this sucks.”

Beacons installed in a shopping mall can bombard smartphone users with advertising and coupons, he noted, while the property management gets data on specifics of foot traffic. “Imagine this at scale,” installed on every block of San Francisco, he added.

“We have a chance to not make this a reality,” McAnlis asserted. “We need IoT technology to make this not suck for users.”

At the end of his keynote, McAnlis asked the attendees to hold up their smartphones and vow, “I solemnly agree not to screw this up.”

ARM CEO Celebrates 500 Years of Connectivity

Wednesday, November 11th, 2015

By Jeff Dorsch, Contributing Editor

“Realize that everything connects to everything else,” Leonardo da Vinci said some five centuries ago.

Simon Segars, chief executive officer of ARM Holdings, took that quotation as the theme for his ARM TechCon keynote address on Wednesday morning (November 11), which was entitled “Building Trust in a Connected World.”

ARM CEO Simon Segars

“The future is dependent on the connections we make,” Segars commented.

He reviewed the history of significant products in the 20th century – automobiles, vacuum cleaners, DVD players, et al. – and noted how their pricing was reduced through “optimizing supply chains,” he said.

In 2015, “smartphones are essentially free,” Segars said. Pulling together all the capabilities and components that go into smartphones today would cost $3.56 million in 1990, the year ARM was established, he estimated. He displayed a RadioShack advertisement from 25 years ago with a page full of consumer electronics – all of which are now contained in smartphones.

In the 21st century, “the world has moved on,” Segars observed. Modern industry involves “planetary ecosystems,” he said, enabling worldwide contributions to developing the Internet of Things.

“Let’s take the opportunity to get IoT right,” Segars said, noting its development will depend on connectivity, based on common standards; security and trust; and partnerships across the ecosystem.

Automotive vehicles, medical electronics, and “smart cities” are key areas where the IoT will find growth prospects, the ARM CEO said.

“Cars are getting smarter,” Segars said, noting that the average vehicle contains hundreds of microcontrollers. It is estimated that 40 percent of the cars in the U.S. will have Long-Term Evolution (LTE) connectivity by 2019, he added.

As he went deeper into the topic of Internet-connected cars, a fire alarm went off in the crowded Mission City Ballroom of the Santa Clara Convention Center. Segars, the son of a fireman, directed the attendees to leave the building, interrupting the keynote address.

When the alarm proved to be false, the keynote resumed, with Segars bringing on three industry executives for a panel session. They were Paul Beckwith of the Progressive Group of Insurance Companies, Coby Sella of ARM, and Balaji Yelamanchili of Symantec.

“We talk about trust,” Sella said. “You have to analyze the risk factors.”

Yelamanchili said, “A lot of times, security is an afterthought.” For the IoT, security measures must be built into the chips and systems involved, he asserted.

To prevent data leakage, “these devices and how you connect these devices are purpose-built,” he added.

Beckwith said “our brand is at risk” if everything in the IoT is not secure.

Sella noted, “We are very much at the beginning” of IoT technology.

Segars asked the panelists what IoT will look like in five years.

“We have to do our best to make sure the security is built in,” Yelamanchili said. “There are enormous opportunities out there.”

Sella said, “We will start to see horizontal play in IoT. It depends on our ability to drive this forward.”

Beckwith commented that the industry will have to “react quicker” to security challenges and data-breach episodes.

ARM CTO looks forward and backward in keynote

Tuesday, November 10th, 2015

UPDATE 15 December 2015: Minor changes made to reflect correct ARM product nomenclature.

By Jeff Dorsch, Contributing Editor

“Innovation is still thriving in semiconductors,” said Mark Muller, chief technology officer of ARM Holdings, in a keynote address Tuesday morning (November 10) at the ARM TechCon conference and exposition in Santa Clara, Calif.

“We’ve always had constraints on what we can do,” he added. Still, “there’s an incredible amount of innovation ahead of us.”

ARM CTO Mike Muller describes the company's strategy, upside in server opportunities, and technology's march towards the IoT.

With ARM marking its 25th anniversary this month, Muller briefly reviewed the history of the company and the technology that preceded its establishment, harking back to the BBC Micro Model A/B computer of 1981 and the 1985 introduction of the ARM1 processor. The BBC Micro has ultimately led to this year’s introduction of the BBC micro:bit single-board computer, which is being provided for free to 10-year-old and 11-year-old schoolchildren in the United Kingdom.

Muller talked about ARM’s progress in getting its designs into server chips, with “multiple manufacturers” shipping ARM-based servers, he noted. Such servers are being implemented at the Barcelona Supercomputing Center in Spain and at Sandia National Laboratories, Muller said.

Moving on, Muller said, “Mobile computing has been transformed.” While the annual growth rate of mobile devices is expected to decline to 10 percent by 2020, such “not bad” growth will primarily be coming from entry-level smartphones by the end of the decade, he added.

The CTO touted “a truly remarkable product,” the ARM Cortex-A35 processor, being introduced at this week’s conference. Chips with that processor design will be able to run on less than 6 milliwatts, he said.

At the same time, Muller said of ARM’s product strategy, “It’s so much more than processors.” The company aspires to provide “all of the IP [intellectual property] you need,” he said to the designers in attendance.

Muller enthused about what he called “the product of the year,” an energy-harvesting Bluetooth Low Energy insulin pen designed by Cambridge Consultants, incorporating a Dialog Semiconductor chip. The KiCoPen concept has no battery, he noted. Using piezoelectric technology, it derives its energy from the injector cap being removed from the pen.

The ARM executive also addressed the security issue with the Internet of Things and related products. “We’re under attack in a way we never were before,” Muller said.

“How do we make a $1 microcontroller design done by people with no security experience, secure?” he asked.

ARM also introduced the TrustZone CryptoCell security technology this week, along with its ARMv8-M architecture for embedded devices.

“The hardware is the easy part,” Muller commented. With the IoT, there are familiar problems in chip and system design, “times trust,” he said.

“You have to be able to secure them,” Muller said of IoT devices. “You share that trust around you.”

Meeting the IoT Design Challenge

Monday, November 2nd, 2015


By Pete Singer, Editor-in-Chief

Mentor Graphics acquired Tanner EDA in March of 2015, in an effort to better address the design, layout and verification of analog/mixed-signal (AMS) and MEMS ICs, key building blocks in Internet of Things (IoT).

Since then, the Tanner team has moved offices and successfully been integrated into Mentor’s corporate structure.

We recently caught up with Jeff Miller, product marketing manager for the Tanner Group at Mentor Graphics. “We’ve kept the team together and we’re continuing to work as a business unit within Mentor Graphics with the same team under the same leadership,” he said. “Greg Lebsack, who was the president of Tanner EDA is now the general manager of the Tanner Group. We have the same basic org chart.” He noted that the same people who were with Tanner for a long time are still there. “We tried to preserve that and we’ve done a good job of that,” Miller said.

With the explosion of IoT devices – some estimate 70 billion devices will be connected to the internet by 2020 – the Tanner acquisition seems particularly prescient in that many if not most IoT devices are analog/mixed signal devices, and many involve the use of MEMS.

“We’ve been involved in various IoT-type designs for a long time,” Miller explained. He defined an IoT device as a sensor and an actuator — that’s the “thing” part – plus some amount of readout or control circuitry, and some digital logic in order to control that and interface to a radio which then communicates to your cell phone or you WiFi network and then on to the internet. “You need to have all those four pieces to make your IoT device,” he said.

The microcontroller or microprocessor component and the radio component have been traditionally been done outside of the Tanner EDA tools, but Miller said they group has been making a big effort in the last couple of years to bring some of that into their design flow in terms of enabling a greater degree of integration. “The cost, size pressures and power pressures are going to force some integration there,” Miller said.

In other words, sensors are being integrated with more and more of intelligence. “Instead of just having a raw MEMS accelerometer, they’ll have a 3-axis accelerometer with a 3-axis gyro and a read-out circuit and enough digital logic to do some processing,” said Miller. “These sensors are becoming a lot smarter and more integrated in order to support these kinds of applications.”

Miller said he’s seen a lot of new entrants into the IoT market. Typically design teams have5 to 20 people. Tanner’s market historically has been the smaller companies with relatively focused products.

“I’m expecting the needs of this market to be diverse enough that we’re going to see a proliferation of small interesting designs that enable a particular class of IoT device,” Miller predicts. “This proliferation across the market will lead to small design teams doing something innovative in a smaller scale environment, trying to make these things as small and efficient as they can possibly be. “

Since the acquisition, a big focus of the Tanner Group has been on how to best integrate Mentor’s tools such as Calibre, ModelSim and AFS with existing Tanner products. “More so than ever before, we have a complete design flow, start to finish, for analog design flow, mixed signal design and for MEMS design, and any integration across those things,” Miller said. “We’re keeping our basic ways of doing things and leveraging the incredible resources that are available being part of a large company like Mentor Graphics. It’s really good for us to part of this new, larger team.”

The first major integration was with Calibre, followed by ModelSim as the digital simulator in their mixed signal flow. “We can integrate our SPICE simulator with ModelSim and do mixed signal simulations and communicate the signals across the boundary between analog and digital,” Miller said. He adds that expects to have more and tighter integrations with other Mentor Graphic tools moving forward.

“I’ve been really encouraged that Mentor has been investing us and making sure we’re going to be around and still doing business in a Tanner kind of way going into the future,” Miller said.

TSMC Forum Emphasizes Industry Collaboration

Thursday, September 17th, 2015


By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing kicked off its Open Innovation Platform (OIP) Ecosystem Forum with thanks – not for another beautiful day in Silicon Valley, but for the collaborative work it does with its customers, suppliers, and other industry partners.

Rick Cassidy, the foundry’s senior vice president and president of TSMC North America, kicked off the all-day event in Santa Clara, Calif., saying he wanted to debunk the myth of the “lone creative genius” in the chip business. “It is a lot of geniuses working together,” he said. “Innovation happens collectively.”

While there has been much attention paid to the slowing growth in the smartphone market, mobile technology will continue to be a significant driver for the semiconductor industry, according to Cassidy. He reviewed the areas of mobile technology, the Internet of Things, and automotive electronics.

“IoT will require an incredible amount of interconnection technology,” Cassidy said.

Between IoT and automotive tech, there will be “a very significant amount of data that’s going to be needed to be stored and processed,” he added.

Cassidy emphasized TSMC’s relations with its many collaborators, large and small. “We’re a pure-play foundry,” he said. “We do not have any products.”

He added, “Nobody does yield better than TSMC.”

Cassidy noted that TSMC will spend more than $2.2 billion this year on research and development, compared with more than $1.9 billion last year. The foundry’s capital expenditure budget for 2015 is $10.5 billion to $11 billion, up from $9.5 billion in 2014, he added.

The opening session also heard from Jack Sun, TSMC’s vice president of R&D and chief technology officer, and Cliff Hou, vice president of the R&D design technology platform, as well as executives of Avago Technologies and Xilinx, two TSMC customers.

International Consortium Sets Up Shop for Advanced Manufacturing Research

Thursday, July 16th, 2015

By Jeff Dorsch, Contributing Editor

Here we go again.

A metropolitan area in the center of the state is putting together a public-private partnership to attract high-tech companies, convincing them to set up shop and create jobs. Part of the attraction is a big public university, engaging in advanced research.

Austin, Texas? No, now it’s Orlando, Florida.

Yes, the home of Walt Disney World, Universal Orlando, and other magnets for visiting families.

About one-third of the jobs in Orlando are in hospitality and tourism, according to Dave Porter, senior vice president of business development for the Orlando Economic Development Commission. The other two-thirds are in a variety of other industries, including energy, military contracting, and telecommunications.

Porter is a veteran of attracting industry to a metropolitan area;  he previously spent a decade working for the Austin Chamber of Commerce, which actively worked with the city and state governments to bring many high-tech employers to the capital of Texas, before joining the Orlando EDC this year.

One of Orlando’s big gets is the International Consortium for Advanced Manufacturing Research (ICAMR), which has a hand in constructing a facility in Osceola County known as the Florida Advanced Manufacturing Research Center, or FAMRC, in cooperation with the University of Central Florida. Osceola County has chipped in nearly $138 million for building the FAMRC, which is scheduled to open in 2016 and will house ICAMR and other parties, especially those interested in the development and manufacturing of smart sensors.

UCF kicked in $17 million of funding, while other Florida universities contributed toward building the center, and the State of Florida may invest in the facility, as well.

ICAMR is modeled after Sematech, the semiconductor manufacturing technology consortium once based in Austin, which helped attract many chip-related businesses to Central Texas over 25 years, according to Porter.

“Orlando is well known, but poorly understood,” he says. “It’s the youngest city in Florida.” The metro area has a labor pool of more than 1.2 million people, with 500,000-plus students within a 100-mile radius.

Sensors are at the heart of the grand scheme known as the Internet of Things. Whether IoT takes off or not, there will be greater demand for more sophisticated sensing technology in the years to come, and ICAMR wants to help lead that field. Porter says business leaders and politicians are always talking about “bringing manufacturing back to the U.S.,” and ICAMR/FAMRC could help that.

Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015


By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.


ITRS 2.0: Top-Down System Integration

Wednesday, April 22nd, 2015


By Andrew B. Kahng, Professor of CSE and ECE, University of California, San Diego, Juan-Antonio Carballo, Senior Manager, Embedded Solutions, AMD, and Paolo Gargini, Chairman, ITRS.

The mission of the System Integration (SI) focus team in ITRS2.0 is to establish a top-down, system-driven roadmapping framework for key market drivers of the semiconductor industry drivers in the 2015-2030 period. The SI focus team is currently developing and constructing roadmaps of relevant system metrics for Mobility, Internet of Things (IoT) and Big Data drivers. Mobility, embodied by the smartphone product, has redefined the existing ITRS SOC-CP (consumer portable system-on-chip) driver with richer feature requirements. IoT, as one of the fastest-growing market segments of electronic devices, imposes significantly different design considerations from conventional electronics design due to low-power and ubiquitous deployment requirements. As a fast-growing aspect of the datacenter, microservers have been separated out from the conventional server market segment. For these new drivers, the SI focus team seeks to identify and roadmap new system-level metrics (e.g., energy efficiency) as functionalities expand, architectures evolve, and heterogeneous integration soars.

Changes in the semiconductor industry supply chain

The 1980s and 1990s saw a semiconductor industry dominated by integrated device manufacturers (IDMs). During this period, the architecture of the main driver in the ITRS, the microprocessor unit (MPU), was not application-driven. Standard components in PC and server systems, e.g., memories and microprocessors, scaled their densities and operating frequencies continuously to meet aggressive performance and cost requirements. Applications had to be designed based on these components. However, in the past ten years, fabless design houses have changed the industry landscape. Design teams have been building customized system-on-chip (SoC) and system-in-package (SIP) products, rather than building standard components, to address specific application requirements. As applications evolve, they drive further requirements for heterogeneous integration, outside system connectivity, etc. A key goal of the SI focus team is to extract the technology requirements hidden behind the evolution of end products such as smartphones and microservers. The IoT is recognized as another driving market and application for the semiconductor industry; system metrics and semiconductor technology requirements pertaining to IoT are still in the preliminary stages of roadmapping.

Motivations and distinctions of system drivers

Historically, the ITRS has used metrics such as transistor density, number of cores, power, etc., to roadmap technology evolution of ICs. These metrics are essentially driven by the physical-dimension scaling as predicted by Moore’s Law. However, new requirements from applications such as mobility, datacenters, etc. require a new, system-level roadmapping approach, as these applications imply roadmaps for system-level metrics (e.g., the number of sensors, memory bandwidth, etc.). The ITRS roadmapping process as previously seen in the System Drivers Chapter has not explicitly incorporated these system-level product requirements. Therefore, a crucial goal of “ITRS 2.0” is to connect emerging system product drivers, along with corresponding metrics, into the ITRS’s semiconductor roadmapping methodology.

Initial driver roadmapping methodology used by system integration

The roadmap process in ITRS2.0 is summarized in Figure 1.  (i) Calibration data comes from sources such as published data from web searches, specification documents, datasheets and whitepapers from IC companies, teardown reports, and high-level comments from industry collaborators. (ii) Function categories are obtained by clustering analysis of IC components. Based on the categorization, we create abstract block diagrams as system models. We also analyze the components and project how metrics such as maximum operating frequency, die area, number of antennas, number of sensors, etc. evolve over the roadmap’s 15-year horizon. Finally, we produce a roadmap for system-level metrics based on the projected metrics and the abstract block diagrams.

Figure 1. Flow of data collection, analysis, and metric projection in the ITRS 2.0 roadmapping methodology.

Smartphone driver

In recent years, mobile devices, notably smartphones, have shown significant expansion of their computing capabilities. Since smartphone systems are built with multiple heterogeneous ICs (e.g., logic, memory, microelectromechanical systems (MEMS), and radio-frequency (RF)), we must understand tradeoffs at the system level. Beyond the current ITRS SOC-CP roadmap, ITRS 2.0 introduces a new smartphone driver to comprehend and roadmap metrics at a higher, system level for mobility applications. Figure 2, based on the Qualcomm Snapdragon family of SOCs [1], illustrates the growth of features and degree of integration in recent application processors (APs). Each new technology generation (aka “node”), which enables reduced computation power (e.g., new instruction set architecture (ISA), new devices, new low-power techniques) or the introduction of new features (e.g., graphic processing unit (GPU) or 1080p video), brings an increased number of vertically-stacked bars in the plot. Figure 2 shows that the degree of integration after 2008 keeps increasing to meet the demands of (i) higher computation performance, (ii) faster wireless connections, and (iii) richer multimedia capabilities. The increasing number of heterogeneous components (RF, logic, memory and MEMS) complicates the system design and blocks form factor reductions, while increasing the smartphone design cost and power budget.


Figure 2. Increasing degree of integration in mobile application processors (Qualcomm SnapdragonTM family) [1

A system (board-level) power projection (5% growth in power per year) is shown in Figure 3(a). A 4.5W power management gap, relative to a system maximum power requirement of 4W, is projected to exist at the 15-year horizon. The power management gap for board-level power leads to a number of design challenges (heat and thermal/thermomechanical design, battery life, etc.). We expect that extremely aggressive low-power design techniques will need to be applied to IC components in smartphones to address power management challenges.  Figure 3(b) shows a projection for a second output metric, namely, board area. An area gap of up to 46cm2 (relative to a 60cm2 limit) is seen by the end of the roadmap, suggesting footprint reduction via vertical integration.

Figure 3. Implied requirements for smartphone board area and system power.

Fig. 4(a) shows the scaling of the number of pixels in smartphone displays. Display pixels of smartphones are driven by high-definition standards (e.g., 720p, 1080p, 4K, etc.). Increase in the display size increases the memory bandwidth requirement as shown in Figure 4(b). By 2029, ultra HD resolutions of 7680 × 4320 could potentially increase memory BW requirements to 148Gb/s. The rapid growth of bandwidth demands for system-level interconnects and off-device interconnects is considered to be a challenge for smartphone design.

Figure 4. Scaling of display size and memory bandwidth.

Key challenges and promising solutions

Several challenges exist in the development of the smartphone driver, based on the projection of system metrics.

The form factor challenge . As sizes of smartphones shrink, especially their thickness, adding new functionalities within compact form factors becomes very challenging. Two obvious challenges for technology development are:

  • The PCB footprint occupied by connectors and components should keep shrinking even though the memory bandwidth requirement and #components increase.
  • The degree of integration of heterogeneous components, such as logic, memories, non-volatile memories (NVMs), MEMs, RF/analog/mixed-signal (RF/AMS), should keep increasing to reduce the required footprint.

The system-level power management challenge. Since the projected board power of smartphones will be well beyond the 3-4W product limitation even by 2018, system-level power management is a clear challenge. The roadblocks to address this challenge are as follows.

  • The increasing memory bandwidth requirement relies on faster signaling and wider system buses, which will increase the board-level power consumption.
  • Increasing the number of sensors and other IC components implies more PCB traces. Shrinking smartphone form factors are expected to worsen this problem since routing traces will be more complicated, with added costs stemming from mitigation of interference as well as power implications of inter-chip communication.

The system-wide bandwidth challenge. System-wide bandwidth refers to the bandwidth between application processors and memories or application processors and other peripherals. As requirements for compute performance, #functionalities and display bandwidth keep growing (as indicated by the scaling of #APs, #GPUs, #sensors,  #pixels, and the communication bandwidth), delivering (energy-)proportionate system-wide bandwidth will become challenging. Another aspect of this challenge will be the tradeoffs between power management and bandwidth.

The communication bandwidth scaling challenge. A further challenge is implicit in the gaps between projections of required cellular data rate or WiFi data rate and achievable data rates. As the required communication standards supported by a single RF module proliferate, cost-feasible process and device technologies must enable smartphones to integrate more bands and communication standards within a fixed PCB footprint budget.

Microserver driver and metrics

In this section, we describe the main features, key metrics, key challenges, and potential solutions for the microserver driver.

Recent studies of datacenters (e.g., by Doller et al. [2]) suggest that high-performance MPU (MPU-HP) and networking SOC (SOC-NW) products are the main components in datacenters. These products may be implemented either in a single chip or in a multichip module (MCM). An optimized datacenter architecture cannot be achieved with a single chip as its key building block; rather a, co-optimization of storage, interconnects and software is required. Since the raw data stored in datacenters is usually sparse, pre-processing that is typically executed in traditional server cores is precluded, due to energy budget. Besides integration of power-efficient cores within an energy budget, datacenters require high bandwidth and accessibility for local memories (mostly non-volatile memories) to execute data-intensive operations. Due to datacenter-specific optimizations and system-level design requirements such as high rack density and cooling capacity, the metrics of servers in datacenters are different from those of server chips in existing products which are comprehended by ITRS.

Some new design challenges to microserver driver are introduced by their deployment in datacenters. Big data computing requires a drastic reduction in communication latencies to meet an under-100ms requirement, that is, data must be increasingly localized. The collected data suggest that the microserver driver addresses the cost issue by limiting the number of cores per rack unit and the latency issue by localizing user-specific search data. The volume of information in datacenters is anticipated to grow at a very high rate (every two years, or even faster). When users search for specific information, latencies can be on the order of tens of milliseconds because datacenters typically store information in a highly distributed manner. As datacenters grow in size, communication latencies increase along with power consumption (e.g., 75MW). To limit power and temperature of datacenters, companies are forced to invest huge amounts of money to establish and maintain power plants adjacent to datacenters, and to construct datacenters in geographies with “natural refrigeration”. There is a limit to such investment in power plants and cooling. Cooling costs, which can reach over 35% of electricity costs, continue to rise in server farms and datacenters; this creates a need to reduce the number of cores and operating frequencies to limit this cost.

To reduce operation cost, microservers must maximize the number of cores in a rack unit subject to power and thermal constraints. Form factor, energy efficiency, and networking throughput are important for this driver. As a consequence, demand for reduced form factor and system design effort drives the integration of the MPU and the chipset. Compared to a 1U server (MPU-HP in the 2013 ITRS), a microserver has a higher degree of integration as it includes on-chip Ethernet and peripheral hubs. Recent MPUs for microservers integrate application-specific accelerators to improve energy efficiency. Hence, high integration of functionalities is another potential challenge.

Key challenges and promising solutions

For the microserver driver, we identify the following challenges.

The service latency challenge. A growing challenge is posed by the crucial requirement for service latency.  Reference [3] proposes much more pessimistic metrics (from 50 percentile to 99 percentile latency) to ensure service quality could be guaranteed when Big Data are hosted. To address this application requirement, the solutions are expected to draw from a wide range of source technologies.

  • Since network performance is a key determinant of service latency, high-radix photonic switching networks are expected to be introduced to address the internode bandwidth requirement.
  • Conventional memory architectures will be unable to address access time requirements in hosting of Big Data; spindle-based hard drives will be replaced by non-volatile memories.
  • To improve the intra-node communication performance (e.g., MPU to memories or memories to NVMs), better heterogeneous integration solutions are expected.

The node density/cooling/power management challenge. To ease the cost of datacenter deployment, the following challenges are inherent in the enablement of sufficient computing resource with MPU cores and application-specific accelerators.

  • Moore’s Law should continue transistor scaling so that more functionalities can be integrated in the same die area, and to avoid power increases that result in too much demand for cooling.
  • Better memory integration (e.g., memory-over-logic) within each compute node is expected to ease the power management challenge by reducing the power impact.
  • Advanced power management techniques such as adaptive power management with on-die power sensors [6] are expected to be developed to address the power management issue.

The electro-optical integration challenge. Since the power and performance requirements of datacenter are both crucial, highly-integrated photonics inter-node networking is expected by 2020 [3]. Since the electro-optical interfaces are distributed all over the datacenter, it is necessary to develop on-chip photonic modulators and detectors to reduce the power, space, and performance overhead due to off-chip converters for electro-optical interfaces.


ITRS2.0 will, for the first time, via its system integration (SI) focus team, drive a top-down system-driven roadmap framework for key semiconductor industry drivers in the 2015-2030 period. The SI focus team is working to complete a roadmap of relevant metrics for Mobility (smartphone), Internet of Things (IoT), Big Data (microserver) drivers, and possibly other product segments that will be critical top-down drivers in the semiconductor industry of the next 15 years.


This overview draws from our recent paper [4]; we thank our coauthors Wei-ting Jonas Chan and Siddhartha Nath for their invaluable contributions.  We also thank members of the ITRS community, and other focus team leaders, for their feedback during the course of this work.



[2]. E. Doller et al., “DataCenter 2020: Near-memory Acceleration for Data-oriented Applications”, Proc. Symposium on VLSI Circuits, 2014


[4]. J.-A. Carballo, W.-T. J. Chan, P. A. Gargini, A. B. Kahng and S. Nath, “ITRS 2.0: Toward a Re-Framing of the Semiconductor Technology Roadmap”, Proc. Intl. Conf. on Computer Design, 2014.

SOI: Revolutionizing RF and expanding in to new frontiers

Friday, April 17th, 2015

By Peter A. Rabbeni, Director, RF Segment Marketing and Business Development, GLOBALFOUNDRIES

Faster connections and greater network capacity for wireless technologies such as LTE, WiFi, and the Internet of Things is driving the demand for more complex radio circuit designs and multi-band operation.  In addition the emergence of wirelessly connected smart wearables is not only driving localized high performance processing power but also extended battery life, two goals which are often in conflict. The predicted explosion in the IoT is shown in Figure 1.

Figure 1. More than 30 billion devices are forecast to be connected to the internet by 2018 (Source: BI Intelligence).

The rapid growth in smartphones and tablet PCs and other mobile consumer applications has created an opportunity and demand for chips based on RF-SOI technology, particularly for antenna interface and RF front end components such as RF switches and antenna tuners.  As a low cost and more flexible alternative to expensive gallium arsenide (GaAs) technologies, the vast majority of RF switches today are built on RF-SOI.

To address the highly complex, multi-band and multi-standard designs, RF front-end modules (RF FEM) require integration of multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management. Today these functions are addressed by different technologies. The RF SOI process technology enables design flexibility by integrating multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management to be integrated—all on the same die. The benefit of integrated radios is they consume   less power and smaller area than traditional radios. Therefore, mobile devices that exploit radio integration using RFSOI can offer more functions with better RF performance at competitive cost.

Mobile devices that implement RF SOI for RF Front End module functions benefit from higher levels of integration that combine with improved linearity and insertion loss, which translates to better transmitter efficiency and thus longer battery life enabling longer talk times (lower power) and faster downloads (higher signal-to-noise ratio).

Emerging technologies like RF-SOI and even FD-SOI have unique properties and capabilities beneficial in enabling RF circuit innovation and integration levels never before seen in silicon-based technologies.  Device ft, gm/I, well bias control and inherent isolation of the substrate all contribute to improved system level performance over competing technology resulting in the ability to achieve higher linearity, lower power, low loss, and low cost/small size.

Innovative solutions

An innovative technology that is currently addressing the ever-increasing challenges of RF front-end design is UltraCMOS 10 (Figure 2). This customer specific process, co-developed by GLOBALFOUNDRIES and Peregrine Semiconductor, demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions. For designers, it dramatically reduces the required engineering and validation time. And, for the end-user, they benefit from longer battery life, better reception, faster data rates and wider roaming range. With the qualification process complete, UltraCMOS 10 technology is now a fully qualified technology platform.

Figure 2. UltraCMOS 10 technology demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions (Source: Peregrine Semiconductor).

High speed digital-to-analog converters (DAC) are an essential component for direct-to-RF conversion architectures. Faster converter sampling speeds and greater peak-to-peak signal fidelity hold high promise in moving mobile digital signal processing closer to the antenna. It has been demonstrated that DACs on fully depleted SOI, achieve high linearity and very low power for nyquist bandwidths as wide as 5.5GHz. The RF architecture with a high-performance DAC results in lower power dissipation while synthesizing very wideband signals (Figure 3). This further demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna.

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Figure 3. Low power RF DAC demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna [1

Agile radio architectures are another key area that can address mobile architecture challenges and cost. Today, the analog RF frontend duplicates much of the circuitry for each band. To simplify, new advancements (Figure 4) in tunable structures and filters are being made to provide a single radio for multi-band/multi-mode frequency. SOI technology offers the possibility to develop tunable/reconfigurable RF FEMs to improve RF performance at competitive cost.


Figure 4. Cutting-edge developments in tunable filters [2

Creating an Ecosystem to Extend SOI to RF

As RF FEM architectures and design challenges become more and more complex, it becomes necessary to relieve some of the increased burden at all levels of the value chain. In order to provide better RF products—from system design and RF integrated circuits down to engineered substrate design—development teams can no longer expect to design in silos and be successful. Collaboration and co-optimization are becoming much more important as a result of the changing dynamics of the design-technology landscape.

Investing in the future is critical to address certain RF challenges such as radio architecture design in multiband, multimode mobile radios and ultra-low power (ULP) wireless devices. Successful collaboration will require adherence to standards to enable interoperability, otherwise, in this fragmented market, the industry won’t see the full benefit of all of the technology innovation. To succeed, we need collaboration at different levels, from R&D to ensure we have the world’s best talent trying to solve all of these problems, all the way through to business models.

There is no doubt that demand on our networks will continue grow and there are advanced chip technology challenges the industry needs to address to enable a higher level of integration and lower power consumption for future wireless communication. GLOBALFOUNDRIES is committed to enabling an SOI portfolio and ecosystem—from process, device, and circuit through system level IP— to lower customer design barriers and complexity and introduce new RF architectures that leverage SOI-based technologies.


1. E. Olieman, A.-J. Annema and B. Nauta, “A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist,,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium on , Honolulu, 2014.

2. Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumpernik, Bram Nauta, “A Forward-Body-Bias Tuned 450MHz Gm-C 3rd-Order Low Pass Filter in 28nm UTBB FD-SOI with >1VdBVp IIP3 over a 0.7 to 1V Supply”, ISSCC, San Francisco, 2015.

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