Part of the  

Solid State Technology

  Network

About  |  Contact

Posts Tagged ‘Imec’

Next Page »

Blog review March 17, 2014

Monday, March 17th, 2014

Pete Singer is delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th.

Phil Garrou takes a look at what was reported at SEMI’s 2.5/3D IC Summit held in Grenoble, focusing on presentations from Gartner, GLOBALFOUNDRIES, TSMC and imec. He writes that GLOBALFOUNDRIES has been detailing their imminent commercialization of 2.5/3D IC for several years, and provide a chart showing the current status report. TSMC offered a definition of their supply chain model where OSATS are now integrated.

Bharat Ramakrishnan of Applied Materials writes about the importance of wearable electronics in the Internet of Things (IoT) era, and the role that precision materials engineering will play. He note that one key part of the wearables ecosystem that is still in need of new innovations is the battery. Two of the biggest challenges to overcome are the thick form factor due to battery size, and the lack of adequate battery life, thus requiring frequent recharging.

The Week in Review: March 14, 2014

Friday, March 14th, 2014

Toshiba Corporation announced that it has brought a civil suit against Korea’s SK Hynix Inc. at the Tokyo District Court, under Japan’s Unfair Competition Prevention Act. The suit seeks damages for the wrongful acquisition and use of Toshiba’s proprietary technical information related to NAND flash memory, which Toshiba pioneered in 1987 and now jointly develops and produces with SanDisk Corporation of the U.S. SanDisk this week also filed a separate lawsuit against SK Hynix for theft of trade secrets.

This week, imec presented the development of fullerene-free organic photovoltaic (OPV) multilayer stacks achieving a record conversion efficiency of 8.4 percent. The imec team now proposes a simple three-layer stack to improve the spectral responsivity range. This device architecture comprises two fullerene-free acceptors and a donor, arranged as discrete heterojunctions. In addition to the traditional exciton dissociation at the central donor-acceptor interface, the excitons generated in the outer acceptor layer are first relayed by energy transfer to the central acceptor, and subsequently dissociated at the donor interface.  This results in a quantum efficiency above 75 percent between 400nm and 720nm. With an open-circuit voltage close to 1V, a remarkable power conversion efficiency of 8.4 percent is achieved. These results confirm that multilayer cascade structures are a promising alternative to conventional donor-fullerene organic solar cells.

STATS ChipPAC, a provider of advanced semiconductor packaging and test services, has designed and implemented an innovative new manufacturing method that is a significant paradigm shift from conventional wafer level manufacturing. This breakthrough approach, known as FlexLine, delivers an unmatched level of flexibility and cost savings for wafer level packaging (WLP).

CEA-Leti announced this week it has fabricated ultra-scaled split-gate memories with gate length of 16nm, and demonstrated their functionality, showing good writing and erasing performances with memory windows over 6V. The devices provide several benefits especially for contactless memory applications, such as enlargement of the memory window and increased functionality. Also because of an optimized fabrication step, the devices allow better control of spacer memory gate shape and length.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, this week announced that its patented NanoSpray conformal coating technology is now available on its newly introduced EVG150XT resist coating and developing system for high-volume manufacturing (HVM) semiconductor applications.  NanoSpray provides conformal coating of structures that have vertical sidewall angles—such as through-silicon vias (TSVs), through-glass vias and through-substrate vias used for 2.5D interposers and 3D-ICs—with thick polymer liners and photoresists.

Solid State Watch: March 7-13, 2014

Friday, March 14th, 2014
YouTube Preview Image

Blog review March 3, 2014

Monday, March 3rd, 2014

If you’ve ever gone to the grocery store and forgotten that one essential item, the question you face is how quickly can you run back in the store, get that necessary item, and be on your way home? Jeff Wilson of Mentor Graphics says that design teams often feel this way as they approach tapeout, only to be confronted with engineering change orders (ECOs). One major factor—the challenge of re-filling designs.

Phil Garrou provides his analysis of the presentations given at this year’s ISS meeting, focusing on those from IBM, Linx, imec, IHS and IBS. IBM’s Jon Casey, for example, notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Pete Singer hasn’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished. At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”

Solid State Watch: February 14-20, 2014

Friday, February 21st, 2014
YouTube Preview Image

The Week in Review: February 14, 2014

Friday, February 14th, 2014

Worldwide silicon wafer revenues declined by 13 percent in 2013 compared to 2012 according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments increased 0.4 percent in 2013 when compared to 2012 area shipments.

Silicon wafer area shipments in 2013 totaled 9,067 million square inches (MSI), slightly up from the 9,031 million square inches shipped during 2012. Revenues totaled $7.5 billion down from $8.7 billion posted in 2012. “Annual semiconductor silicon shipment levels have remained essentially flat for the past three years,” said Hiroshi Sumiya, chairman of SEMI SMG and general manager of the Corporate Planning Department of Shin-Etsu Handotai Co., Ltd. ”However, industry revenues have declined significantly for the past two years.”

Rudolph Technologies, Inc. announced this week the sale of its first NSX 320 TSV Metrology System to CEA-Leti, a research organization based in Grenoble, France, which, in the frame of the Nanoelec Research Technology Institute (Nanoelec RTI) program, is developing three-dimensional integrated circuit (3DIC) technologies that use through silicon vias (TSVs) to conduct signals among vertically-stacked chips. The new NSX 320 TSV system includes integrated 3D metrology that enables specialized measurements critical to the TSV process.

Honeywell announced today that it has introduced new RadLo low alpha plating anodes based on proprietary technology to help reduce alpha particle radiation that can lead to data errors in semiconductors. The new plating anodes for semiconductor packaging wafer bumping applications expand Honeywell’s RadLo offerings and employ proprietary Honeywell metrology and refining techniques.

At this week’s International Solid State Circuits Conference (ISSCC2014), imec and Holst Centre, together with Olympus, demonstrated a low-power single channel implantable electrocardiography (ECG) acquisition chip with analog feature extraction, which enables precise monitoring of the signal activity in a selected frequency band. Leadless Pacemakers with ultra-small size and ultra-low power consumption are emerging, improving analysis and clinical research of the intra-cardiac rhythm, and as a result, improving patients’ quality of life. The new low-power ECG acquisition chip advances the state-of-the-art by consuming only 680nA when all features are active, and also provides competitive performance, such as input SNR>70dB, CMRR >90dB, PSRR >80dB without any external passive components. By equipping an ultra-low power analog feature extractor, the new chip is capable of assisting digital signal processor platforms for the implementation of low-power heartbeat detection algorithms.

SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets today announced the opening of a new office in Korea. The new SPTS Korea office is situated in Pangyo and will be the central base of operations for sales, field process and engineering staff. The new facility will also carry essential and critical spares inventory to support SPTS’ system installed base.

Fujitsu Laboratories Ltd. and imec Holst Centre this week announced that they have developed a wireless transceiver circuit for use in body area networks (BAN) for medical applications that adheres to the 400 MHz-band  international standard. While the subject of high expectations for medical applications, wireless monitoring of brainwaves or other vital signs has in the past required over a dozen milliwatts (mW) of electric power. Now, however, by optimizing the architecture and circuitry, Fujitsu Laboratories and imec Holst Centre have succeeded in reducing the electric power requirements of wireless transceiver front-ends, to just 1.6 mW when receiving data and 1.8 mW when transmitting.

Solid State Watch: January 17-23, 2014

Friday, January 24th, 2014
YouTube Preview Image

Solid State Watch: January 9-16, 2014

Friday, January 17th, 2014
YouTube Preview Image

The Week In Review: Nov. 7, 2013

Friday, November 8th, 2013

Peregrine Semiconductor Corp. and GLOBALFOUNDRIES are sampling the first RF Switches built on Peregrine’s new UltraCMOS 10 RF SOI technologies. This partnership unites Peregrine’s 25 years of RF SOI experience with a tier-one foundry. In a joint development effort, GLOBALFOUNDRIES and Peregrine created a unique fabrication flow for the versatile, new, 130 nm UltraCMOS 10 technology platform. This new technology delivers a more than 50-percent performance improvement over comparable solutions. UltraCMOS 10 technology gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.

Peregrine Semiconductor this week celebrated two significant milestones – its 25th anniversary of pioneering RF SOI solutions and the shipment of the two-billionth chip. Peregrine reaches the two-billionth-chip milestone in an order to Murata Manufacturing Company, the supplier of RF front-end modules for the global mobile wireless marketplace.

Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters.  This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.

Semiconductor Research Corporation and Northeastern University researchers announced advancements in radio-frequency (RF) circuit technology that promise to improve and widen the applications of mobile devices.

Imec announced that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon.

STMicroelectronics announced this week its close collaboration with Memoir Systems has made the revolutionary Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully-depleted silicon-on-insulator (FD-SOI) process technology.

Sign up to receive more semiconductor news here.

Research News: Nov. 5, 2013

Tuesday, November 5th, 2013

Imec, a nanoelectronics research center, announced today that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon. The breakthrough not only enables continual CMOS scaling down to 7nm and below, but also enables new heterogeneous system opportunities in hybrid CMOS-RF and CMOS-optoelectronics. “To our knowledge, this is the world’s first functioning CMOS compatible IIIV FinFET device processed on 300mm wafers,” stated An Steegen, senior vice president core CMOS at imec. “This is an exciting accomplishment, demonstrating the technology as a viable next-generation alternative for the current state-of-the-art Si-based FinFET technology in high volume production.”

Columbia Engineering researchers have experimentally demonstrated for the first time that it is possible to electrically contact an atomically thin two-dimensional (2D) material only along its one-dimensional (1D) edge, rather than contacting it from the top, which has been the conventional approach. With this new contact architecture, they have developed a new assembly technique for layered materials that prevents contamination at the interfaces, and, using graphene as the model 2D material, show that these two methods in combination result in the cleanest graphene yet realized. The study is published in Science on November 1, 2013. The researchers fully encapsulated the 2D graphene layer in a sandwich of thin insulating boron nitride crystals, employing a new technique in which crystal layers are stacked one-by-one. Once they created the stack, they etched it to expose the edge of the graphene layer, and then evaporated metal onto the edge to create the electrical contact. By making contact along the edge, the team realized a 1D interface between the 2D active layer and 3D metal electrode. And, even though electrons entered only at the 1D atomic edge of the graphene sheet, the contact resistance was remarkably low, reaching 100 Ohms per micron of contact width—a value smaller than what can be achieved for contacts at the graphene top surface.

UPV/EHU-University of the Basque Country researchers have developed and patented a new source of light emitter based on boron nitride nanotubes and suitable for developing high-efficiency optoelectronic devices. Scientists are usually after defect-free nano-structures. Yet in this case the UPV/EHU researcher Angel Rubio and his collaborators have put the structural defects in boron nitride nanotubes to maximum use. The outcome of his research is a new light-emitting source that can easily be incorporated into current microelectronics technology. The research has also resulted in a patent.

Next Page »