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Research Alert: June 24, 2014

Tuesday, June 24th, 2014

imec joins Graphene Flagship

To coincide with Graphene Week 2014, the Graphene Flagship announced that today one of the largest-ever European research initiatives is doubling in size. Sixty-six new partners are being invited to join the consortium following the results of a €9 million competitive call. While most partners are universities and research institutes, the share of companies, mainly SMEs, involved is increasing. This shows the growing interest of economic actors in graphene. The partnership now includes more than 140 organizations from 23 countries. It is fully set to take “wonder material” graphene and related layered materials from academic laboratories to everyday use.

“Imec aims to show that graphene can form the basis of practical optoelectronic devices, such as high speed modulators and detectors, for use in low power optical interconnects,” said Cedric Huyghebaert, team leader of imec’s graphene group. “During the past five years, we have built a strong knowledge in graphene device making, focused on the generic building blocks like contacting, doping and gate engineering, which are essential to progress in any graphene application. This knowledge, combined with our unique experience in integrating novel materials into CMOS-processes, and our optoelectronic silicon waveguide platform, makes imec a very suitable place to develop hybrid-silicon-graphene optoelectronic devices compatible with CMOS.”

Collecting light with artificial “moth eyes”

All over the world researchers are investigating solar cells which imitate plant photosynthesis, using sunlight and water to create synthetic fuels such as hydrogen. Empa researchers have developed such a photoelectrochemical cell, recreating a moth’s eye to drastically increase its light collecting efficiency. The cell is made of cheap raw materials – iron and tungsten oxide.

Rust – iron oxide – could revolutionize solar cell technology. This usually unwanted substance can be used to make photoelectrodes which split water and generate hydrogen.  Sunlight is thereby directly converted into valuable fuel rather than first being used to generate electricity. Unfortunately, as a raw material iron oxide has its limitations. Although it is unbelievably cheap and absorbs light in exactly the wavelength region where the sun emits the most energy, it conducts electricity very poorly and must therefore be used in the form of an extremely thin film in order for the water splitting technique to work. The disadvantage of this is that these thin-films absorb too little of the sunlight shining on the cell.

Empa researchers Florent Boudoire and Artur Braun have now succeeded in solving this problem. A special microstructure on the photoelectrode surface literally gathers in sunlight and does not let it out again. The basis for this innovative structure are tiny particles of tungsten oxide which, because of their saturated yellow colour, can also be used for photoelectrodes. The yellow microspheres are applied to an electrode and then covered with an extremely thin nanoscale layer of iron oxide. When external light falls on the particle it is internally reflected back and forth, till finally all the light is absorbed. All the entire energy in the beam is now available to use for splitting the water molecules.

In principle the newly conceived microstructure functions like the eye of a moth, explains Florent Boudoire. The eyes of these night active creatures need to collect as much light as possible to see in the dark, and also must reflect as little as possible to avoid detection and being eaten by their enemies. The microstructure of their eyes especially adapted to the appropriate wavelength of light. Empa’s photocells take advantage of the same effect.

In order to recreate artificial moth eyes from metal oxide microspheres, Florent Boudoire sprays a sheet of glass with a suspension of plastic particles, each of which contains at its center a drop of tungsten salt solution. The particles lie on the glass like a layer of marbles packed close to each other. The sheet is placed in an oven and heated, the plastic material burns away and each drop of salt solution is transformed into the required tungsten oxide microsphere. The next step is to spray the new structure with an iron salt solution and once again heat it in an oven.

A silicon replacement? USC Viterbi School of Engineering overcomes major issue in carbon nanotube tech

When it comes to electronics, silicon may one day have to share the spotlight. In a paper recently published in Nature Communications, researchers from the USC Viterbi School of Engineering describe how they have overcome a major issue in carbon nanotube technology by developing a flexible, energy-efficient hybrid circuit combining carbon nanotube thin film transistors with other thin film transistors. This hybrid could take the place of silicon as the traditional transistor material used in electronic chips, since carbon nanotubes are more transparent, flexible, and can be processed at a lower cost.

Electrical engineering professor Dr. Chongwu Zhou and USC Viterbi graduate students Haitian Chen, Yu Cao, and Jialu Zhang developed this energy-efficient circuit by integrating carbon nanotube (CNT) thin film transistors (TFT) with thin film transistors comprised of indium, gallium and zinc oxide (IGZO).

“I came up with this concept in January 2013,” said Dr. Chongwu Zhou, professor in USC Viterbi’s Ming Hsieh Department of Electrical Engineering. “Before then, we were working hard to try to turn carbon nanotubes into n-type transistors and then one day, the idea came to me. Instead of working so hard to force nanotubes to do something that they are not good for, why don’t we just find another material which would be ideal for n-type transistors—in this case, IGZO—so we can achieve complementary circuits?”

Carbon nanotubes are so small that they can only be viewed through a scanning electron microscope. This hybridization of carbon nanotube thin films and IGZO thin films was achieved by combining their types, p-type and n-type, respectively, to create circuits that can operate complimentarily, reducing power loss and increasing efficiency. The inclusion of IGZO thin film transistors was necessary to provide power efficiency to increase battery life. If only carbon nanotubes had been used, then the circuits would not be power-efficient. By combining the two materials, their strengths have been joined and their weaknesses hidden.

Zhou likened the coupling of carbon nanotube TFTs and IGZO TFTs to the Chinese philosophy of yin and yang.

“It’s like a perfect marriage,” said Zhou. “We are very excited about this idea of hybrid integration and we believe there is a lot of potential for it.”

3D memory for future nanoelectronic systems

Wednesday, June 18th, 2014

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By Ed Korczynski, Sr. Technical Editor

The future of 3D memory will be in application-specific packages and systems. That is how innovation continues when simple 2D scaling reaches atomic-limits, and deep work on applications is now part of what global research and development (R&D) consortium Imec does. Imec is now 30 years old, and the annual Imec Technology Forum held in the first week of June in Brussels, Belgium included fun birthday celebrations and very serious discussions of the detailed R&D needed to push nanoelectronics systems into health-care, energy, and communications markets.

3D memory will generally cost more than 2D memory, so generally a system must demand high speed or small size to mandate 3D. Communications devices and cloud servers need high speed memory. Mobile and portable personalized health monitors need low power memory. In most cases, the optimum solution does not necessarily need more bits, but perhaps faster bits or more reliable bits. This is why the Hybrid Memory Cube (HMC) provides >160Gb/sec data transfer with Through-Silicon Vias (TSV) through 3D stacked DRAM layers.

“We’re not adding 70-80% more bits like we used to per generation, or even the 40% recently,” explained Mark Durcan, chief executive officer of Micron Technology. “DRAM bits will only grow at the low to mid-20%.” With those numbers come hopes of more stability and less volatility in the DRAM business. Likewise, despite the bit growth rates of the recent past, NAND is moving to 30-40%  bit-increase per new ‘generation.’

“Moore’s Law is not over, it’s just slowing,” declared Durcan. “With NAND, we’re moving from planar to 3D, and the innovation is that there are different ways of doing 3D.” Figure 1 shows the six different options that Micron defines for 3D NAND. Micron plans for future success in the memory business to be not just about bit-growth, but about application-specific memory solutions.

Fig. 1: Different options for Vertical NAND (VNAND) Flash memory design, showing cell layouts and key specifications. (Source: Micron Technology)

E. S. Jung, executive vice president Samsung Electronics, presented an overview of how “Samsung’s Breaking the Limits of Semiconductor Technology for the Future” at the Imec forum. Samsung Semiconductor announced it’s first DRAM product in 1984, and has been improving it’s capabilities in design and manufacturing ever since. Samsung also sees the future of memory chips as part of application-specific systems, and suggests that all of the innovation in end-products we envision for the future cannot occur without semiconductor memory.

Samsung’s world leading 3D vertical-NAND (VNAND) chips are based on simultaneous innovation in three different aspects of materials and design:

1)    Material changed from floating-gate,

2)    Rotated structure from horizontal to vertical (and use Gate All Around), and

3)    Stacked layers.

To accomplish these results, partners were needed from OEM and specialty-materials suppliers during the R&D of the special new hard-mask process needed to be able to form 2.5B vias with extremely high aspect-ratios.

Rick Gottscho, executive vice president of the global products group Lam Research Corp., in an exclusive interview with SST/SemiMD, explained that with proper control of hardmask deposition and etch processes the inherent line-edge-roughness (LER) of photoresist (PR) can be reduced. This sort of integrated process module can be developed independently by an OEM like Lam Research, but proving it in a device structure with other complex materials interactions requires collaboration with other leading researchers, and so Lam Research is now part of a new ‘Supplier Hub’ relationship at Imec.

Luc Van den hove, president and chief executive officer of Imec, commented, “we have been working with equipment and materials suppliers form the beginning, but we’re upgrading into this new ‘Supplier Hub.’ In the past most of the development occurred at the suppliers’ facilities and then results moved to Imec. Last year we announced a new joint ‘patterning center’ with ASML, and they’re transferring about one hundred people from Leuven. Today we announced a major collaboration with Lam Research. This is not a new relationship, since we’ve been working with Lam for over 20 years, but we’re stepping it up to a new level.”

Commitment, competence, and compromise are all vital to functional collaboration according to Aart J. de Geus, chairman and co-chief executive officer of Synopsys. Since he has long lead a major electronic design automation (EDA) company, de Geus has seen electronics industry trends over the 30 years that Imec has been running. Today’s advanced systems designs require coordination among many different players within the electronics industry ecosystem (Figure 2), with EDA and manufacturing R&D holding the center of innovation.

Fig. 2: Semiconductor manufacturing and design drive technology innovation throughout the global electronics industry. (Source: Synopsys)

“The complexity of what is being built is so high that the guarantee that what has been built will work is a challenge,” cautioned de Geus. Complexity in systems is a multiplicative function of the number of components, not a simple summation. Consequently, design verification is the greatest challenge for complex System-on-Chips (SoC). Faster simulation has always been the way to speed up verification, and future hardware and software need co-optimization. “How do you debug this, because that is 70% of the design time today when working with SoCs containing re-used IP? This will be one of the limiters in terms of product schedules,” advised de Geus.

Whether HMC stacks of DRAM, VNAND, or newer memory technologies such as spintronics or Resistive RAM (RRAM), nanoscale electronic systems will use 3D memories to reduce volume and signal delays. “Today we’re investigating all of the technologies needed to advance IC manufacturing below 10nm,” said Van den hove. The future of 3D memories will be complex, but industry R&D collaboration is preparing the foundation to be able to build such complex structures.

DISCLAIMER:  Ed Korczynski has or had a consulting relationship with Lam Research.

Blog review June 16, 2014

Monday, June 16th, 2014

An upcoming webcast will focus on The Rise of MEMS Sensors. Jay Esfandyari from STMicroelectronics will talk about how the introduction of MEMS technology into consumer markets has opened the floodgates with multiple MEMS – accelerometers, gyros, compasses, pressure sensors and microphones – in games such as the Wii and now in smartphones and tablets. Simone Severi from imec will Next, Simone Severi, lead for SiGe MEMS at imec, will discuss SiGe MEMS technology for monolithic integration on CMOS.

The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI. Adele Hars blogs that they’ve covered all the bases, so that designers going to Samsung’s foundry services for ST’s 28nm FD-SOI can hit the ground running.

Phil Garrou reports on the 16th biennial Symposium on Polymers, which was held this May in Wilmington DE. In this blog post, he analyzes presentations from Fraunhofer IZM, ASE and Hitachi Chemicals.

Jamie Girard, senior director, Public Policy, SEMI North America, blogs that with changes coming in Washington, SEMI has important work ahead supporting the innovators and job creators of this country. Advancing the goals of its members, SEMI advocates legislation in congress, targeting passage of the Commerce, Justice and Science Appropriations Act, increases to NSF and NIST funding and changes to R&D tax credits.

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Prakash Arunkundrum, PwC Strategy and Operations Consulting Director blogs about improving financial predictability. He notes that there is continued evidence that despite spending several millions on IT transformations, improving internal planning processes, maturing supply chains, and streamlining product development processes, several companies still struggle with predicting their financial and operational performance.

The Week in Review: June 6, 2014

Friday, June 6th, 2014

After two years of decline, fab equipment spending for Front End facilities in 2014 is expected to increase 24 percent in 2014 (US$35.7 billion), according to the May 2014 SEMI World Fab Forecast Report released this week.

This week, the Society for Information Display (SID) unveiled the winners of its prestigious 19th annual Display Industry Awards.

The Semiconductor Industry Association (SIA) this week announced that worldwide sales of semiconductors reached $26.34 billion for the month of April 2014.

Imec announced this week that it is collaborating with Samsung Electronics to accelerate innovation and collaboration among technology companies and researchers working in the burgeoning mobile wearable field.

Synopsys, Inc. and Intel Corporation this week announced broad SoC design enablement for Intel’s 14nm Tri-Gate process technology for use by customers of Intel Custom Foundry.

Blog review March 17, 2014

Monday, March 17th, 2014

Pete Singer is delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th.

Phil Garrou takes a look at what was reported at SEMI’s 2.5/3D IC Summit held in Grenoble, focusing on presentations from Gartner, GLOBALFOUNDRIES, TSMC and imec. He writes that GLOBALFOUNDRIES has been detailing their imminent commercialization of 2.5/3D IC for several years, and provide a chart showing the current status report. TSMC offered a definition of their supply chain model where OSATS are now integrated.

Bharat Ramakrishnan of Applied Materials writes about the importance of wearable electronics in the Internet of Things (IoT) era, and the role that precision materials engineering will play. He note that one key part of the wearables ecosystem that is still in need of new innovations is the battery. Two of the biggest challenges to overcome are the thick form factor due to battery size, and the lack of adequate battery life, thus requiring frequent recharging.

The Week in Review: March 14, 2014

Friday, March 14th, 2014

Toshiba Corporation announced that it has brought a civil suit against Korea’s SK Hynix Inc. at the Tokyo District Court, under Japan’s Unfair Competition Prevention Act. The suit seeks damages for the wrongful acquisition and use of Toshiba’s proprietary technical information related to NAND flash memory, which Toshiba pioneered in 1987 and now jointly develops and produces with SanDisk Corporation of the U.S. SanDisk this week also filed a separate lawsuit against SK Hynix for theft of trade secrets.

This week, imec presented the development of fullerene-free organic photovoltaic (OPV) multilayer stacks achieving a record conversion efficiency of 8.4 percent. The imec team now proposes a simple three-layer stack to improve the spectral responsivity range. This device architecture comprises two fullerene-free acceptors and a donor, arranged as discrete heterojunctions. In addition to the traditional exciton dissociation at the central donor-acceptor interface, the excitons generated in the outer acceptor layer are first relayed by energy transfer to the central acceptor, and subsequently dissociated at the donor interface.  This results in a quantum efficiency above 75 percent between 400nm and 720nm. With an open-circuit voltage close to 1V, a remarkable power conversion efficiency of 8.4 percent is achieved. These results confirm that multilayer cascade structures are a promising alternative to conventional donor-fullerene organic solar cells.

STATS ChipPAC, a provider of advanced semiconductor packaging and test services, has designed and implemented an innovative new manufacturing method that is a significant paradigm shift from conventional wafer level manufacturing. This breakthrough approach, known as FlexLine, delivers an unmatched level of flexibility and cost savings for wafer level packaging (WLP).

CEA-Leti announced this week it has fabricated ultra-scaled split-gate memories with gate length of 16nm, and demonstrated their functionality, showing good writing and erasing performances with memory windows over 6V. The devices provide several benefits especially for contactless memory applications, such as enlargement of the memory window and increased functionality. Also because of an optimized fabrication step, the devices allow better control of spacer memory gate shape and length.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, this week announced that its patented NanoSpray conformal coating technology is now available on its newly introduced EVG150XT resist coating and developing system for high-volume manufacturing (HVM) semiconductor applications.  NanoSpray provides conformal coating of structures that have vertical sidewall angles—such as through-silicon vias (TSVs), through-glass vias and through-substrate vias used for 2.5D interposers and 3D-ICs—with thick polymer liners and photoresists.

Solid State Watch: March 7-13, 2014

Friday, March 14th, 2014
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Blog review March 3, 2014

Monday, March 3rd, 2014

If you’ve ever gone to the grocery store and forgotten that one essential item, the question you face is how quickly can you run back in the store, get that necessary item, and be on your way home? Jeff Wilson of Mentor Graphics says that design teams often feel this way as they approach tapeout, only to be confronted with engineering change orders (ECOs). One major factor—the challenge of re-filling designs.

Phil Garrou provides his analysis of the presentations given at this year’s ISS meeting, focusing on those from IBM, Linx, imec, IHS and IBS. IBM’s Jon Casey, for example, notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Pete Singer hasn’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished. At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”

Solid State Watch: February 14-20, 2014

Friday, February 21st, 2014
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The Week in Review: February 14, 2014

Friday, February 14th, 2014

Worldwide silicon wafer revenues declined by 13 percent in 2013 compared to 2012 according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments increased 0.4 percent in 2013 when compared to 2012 area shipments.

Silicon wafer area shipments in 2013 totaled 9,067 million square inches (MSI), slightly up from the 9,031 million square inches shipped during 2012. Revenues totaled $7.5 billion down from $8.7 billion posted in 2012. “Annual semiconductor silicon shipment levels have remained essentially flat for the past three years,” said Hiroshi Sumiya, chairman of SEMI SMG and general manager of the Corporate Planning Department of Shin-Etsu Handotai Co., Ltd. ”However, industry revenues have declined significantly for the past two years.”

Rudolph Technologies, Inc. announced this week the sale of its first NSX 320 TSV Metrology System to CEA-Leti, a research organization based in Grenoble, France, which, in the frame of the Nanoelec Research Technology Institute (Nanoelec RTI) program, is developing three-dimensional integrated circuit (3DIC) technologies that use through silicon vias (TSVs) to conduct signals among vertically-stacked chips. The new NSX 320 TSV system includes integrated 3D metrology that enables specialized measurements critical to the TSV process.

Honeywell announced today that it has introduced new RadLo low alpha plating anodes based on proprietary technology to help reduce alpha particle radiation that can lead to data errors in semiconductors. The new plating anodes for semiconductor packaging wafer bumping applications expand Honeywell’s RadLo offerings and employ proprietary Honeywell metrology and refining techniques.

At this week’s International Solid State Circuits Conference (ISSCC2014), imec and Holst Centre, together with Olympus, demonstrated a low-power single channel implantable electrocardiography (ECG) acquisition chip with analog feature extraction, which enables precise monitoring of the signal activity in a selected frequency band. Leadless Pacemakers with ultra-small size and ultra-low power consumption are emerging, improving analysis and clinical research of the intra-cardiac rhythm, and as a result, improving patients’ quality of life. The new low-power ECG acquisition chip advances the state-of-the-art by consuming only 680nA when all features are active, and also provides competitive performance, such as input SNR>70dB, CMRR >90dB, PSRR >80dB without any external passive components. By equipping an ultra-low power analog feature extractor, the new chip is capable of assisting digital signal processor platforms for the implementation of low-power heartbeat detection algorithms.

SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets today announced the opening of a new office in Korea. The new SPTS Korea office is situated in Pangyo and will be the central base of operations for sales, field process and engineering staff. The new facility will also carry essential and critical spares inventory to support SPTS’ system installed base.

Fujitsu Laboratories Ltd. and imec Holst Centre this week announced that they have developed a wireless transceiver circuit for use in body area networks (BAN) for medical applications that adheres to the 400 MHz-band  international standard. While the subject of high expectations for medical applications, wireless monitoring of brainwaves or other vital signs has in the past required over a dozen milliwatts (mW) of electric power. Now, however, by optimizing the architecture and circuitry, Fujitsu Laboratories and imec Holst Centre have succeeded in reducing the electric power requirements of wireless transceiver front-ends, to just 1.6 mW when receiving data and 1.8 mW when transmitting.

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