By Mark LaPedus

A group of 19 European companies and academic institutions have launched a three-year, 360 million euro ($464.5 million) pilot-line project to support the industrialization of fully-depleted silicon-on-insulator (FD-SOI) technology.

The project, dubbed Places2Be, is led by one of the biggest proponents of FD-SOI–STMicroelectronics. In addition, STMicroelectronics and GlobalFoundries will provide the manufacturing capabilities for the program. Separately, GlobalFoundries is also joining Imec’s advanced MRAM project.

Meanwhile, Places2Be, which stands for “Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe,” is aimed to support the deployment of FD-SOI pilot lines at 28nm and beyond.  It will also drive the creation of a European microelectronics design ecosystem using this FD-SOI platform and explore the path towards the next step for this technology at 14nm and 10nm.

The FD-SOI manufacturing sources for the project are located in two fabs. The first is the pilot line in STMicroelectronics’ Crolles fab, near Grenoble, France. The dual-source is in GlobalFoundries’ fab 1 in Dresden, Germany. STMicroelectronics and IBM are the biggest proponents for FD-SOI. Not long ago, STMicroelectronics signed an FD-SOI foundry deal with GlobalFoundries.

FD-SOI is a low-power, high-performance alternative to conventional bulk silicon and finFET technologies. The first FD-SOI systems-on-chips are expected to be used in consumer electronics, high-performance computing and networking.

The project includes participation of 19 partners from 7 countries, and the planned involvement of about 500 engineers over three years across Europe. Places2Be is the largest ENIAC Joint Undertaking project to date and is supported as well by the National Public Authorities in the participating countries. The ENIAC JU was set up in 2008 and will allocate grants throughout 2013. The projects selected for funding shall be executed till December of 2017. The total value of the R&D activities generated through ENIAC JU is estimated at 3 billion euros ($3.8 billion).

“The Places2Be project will reinforce the ecosystems of both Grenoble and Dresden clusters, while also positively impacting the whole value chain of microelectronics in Europe–large companies, SMEs, start-ups and research organizations–beyond the direct impact induced by the material and IP investments,” said François Finck, director of ST’s R&D cooperative programs and project coordinator, in a statement.

The Places2Be members include ACREO Swedish ICT AB,  Adixen Vacuum Products,  Axiom IC, Bruco Integrated Circuits, Commissariat à l’énergie atomique et aux énergies alternatives, Dolphin Integration,  Ericsson AB, eSilicon Romania S.r.l., Forschungzentrum Jülich Gmbh, GlobalFoundries Dresden, Grenoble INP, IMEC,  Ion Beam Services, Mentor Graphics France Sarl, Soitec, ST-Ericsson, STMicroelectronics, Université Catholique de Louvain, and the University of Twente.

In a separate move, GlobalFoundries is joining Imec and others to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology. The first IC manufacturer to join Imec’s R&D program on emerging memory technologies, GlobalFoundries completes the value chain of Imec’s research platform.

GlobalFoundries is joining a team with Qualcomm and several worldwide equipment suppliers providing the complete infrastructure necessary for R&D on STT-MRAM. In January, Qualcomm joined Imec’s STT-MRAM program.

STT-MRAM technology is a promising high-density alternative to existing memory technologies, like SRAM and DRAM. Together, imec and the program members aim to explore the potential of STT-MRAM, including performance below 1ns and scalability beyond 10nm for embedded and standalone applications.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”

By Mark LaPedus
Has Apple finally hit the wall after years of sizzling growth? “Relatively soft sales of large-format iPads and iPhones are likely to drive FQ2 revenue to $41.1 billion and FQ3 revenue to $33.5 billion, both of which are below the Street estimates of $42.8 billion and $40.0 billion, respectively,” according to a research note from Pacific Crest Securities. “Among them, we consider the reduction to our large-format iPad estimates to be the most significant, as this appears likely to be a sustained trend as tablet demand shifts to smaller and less expensive models. The shifts to our iPhone estimates are largely related to the product cycle, which we consider to be a transitory issue. However, we continue to believe sell-through evidence supports our view that the high end of the smartphone market is quickly becoming saturated.”

The semiconductor equipment market continues to consolidate. Hitachi High-Technologies has completed its acquisition of SII NanoTechnology from Seiko Instruments. SII, a supplier of photomask repair tools, has been placed into a new subsidiary called Hitachi High-Tech Science. The move also propels Hitachi High-Tech into the mask repair equipment business.

The European Commission is funding yet another 450mm program. The project, called Enable450, includes Intel and fab tool vendors. It is aimed at 450mm wafer processing, specifically targeting European material and equipment companies. The group also consists of U.S. tool vendors, as well. ASM International is the coordinator of the group. Other members are Applied Materials Israel, ASML, CEA-LETI, Fraunhofer, Future Horizons, IMEC, RECIF, SEMI, Soitec, among others. At present, there is no news to report beyond the formation of this group. Stay tuned.

IC Insights has released its top-50 semiconductor supplier rankings. In the rankings, Qualcomm registered a 34% surge in sales and moved up three positions to replace TI as the fourth-largest semiconductor supplier in 2012. GlobalFoundries registered better than 30% growth last year, moving from 21st place in the rankings in 2011 to 15th last year.

Taiwan DRAM maker ProMOS Technologies has agreed to sell its 300mm wafer fab and equipment to GlobalFoundries, according to Reuters.

Peregrine Semiconductor has filed a new suit, alleging the infringement of its RF silicon-on-insulator (SOI) technology by RF Micro Devices. This new legal action is in addition to an existing suit filed by Peregrine against RFMD in February 2012. That case is still pending.

In a blog, Applied Materials’ venture capital arm discusses the lessons it has learned to ensure the mutual success of a startup company and a corporate investor.

In another blog, Applied Materials talks about the evolution of the semiconductor service model. Instead of just repairing the equipment as in the past model, the new idea is to make fab tools work better, with higher output and lower cost of ownership.

SEMI Europe honored four industry leaders for their accomplishments in developing standards for the photovoltaics (PV) industry. The SEMI Standards awards were recently announced at the SEMI PV Fab Manager Forum 2013.

Why is there a need for “best practices” in mixed-signal SoC verification, and what are some of those practices? Cadence provides some insights in a video.

Mentor Graphics said that its FloEFD computational fluid dynamics (CFD) simulation solution helped Skeleton Bobsleigh World Championship winner Shelley Rudman of Great Britain to her first world championship win on Feb. 1 in St. Moritz, Switzerland.

Analog Devices announced that CEO Jerald Fishman passed away suddenly from an apparent heart attack. ADI President Vincent Roche has been appointed CEO on an interim basis by ADI’s board. In a research note, Doug Freedman, an analyst with RBC, said: ”If Jerry Fishman did not touch your life personally, his work and that of ADI have surely touched your life. I had the pleasure of competing against ADI for 12 years, and writing investment research about ADI for another 11 years. While Jerry was given a great company to run he did so much more than could be expected. ADI has been the envy of the analog IC industry for as long as I can remember. In Silicon Valley, we watched ADI build and maintain a data convertor and amplifier franchise that is unmatched in our industry. All the while, competitors tried extremely hard to take away the market share ADI had, and at every turn Jerry, and his east coast based team, turned away the efforts from Silicon Valley and Texas. In one instance, a competitor hired a team of engineers away from ADI and was able to get a foot hold into a market. Jerry fought back and won, not just in the market but in the courts having found patents that were violated. The far reaching impact of Jerry and the work at ADI is being felt in the areas of driver safety, medical imaging, and mobile communication (none of which would be as advanced as they are today without Jerry and his team of analog engineers). In recent years he had turned his attention on making the best better, not just technically but financially. The path he sought was always clear and easy to see, for all those that wished to follow him. I always enjoyed my interactions with him and will miss his conviction, thoughts and guidance. Jerry, Your legacy lives on in your family and ADI.”

China’s move to corner the market for rare-earth minerals (REMs) has prompted manufacturers of low-voltage industrial motors to adopt alternative technologies that reduce or eliminate the use of these materials, spurring new growth in the motors market, according to IHS.

By Mark LaPedus
At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969.

This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo over the potential use of DSA, an alternative patterning technology that enables fine pitches through the use of block copolymers.

A year later, DSA has joined the lithography establishment. Amazingly, within a short time span, DSA has moved from a mere curiosity item into the R&D mode at GlobalFoundries, IBM, Intel, Samsung and TSMC. “Companies are taking DSA seriously,” said Bencher, a DSA expert. “If you compared it to last year, we are now in the pre-competitive stage with DSA. The people in DSA have all grown up and are now wearing suits and ties.”

For some time, most chipmakers have kept their DSA efforts shrouded in secrecy. At the recent SPIE event, however, chipmakers finally provided the first glimpse of their initial work and results.

Based on the early findings, DSA still has a way to go before it moves into IC production. Chipmakers are just getting their arms around the problems. And they are still experimenting with an assortment of fab tools, flows, chemistries and design methodologies.

Still, the initial findings are also promising, providing a clue to where DSA is heading. For example, using DSA, Intel demonstrated 28nm structures. Separately, GlobalFoundries devised 28nm fins with DSA. IBM developed a silicon-on-insulator (SOI) DSA flow. And Samsung may have found the path towards sub-20nm DRAMs.

It’s still unclear when DSA will reach production. The projections range from the 14nm to 7nm nodes. “If you ask different people, you will get different answers,” said Joy Cheng, a research staff member at IBM.

DSA: From the lab to the fab?
DSA is not a next-generation lithography (NGL) tool per se, but rather it is a complementary and double-patterning scheme. DSA is also disruptive and threatens the status quo, because the process isn’t dependent on traditional and costly lithography. Many of the key processing steps are conducted in an existing wafer track system.

There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

In theory, DSA is attractive because it could reduce the overall cost of lithography. And compared to EUV, DSA requires less R&D funding.

“We don’t need billions of dollars,” said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications. “Materials development is inherently cheaper than tool development. The current funding is probably adequate to get the industry going for the 14nm node with DSA. If we’re talking about high chi polymers, which will be needed for the 10nm node and beyond, the industry should think about different funding mechanisms. But even so, we are not talking about huge sums.”

Meanwhile, over the last year, Albany Nanotech, CEA-Leti and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations. “Basically, DSA is still in the R&D stage,” said Charles Pieczulewski, director of strategic marketing for Sokudo, a wafer track supplier. “The industry is still working through the bugs with the materials.”

Going forward, the challenge is to bring DSA into the IC design and production phases. “The main challenge is device integration,” said Ben Rathsack, strategic marketing and technology manager at Tokyo Electron Ltd., the world’s largest wafer track supplier.

Last year, Applied’s Bencher listed defectivity as the top challenge for DSA, followed in order by registration, design flexibility and positional accuracy. For 2013, positional accuracy—or the ability to align the block copolymers in the proper place—has moved to the biggest challenge for DSA, Bencher said.

Bencher expects memory makers will be the early adopters for DSA, followed by logic and foundry vendors. The prediction is based on the ability to generate IC designs using DSA. “You hear people saying: ‘We need a whole design ecosystem to enable DSA.’ That might be true for logic, but these are the last people that would implement DSA. This is because you need the most flexible designs in logic,” Bencher said. “Memory makers don’t really need that whole design ecosystem. They need maybe 1% of the EDA ecosystem, compared to the logic people.”

Currently, there are several design approaches for DSA. One idea is using 1D gridded arrays, but the problems are obvious. “Designers don’t want to be restricted to having contacts only on a grid or vias on a grid,” Bencher said.

Another concept is laying down a sea of holes or fins on a pattern. “In the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which ones you want to keep and which ones you want to get rid of. But the problem is that the aerial image can be very sloppy,” he said.

And in another approach, Stanford University is developing an arbitrary design methodology for DSA using an alphabet soup of characters. In this approach, positional accuracy with the contact holes is the biggest challenge.

Chipmakers tip DSA efforts
Design is just one of the many challenges facing silicon foundries with DSA. For example, GlobalFoundries has set up a DSA R&D line at Albany Nanotech. Using chemical epitaxy, the company demonstrated three-stack, 28nm silicon fin structures. It also is experimenting with a graphoepitaxy flow.

“The advantage for using chemical epitaxy is that there is no loss for aerial density,” said Richard Farrell, a principal engineer at GlobalFoundries. “The advantage in working with graphoepitaxy is that it involves a relatively simple process. Some of the challenges that we face for graphoepitaxy is the translation of the edge roughness into the DSA pattern itself. For line/space, we need temperatures above 200 degrees. This has additional constraints on the lithographic performance of the resists.”

Bringing up DSA in a fab is another issue. “First, we have to deal with fab-compatibility in DSA processing,” he said. “There are contamination issues. In pattern transfer, we need to think about balance reflectivity and the use of planarization.”

Despite the challenges, chipmakers are moving full speed ahead with DSA—and for good reason. For example, NAND flash vendors are pushing 193nm immersion and multi-patterning to the limits, but suppliers are in dire need of a new solution. “EUV lithography and double patterning are widely known (to handle) sub-20nm patterning,” said Jaewoo Nam, a lithography engineer at Samsung, at the recent SPIE conference. “But EUV has some limitations. The pattern resolution for EUV is 16nm only. The cost is huge. Double patterning is also very complicated.”

Using DSA, Samsung is exploring the possibility of developing DRAMs at 18nm. Samsung’s initial goal with DSA is to devise 20nm contact holes. In a DSA R&D line, the company has implemented a graphoepitaxy flow using block PS-b-PMMA materials. With a proprietary treatment process, Samsung has improved the CD distribution by 28%, Nam said.

Like Samsung, Intel also is bullish about DSA. “DSA sparks off a dozen different ideas,” said Sam Sivakumar, a fellow and director of lithography at Intel. The possible applications for DSA include contact holes, vias, and the back-end-of-the-line (BEOL) flow, he said.

Intel is conducting its DSA R&D at IMEC. Last year, IMEC set up a 300mm DSA R&D line, which consists of TEL’s track systems. Using the University of Wisconsin flow, Intel devised a three-layer, 28nm stack. The stack includes an interconnect, via and a metal 1 layer.

Intel started with staggered contact hole arrays on a grid at 50nm to 55nm. After the pattern transfer process, the holes were reduced to 26nm to 22nm, representing a 35% shrink. With a blended DSA formula from JSR, Intel obtained the targeted resolutions with good results, said Todd Younkin, a lithography materials researcher at Intel. However, the results were less conclusive with traditional block copolymers, which are provided by both AZ Electronic Materials and Dow.

Another R&D organization, CEA-Leti, last year set up a 300mm DSA pilot line, which uses Sokudo’s track systems. Using PS-b-PMMA from Arkema and a graphoepitaxy process flow, CEA-Leti achieved resolutions from 35nm to 10nm, said Raluca Tiron, a senior scientist at CEA-Leti. “We showed good uniformity with three sigma around 2nm,” she said. “After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts.”

PS-b-PMMA is expected to hit the wall at 10nm, meaning the industry must develop next-generation high chi DSA materials. Others see it differently. “We think we can extend PS-b-PMMA down to the 7nm node,” said Laurent Pain, lithography lab manager at CEA-Leti.

Another player, IBM, is involved in several different DSA efforts. In one effort, IBM demonstrated a larger-pitch 42nm flow, which could one day enable the development of smaller chips based on SOI. In this experiment, IBM used both the Almaden and University of Wisconsin flows, which enabled 42nm and 28nm resolutions. “If we can do self-assembly at 42nm, we can do assembly at smaller pitches,” said Chi-Chun Liu, a research staff member at IBM.

By Mark LaPedus
Altera has entered into an agreement for the future manufacturing of its FPGAs based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant. That puts the processor giant on a collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC

The Altera-Intel deal could change the landscape in the foundry business, in which Intel will likely become a much bigger player in the arena. But does Intel have staying power to remain in the foundry business? Added John Vinh, an analyst from Pacific Crest Securities: Altera’s “foundry agreement with Intel is exclusive for the foreseeable future. We believe Altera will have exclusive access versus Xilinx at 14nm and effectively have the right of first refusal at 10nm. Strategically, we believe this is likely the most significant aspect of this agreement in that it prevents Xilinx from having access.”

At SPIE, ASML Holding disclosed various milestones with its extreme ultraviolet (EUV) lithography technology. ASML’s EUV production tool, dubbed the NXE:3300B, has demonstrated resolutions of 13nm for lines and spaces and 18nm contact holes. In addition, ASML demonstrated a 40-Watt source with dose control and under good collector protection conditions in six 1-hour runs. It also demonstrated a 55-Watt source in a 1 hour run. But that’s a far cry from the eventual goal. By 2015, ASML hopes to deliver a 250-Watt source for the NXE:3300B, thereby enabling a throughput of 126 wafers an hour.

With the help of self-aligned double patterning (SADP), sometimes called spacer, ASML’s NXE:3300B also demonstrated the ability to print lines and spaces down to 9nm. The work was done in conjunction with ASML, Applied Materials and Imec.

At the International Semiconductor Strategy Symposium in Europe (ISS Europe) on Feb. 24-26, the European semiconductor industry discussed 450mm fabs and other chip topics. In addition, European Commissioner Neelie Kroes floated the idea of creating an “Airbus for chips,” a European initiative for the semiconductor industry comparable to the launch of the Airbus in the aviation industry.

Also at ISS Europe, Malcolm Penn, chairman and CEO of Future Horizons, said that the decline of the major European chip makers has been a result of a defeatist attitude, not necessarily fundamental structural issues. He suggests European chip makers should build a 450mm fab jointly and operate it as a foundry.

SEMI has announced the release of “Global Trade War and Peace: Unified Approaches to a Global Solar Energy Solution,” a white paper containing recommendations to move beyond trade litigation and encourage an accelerated path towards dispute resolution.

In case your calendar has turned into a blur, take note: Semicon is near! SEMI, in collaboration with leading investment groups, has announced the Silicon Innovation Forum (SIF). The forum will bridge funding gaps for new and early-stage companies with manufacturing and technology solutions. SIF will be held in conjunction with Semicon West, on July 9 at the Moscone Center in San Francisco.

At the Mobile World Congress in Barcelona, Peregrine Semiconductor rolled out its latest version of its UltraCMOS process technology, dubbed Semiconductor Technology Platform 8 (STeP8). UltraCMOS is a variant of silicon-on-insulator (SOI) technology called silicon-on-sapphire (SoS).

Also in Spain, Skyworks Solutions said it is ramping several antenna-tuning products with leading smartphone manufacturers. The tuning devices are based on SOI technology.

The RATP Group, the fifth-largest urban transport operator worldwide, has awarded Soitec and Philips/Step an LED lighting contract for its metro and network stations.

Soitec and Medina College of Technology have signed a cooperative agreement for concentrating photovoltaic technology in Saudi Arabia.

GT Advanced Technologies has entered into a development and licensing agreement with Soitec to develop and commercialize a hydride vapor phase epitaxy (HVPE) system for producing GaN template substrates.

Mentor Graphics announced record financial results for the company’s fiscal fourth quarter and year ended Jan. 31.

During a conference call, Walden Rhines, chairman and CEO of Mentor, said the quarter was an all-time revenue and EPS record. Rhines also has a mixed forecast for the overall IC industry in 2013. “For next year, the analysts project mid-single-digit growth, but the general attitude is less positive,” he said.

Mentor Graphics rolled out the Kronos Cell Characterization and Analysis platform.

A blogger discusses Applied Materials, saying the company is at the cyclical trough and its prospects should improve with an increase in equipment spending.

Applied Materials announced that Bob Halliday has been named senior vice president and chief financial officer. Halliday previously was executive vice president and chief financial officer of Varian Semiconductor Equipment Associates prior to Applied’s acquisition of the company in November 2011.

Micron Technology announced the Tokyo District Court’s issuance of an order approving Elpida’s plan of reorganization. Elpida’s plan of reorganization calls for Micron to acquire Elpida. In addition, mixed-signal foundry specialist LFoundry has acquired Micron’s fab in Italy.

Whatever happened to Conexant Systems? The chipmaker recently went private to avoid a takeover. Now, the company this week implemented a restructuring agreement. As part of the plan, Conexant voluntarily filed protection under Chapter 11 of the United States Bankruptcy Code.

Photomask maker Photronics has announced its intent to acquire the shares of its majority-owned Taiwan subsidiary, PSMC.

After a loss and a proxy battle, Aetrium is considering options that may include a sale or other disposition of one or both of its reliability test and test handler product groups.

According to IHS, the competitive landscape of the cell-phone integrated circuits business has completely transformed over the past five years, with Qualcomm and Samsung capitalizing on the rise of smartphones and 4G.

By Mark LaPedus
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node.

Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts to introduce their initial finFET processes at 14nm. And the foundries are already defining their next-generation finFETs at 10nm.

Chipmakers face numerous challenges in terms of ramping up their first- and next-generation finFETs. But the challenges, and costs, could pale in comparison when vendors extend finFET technology to the 7nm and 5nm nodes—or perhaps beyond.

Starting at 7nm, chipmakers plan to inject finFETs with various and exotic III-V materials in the channels to boost the mobility, which refers to how fast the electrons can move through a device. Currently, the industry has narrowed the options down to about five leading candidates for the high-mobility finFET era: finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET.

The two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs. “Conventional thinking currently suggests that we will see a Ge PFET and an InGaAs NFET at 7nm,” said Dean Freeman, an analyst with Gartner. “If the industry could make a silicon nanowire, and create a transistor using silicon and high-k/metal-gate, then we could see the industry move in that direction.”

The III-V materials themselves exist today, but many of the associated manufacturing techniques are in their infancy or simply don’t exist. Bringing up compound semiconductor materials in silicon fabs is a monumental task. And the ability to design and integrate III-V finFETs in a cost-effective manner is easier said than done. “This is not a straightforward process,” said Luc Van den hove, chief executive of IMEC. “We are talking about materials with different lattice constants.”

The challenges leave some observers wondering whether chipmakers should skip the high-mobility finFET era and move directly to the more exotic technologies like carbon nanotubes and graphene. Perhaps the best avenue is the pursuit of stacked 2.5D/3D devices.

Looking into his crystal ball, Gary Patton, vice president of IBM’s Semiconductor Research and Development Center, predicts the two 3D-like approaches, finFETs and stacked die, will have a long and viable future. “The 3D era should carry us well into the 2020 timeframe,” Patton said. “I expect finFETs will last a decade. But then at some point, we hit the atomic dimension limit. Then, we’re talking about silicon nanowires and carbon nanotubes. And to deal with the interconnect issues, we have to talk about integrating photonics on the chip and stacking multiple chips together. That’s really in the next decade.”

Take III-V
Today, the industry is moving towards an inflexion point. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects. So, at 14nm, foundries will introduce finFETs, which have better short-channel electrostatic characteristics than planar.

Today’s finFETs will likely scale at least two generations to 10nm, said Subramani Kengeri, vice present of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V materials to provide a mobility boost, Kengeri said.

The next roadblock is that today’s strained-silicon technology is under stress. For some time, chipmakers have used a silicon-germanium (SiGe) alloy stressor in the channel to boost carrier mobility. “Starting from the 90nm and 65nm nodes, the source-drain areas have been grown using a SiGe epi process in order to bring strain into the device,” said IMEC’s Van den hove. “With strain, we can increase the drive current and device mobility. In the finFET structure, we can do that as well. But this space is very limited, because of the [difficulties] to introduce enough strain into those tiny channels. An alternative way to boost the drive current is by using materials that have intrinsically higher mobilities. This will reduce power consumption.”

The first of these high-mobility devices is expected to appear at 7nm, with the emergence of a finFET with Ge in the p channel and tensile silicon in the n channel. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,400cm-square-over-Vs for silicon.

“But germanium in the p channel is not a straightforward process,” said Aaron Thean, director of the logic program at IMEC. “Germanium tends to move around once exposed to temperature. So the challenges are defects and the structural stability of the device. The surface passivation (for the high-k/metal-gate stack) is also very tricky.”

Following this device, the industry will move to a next-generation high-mobility finFET at 7nm. The first option is a finFET with Ge for both the p and n channels. The second option is Ge for the p channel and indium gallium arsenide (InGaAs) for the n channel. InGaAs has an electron mobility of 12,000cm-square-over-Vs.

“Those two options are competing,” Thean said. “The germanium-germanium option requires compressively strained Ge in the p channel and relaxed Ge in n channel. There are issues with the gate stack and dopant activation.”

Intel and others are leaning toward the Ge-InGaAs option. “InGaAs is our front-up option. It can offer mobilities up to 10X and higher. It’s a better-understood III-V material. I wouldn’t say InGaAs is easy in terms of processing, but it is not as challenging of a material to handle,” Thean said.

The other 7nm candidate is the gate-all-around (GAA) finFET, which can have two or more gates that are wrapped around by a nanowire channel. Purdue University, for one, recently demonstrated GAA finFET with 20nm channel lengths and a sub-threshold swing of 63mV/decade. “There are still lots of challenges with GAA,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.”

Intel and others also have shown interest in the TFET, which may appear at 5nm. In TFET, a tunnel barrier is created at the source-channel contact to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5 volts, said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “TFETs enable steeper sub-threshold voltages,” he said.

There are other options, such as exotic III-V materials for both NFET and PFET. Other III-V materials, including indium antimonide (InSb), are still in R&D. The Sb materials are promising, but have narrow band gaps.

Tool gaps
All of the futuristic, high-mobility finFET devices suffer from the same problem—they are expensive and difficult to manufacture. The most obvious problem is lithography. It’s still unclear if extreme ultraviolet (EUV) lithography will be ready for the 7nm node, meaning the industry may need to extend 193nm immersion and multiple patterning.

Patterning is only one piece of the finFET puzzle. “Lithography has been the story for at least the last 10 years,” said Mike Splinter, chairman and chief executive of Applied Materials. “Now, we are seeing many of the bottlenecks in interface engineering, precision materials and how are you going to get the low-k values.”

For example, RF chipmakers have been fabricating III-V chips in trailing-edge fabs at smaller wafer sizes. At 7nm, the challenge is to grow III-V materials on 300mm or 450mm silicon wafers with good yields and throughput.

It’s unclear which technology, bulk or FD-SOI, will prevail at 7nm and beyond. STMicroelectronics says FD-SOI can extend to at least 10nm and perhaps beyond. “We are continuing to look at SOI,” said IMEC’s Thean. “The nice thing about fully-depleted devices on SOI is that they have excellent isolation.”

In one emerging SOI effort, Ed Nowak, device chief designer at IBM, recently described a fin-on-oxide (Fox) technology that could scale to 5nm. Fox enables a finFET technology with oxide dielectric isolation. Like SOI, Fox enables the finFET manufacturer to produce a controlled fin height, thereby reducing variability. Silicon wafer maker MEMC recently rolled out SOI substrates based on Fox.

The integration between III-V and silicon is perhaps the biggest issue. “In III-V, for example, we use gold as a contact material,” said Raj Jammy, vice president of emerging technologies at Sematech. “Gold is a poisonous material for silicon. So, you need to come up with a new contact metal scheme.”

There is also a need for new metrology tools to find defects in III-V finFETs. New tools are also are required for GAA finFETs with nanowires. “When it comes to gate all-around, you need selective ALD processes,” Jammy said. “For fin/gate fidelity, this requires selective III-V/Ge epi. For etch, we might not be able to use the processes we have today. We are looking into ALD etch.”

The industry is making progress on one front. “One of the areas we are looking at is a low damage conformal 3D doping technique, which we call monolayer doping,” he said. “This enables selective and very shallow junctions. We have solutions with arsenic and phosphorous. What is exciting about this is that the fins that have monolayer doping don’t have any damage.”

All told, high-mobility finFETs promise to enable chip scaling, but the challenges and costs are steep. “There is no free lunch,” he added.

By Mark LaPedus
In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations.

Dual damascene remains the workhorse process flow in the fab since its fabled introduction. But more recently, there are questions regarding the extendibility of the trusty dual damascene flow as the IC industry moves towards the 14nm node and beyond.

It all boils down to the interconnect. Copper interconnects—the tiny wiring schemes in devices—are becoming more compact at each node, causing an alarming increase in the resistance-capacitance (RC) delay. “The interconnect scaling roadmap looks like a looming disaster,” said Rob Aitken, an ARM fellow. “We want the materials to save us.”

The problem is that the dual damascene flow may extend to 10nm—and then could promptly run out of steam, according to some experts. Then, at 7nm, the industry may need to switch gears and move to a new flow—the single damascene process.

At 5nm, chip makers may need to switch again and re-visit the subtractive reactive ion etch (RIE) process for copper. Ironically, the industry explored the development of subtractive copper etch a decade ago, but the technology never got off the ground and was shelved.

Still others believe the risk-averse industry would rather extend the current technology as long as possible before moving to a new process. “I think dual damascene will extend to 10nm and probably the 7nm node,” said Daniel Edelstein, a fellow and manager of BEOL technology strategy at IBM. Edelstein was also the original project leader for IBM’s groundbreaking dual damascene efforts in the 1990s.

“I regard single damascene as a backup, not a front-up roadmap point,” he said. “Copper RIE is just one component of a subtractively etched multilevel copper wire and via integration, which I think is unworkable for copper.”

Beyond 7nm, the industry is looking at dual damascene, single damascene and copper RIE. In parallel, the industry is taking a different approach to the RC problem by working on stacked 2.5D and 3D chips. And for the distant future, the industry is looking at new transistor schemes, photonics and other technologies.

The looming crisis
For years, the industry has been grappling with a crisis in the interconnect. The industry averted a disaster in 1997, when IBM rolled out its CMOS 7S process, a 0.22-micron technology using the industry’s first dual damascene flow.

Until then, leading-edge logic devices deployed aluminum interconnects using an aluminum subtractive etch process. But as the industry moved towards 0.25-micron geometries and beyond, aluminum was unable to withstand the higher current densities in logic. And copper was (and still is) about 40% less resistive than aluminum, and it is less vulnerable to electromigration.

More recently, DRAM makers have made the transition from aluminum to copper. The shift towards copper requires a dual damascene process, which takes place at the back-end-of-the-line (BEOL) in the manufacturing flow. The process enables the formation of two main parts of the interconnect: metallization and low-k dielectrics.

In the dual damascene process, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin layer of barrier of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper seed barrier via PVD. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).

In the single damascene process, the trenches and vias are formed one step at a time. In contrast, they are formed simultaneously in dual damascene. Fewer steps make dual damascene a less expensive approach. And in a completely different flow, the copper subtractive process makes use of RIE tools.

Dual damascene, meanwhile, continues to extend and evolve. PVD, the workhorse tool technology for the metallization process in dual damascene, may extend to at least 10nm. But if PVD should stumble, the industry is evaluating rival tool technologies like chemical-vapor deposition (CVD) and atomic-layer deposition (ALD).

In the low-k part of the equation, however, the technology remains stuck. “The RC delay is increasing,” said Dean Freeman, an analyst with Gartner. “To improve the RC delay, you need lower k materials. But to get lower k, you need to add more porosity or air to the dielectric material. That compromises the structural integrity of the dielectric. It also makes it more difficult to keep the copper from diffusing into the dielectric and causing shorts, or leakage between metal lines.”

There are also challenges in the metallization process. “The resistance of the copper is also increasing. As you get smaller and smaller vias and lines, you get smaller and smaller grains. A smaller grain/crystal means that you have more electron scatter, which increases the resistance and the heat in the device. This is why the device manufacturers are trying to keep the metal lines as wide as possible where they can,” Freeman said.

At 14nm, in fact, the interconnect is headed toward an “inflection point,” in which copper resistivity increases exponentially, said Mehul Naik, a distinguished member of the technical staff at Applied Materials.

“The question is how long you can extend copper damascene,” Naik said. “From a resistive perspective, how can you get more and more copper inside the trenches and how can you design your materials so you get rid of scattering issues that increase the copper resistivity. It’s maximizing the volume and minimizing the scattering of copper. If we can achieve that, we can extend damascene as far as possible. But that goes back into how you pattern the copper and get the fine pitch, and what kinds of issues you run into when you get a fine pitch.”

If dual damascene runs out of steam, the industry is looking at single damascene technology and subtractive copper etch. In theory, the single damascene approach could potentially enable smaller gaps with higher aspect ratios, but it is more expensive, Naik said.

Unlike single damascene, which may use existing tool technologies and materials, the industry may need to start from scratch in subtractive copper etch. “There are no tools (in the market),” he said. “So, you would need to develop a copper etch process.”

What’s next?
Looking into his crystal ball, IBM’s Edelstein sees dual damascene extending to at least 7nm and predicts a cloudy future for copper RIE. “Single damascene would be the backup with penalties if dual damascene breaks irreparably,” he said.

“Copper RIE discussions always seem to neglect the classic copper integration problems that would come with it.  These problems were circumvented by going to damascene in the first place,” he said. “Why would bringing those unsolved problems back be any easier at vastly smaller dimensions? How would you propose to make a viable subtractive-etched multilevel copper BEOL line/via integration at competitive pitches, with all the needs for copper passivation, via contact, electrical and corrosion insulation, while at the same time retaining competitive cost, performance and reliability?”

Beyond 7nm, there are new and conventional approaches on the table. Even before 7nm, the industry is developing 2.5D/3D stacked chips to circumvent the RC delay problem. But advanced chip stacking has a number of challenges and is still a few years away from mass production

There are other and more futuristic technologies in R&D, many of which are exotic and expensive. The candidates include carbon nanotubes contacts, graphene, photonics, network-on-a-chip architectures, smart interconnects and others, said Jon Candelaria director of interconnect and packaging sciences at the Semiconductor Research Corp. (SRC).

For example, using a single damascene process, IMEC, TEL and others recently described 150nm diameter contacts filled with carbon nanotubes and a copper top metal. Carbon nanotubes before metallization reduced the single contact hole resistance from 4.8 kΩ down to 2.8 kΩ.

In a separate effort, Japan’s AIST recently fabricated multi-layer graphene interconnects directly on silicon dioxide by annealing sputtered amorphous carbon with a cobalt catalyst layer. A resistivity of around 500 μΩcm was obtained after cobalt removal.

And for years, the industry has been talking about the use of optical interconnects. “The bottom line is that the RC delay is increasing and there are no great solutions on the horizon other than copper and low-k,” said Gartner’s Freeman. “Ideally, the industry would like to go to a material with lower resistance, such as gold or carbon nanotubes for the interconnect. Unfortunately, gold is a bit too expensive and does not provide significant improvement over copper.”

Graphene is also expensive and involves some tough integration problems. “While nanotubes have demonstrated great promise, they have high resistance where they make contact to the metal lines. But IMEC has suggested that we are further along than people think on this topic,” Freeman said. “Optical interconnects are still a ways out. The big issue here is creating the laser and the collector in silicon, or on silicon. Intel continues to research this and I think they are getting close on chip-to-chip, but we are still a ways away from the technology.”

By Mark LaPedus
In today’s systems, consumers want more performance and bandwidth with a longer battery life.

Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the past few years,” said Abe Yee, senior director of advanced technology and package development at Nvidia. “Memory bandwidth has not kept up.”

In fact, there is a growing gap between memory bandwidth and overall system requirements, creating an unwanted I/O bottleneck, Yee said. The memory bandwidth gap, resistance-capacitance (RC) delays and other factors are fueling the development of new 3D DRAM schemes like Wide I/O. “We need Wide I/O memory,” he said. “We also need a known good die stack.”

But advanced chip stacking has a multitude of challenges and is still a few years away from mass production. One of the bigger, and sometimes forgotten, challenges is the ability to obtain and test known good die (KGD). A KGD is an unpackaged part or a bare die that meets a given specification.

As chip complexity increases, the industry may need to lower its targets and not expect a perfect KGD. In other words, the idea of having a KGD may not be attainable. “Ensuring KGD is (expected to be) more difficult in the ‘more than Moore Era,’ “ said Bill Bottoms, chairman and chief executive of ATE vendor Third Millennium Test Solutions (3MTS), in a recent presentation. “The era of known good die is drawing to an end. The concept of known good die will be displaced by ‘probably good die’ for very complex systems.”

Not all is lost, however. To address the KGD problem, the industry is developing a new class of probe cards. Chipmakers also are counting on a range of design-for-test (DFT) technologies, such as boundary scan, built-in-self-test (BIST), redundancy and repair, to enable the “probably good die” era.

Live and let die
KGD became a major issue in the 1980s, when the industry began to push multi-chip modules (MCMs) in systems. In MCMs, several unpackaged dies are stacked or assembled side-by-side within a module as a means to create smaller and faster systems.

MCMs met with limited success and a plethora of startups that were pushing the technology folded in the 1980s and 1990s. “The problem (with MCMs) was the dielectrics,” recalled Richard Otte, president and chief executive of Promex Industries, an IC packaging house. “The dielectrics were crummy.”

The other problem with MCMs was (and still is) the ability to obtain KGD. For years, the industry has procured KGD or bare die for use in MCMs, RF modules and system-in-packages (SIPs). Generally, a bare die takes up less space in a system compared with a traditional packaged part. For this reason, a large percentage of RF chips are sold as bare die and then assembled in RF modules. Analog chips, discretes, memories, MCUs and passives also can be sold as bare die.

Still, IC makers prefer to sell packaged parts, which can be tested in conventional ATE to ensure their quality. Bare die are sometimes viewed as a nuisance because they require specialized testing and handling. As a result, they are sold at a premium.

Selling KGD or bare die “is something chipmakers would prefer not to do,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC. “It’s hard to guarantee the quality of KGD. It is sometimes not possible to access all of the test vectors at the die level.”

The challenges escalate for 2.5D/3D designs. In chip stacking, the probability of obtaining KGD decreases. For example, the average yield for a memory wafer is around 50% today, said Robert Patti, chief technology officer for Tezzaron Semiconductor, a 3D DRAM supplier. For a four-layer stacked memory device, the average yield could go as low as 6%, he said, which he described as “not economically viable.”

The inadvertent use of a defective die is catastrophic in 2.5D/3D designs. It will result in yield loss. And in many cases, the entire part must be discarded.

There are other challenges, especially as chipmakers move towards heterogeneous 2.5D/3D designs. In one scenario, an IC maker may use an internal part. Then, the company obtains and integrates a separate bare die from another vendor. But if the device fails in the field, it’s unclear who will take responsibility for the faulty part.

Settling for imperfection
To attack the KGD problem, chipmakers will require breakthroughs on two basic fronts: probe cards and DFT. It also requires a different test flow. The flow for conventional packaged chips includes IC manufacturing, wafer sort, packaging and final test. Wafer sort is considered an initial screening process for packaged ICs.

In contrast, a bare die is not tested at final test using conventional ATE. Instead, a die is tested at wafer sort using a wafer prober. In this flow, chipmakers claim they can achieve a reliable KGD, but overall test costs are sometimes higher. Die failure rates are reduced, but they are never totally eliminated in wafer-level testing.

For 2.5D/3D testing, the industry is working on new probe card technology. A wafer prober is incorporated with a custom probe card, which itself has thousands of probing needles that hit the bond pads on a die. In effect, the prober detects defective die, which are eliminated.

In complex designs, the needles may miss some of the tiny bond pads on the die. The contact force of the needles also could damage the die. Concerning KGD in 2.5D/3D designs, the industry requires “improvements in fine-pitch probe technology,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). Specifically, the big challenge for the industry is to develop probe cards that can handle greater than 1,000 contacts and pitches below 50um, Rice said.

In probe cards, there are two basic camps. FormFactor and others are working on fine-pitch probe cards using MEMS-based technology. In another camp, IMEC and Cascade Microtech have been working on a “rocking beam interposer” (RBI) probe card technology. RBI is based on Cascade’s membrane technology. “The metal energy doesn’t bend. It rocks,” said Ken Smith, vice president of technology development at Cascade, a supplier of wafer probers and probe cards.

In RBI, the probe tips are 6um square and 15um tall. With tip forces below 1 gram-force, RBI has demonstrated 40um and below pitches with a pad damage less than 100nm deep. “This technology is still in the early stages of the development cycle,” Smith said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

Even with breakthroughs in probe cards, 3D test still remains a challenge. In the flow, 3D devices will require at least four more test steps: a pre-bond test before stacking; a mid-bond test in the partial stacking phase; a post-bond test after final stacking; and a final test. The interposer and TSVs may also require separate testing.

Conventional ATE cannot be used in many, or possibly any, of these steps. So test must start in the design phase with various DFT techniques. In one scenario envisioned by Mentor Graphics, boundary scan can be used to test the bottom die in a 2.5D/3D design. Embedded core test can be used to test the middle or other dies, according to Mentor.

“The bigger challenge is with stacked logic die,” said Steve Pateras, product marketing director at Mentor. “There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question.”

For years, memory makers have made use of BIST, repair and redundancy in their 2D designs, which may translate in the 2.5D/3D world. “With memory it’s easier, because there’s a robust testing methodology for bare memory die. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BIST,” Pateras said.

Using such techniques, 3D DRAM maker Tezzaron claims to have obtained better yields in 3D over 2D. “You have to change the way you think about design,” said Tezzaron’s Patti. “The secret to KGD is design-for-repair.”

Tezzaron refers to its design-for-repair and BIST solution as “BiSTAR.” Designed to repair bad memory cells and ensure a known good memory stack, BiSTAR includes 256 BIST sequencers, which run independently in parallel.

Besides repair and BIST, Patti said the industry must rethink its definition of KGD and may need to settle for something less. “Will we ever have 100% perfect KGD? It’s probably not practical,” he said. “A ‘kind of a good die’ may be acceptable. We may also have to accept the idea of having ‘not bad die.’”

By Mark LaPedus
Get ready for the 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco. At the event, slated for today through Wednesday, GlobalFoundries CEO Ajit Manocha will give a keynote, entitled: “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!”

Here are some of the papers and events at the IEDM event:

*A team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. Researchers have integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm.

*IBM will describe a fully-integrated SOI SRAM at 22nm.

*In a separate paper, CEA-LETI, STMicroelectronics, IBM, GlobalFoundries and Renesas will discuss FD-SOI for the 20nm node and beyond.

*STMicroelectronics will describe the performance of ultra-thin box and body technology. The SOI technology will provide a total power reduction of 30% to 40% at identical speed with respect to bulk thanks to back side gate biasing efficiency.

*National Chiao Tung University will discuss a high-performance Ge CMOS finFETs on a thin SOI wafer.

*Imec, GlobalFoundries and Samsung will talk about stress enhanced mobility for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond.

*Applied Materials and Synopsys will present a paper entitled, “Is strain engineering scalable in FinFET era?”

*SuVolta, a developer of low-power CMOS technologies, announced the results that demonstrate the performance and power advantages of its Deeply Depleted Channel (DDC) technology.

*The SOI Industry Consortium has organized a symposium that will address the world of fully depleted SOI. The symposium will be held at the San Francisco Hilton Hotel today, concurrent with the IEDM 2012 Conference.

*The 14nm node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. Tomorrow, Applied Materials will host a forum in San Francisco to explore the subject.

Intel’s push in the foundry business has the industry talking. Can the chip giant give the traditional foundries a run for their money? Some say no. In a report, Hans Mosesmann, an analyst with Raymond James, said: “The chatter that Intel should become a foundry for Apple/Qualcomm as a positive for the company is amusing to us given that foundries are the low-end of the semiconductor manufacturing totem-pole. Does it make sense for Intel to build $10 billion shiny new fabs for foundry work? We think not for 45-50% gross margins, and ask IBM how the foundry investment turned out. Intel’s fabs are not meant for the fragmented nature of foundries and truth be known, Intel is a laggard in SoC manufacturing anyway (at least today). Regardless, a formalized foundry strategy would be an acknowledgment by Intel that its model isn’t working and a negative for gross margins.”

Thanks to investments from Intel, Samsung and TSMC, ASML is developing a 450mm EUV scanner. But EUV remains delayed. So the industry is hedging its bets. In an announcement at Semicon Japan, Kazuo Ushida, president of Nikon, said that the company plans to ship 450mm, 193nm lithography tools in 2017 through a joint development effort with Intel. Nikon plans to have 450mm-enabled ArF immersion prototype tools in 2015-16.

In a video on SEMI’s site, Paul Farrar, general manager of the Global 450mm Consortium (G450C), discussed the progress and impact of the G450C.

AMD has amended its wafer supply agreement with GlobalFoundries. As part of the plan, AMD will reduce its procurement of wafers from GlobalFoundries.

International Rectifier introduced a series of high-current, ultra-low dropout hybrid linear voltage regulators based on SOI.

A team of ST and CEA-LETI received the 2012 Général Ferrié Award. They were honored for their work on FD-SOI technology.

ST has taken the decision to exit ST-Ericsson after a transition period and is currently in negotiations on exit options. This disengagement process has started, with the transition expected to end during the third quarter of 2013.  ST will continue to support ST-Ericsson as its supply-chain partner, advanced process-technology partner (FD-SOI) and application-processor IP provider.

Soitec will hold a grand opening celebration of its North American solar headquarters and manufacturing facility in San Diego on Dec. 19.

The Center for Science Teaching and Learning (CSTL) and Applied Materials announced a new clean tech competition challenge that addresses the global problem of access to clean water. The program, which now includes students from Singapore, as well as Xi’an, China, and California’s San Francisco Bay Area, was created last year to inspire the next generation of leaders and innovators in clean technology.

As a result of an equity investment, Qualcomm will become a minority shareholder in Sharp.

Axcelis will exit the dry-strip business to focus on the ion implanter market. Axcelis will sell its dry-strip business to Lam Research.

CyberOptics announced the completion of a restructuring and staff reduction totaling approximately 10% of its global workforce.

Signetics will double its capacity for flip chip package assembly within its factory in Paju, South Korea.

For most of the last two decades personal computers have accounted for a third or more of annual IC sales, but standard PCs are now on the brink of being replaced as the largest end-use product category for integrated circuits, according to IC Insights.

Amid weak economic conditions, IHS is downgrading its forecast for the global semiconductor market in 2012, with revenue now expected to decline by 2.3% for the year.

Sony next year is expected to purchase $8.4 billion worth of semiconductors, up nearly 5% from $8.0 billion in 2012, according to HIS. Meanwhile, Toshiba’s spending will increase 2.0% to $6.1 billion in 2013, up from $6.0 billion in 2012. In contrast, spending at the other major Japanese consumer electronics OEMs, Panasonic and Sharp, will decline in 2013 and 2014.