Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘Imec’

Next Page »

3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015

thumbnail

By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

MicroWatt Chips shown at ISSCC

Thursday, March 5th, 2015

thumbnail

By Ed Korczynski, Sr. Technical Editor

With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW). From analog to digital logic to radio-frequency (RF) chips and extending to complete system-on-chip (SoC) prototypes, silicon IC functionality is being designed with evolutionary and even revolutionary reductions in the operational power needed.

The figure shows a multi-standard 2.4 GHz radio that was co-developed by imec, Holst Centre, and Renesas using a 40nm node CMOS process. This was detailed in session 13.2 when Y.H. Liu presented “A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS.” It uses a digital-intensive RF architecture tightly integrated with the digital baseband (DBB) and a microcontroller (MCU), and the digital-intensive RF design reduces the analog core area to 1.3mm2, and the DBB/MCU/SRAM occupies an area of 1.1mm2. This is an evolution of a previous 90nm RF front-end design that results in a reduced supply voltage (20 percent), power consumption (25 percent), and chip area (35 percent).

Ultra-low-power multi-standard 2.4 GHz radio compliant with Bluetooth Low Energy and ZigBee, co-developed by imec, Holst Centre, and Renesas. (Source: Renesas)

“From healthcare to smart buildings, ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life,” said Harmke De Groot, Department Director at imec. “The radio consumes the majority of the power of the total system and is one of the most critical components to enable these emerging applications. Moreover, a low-cost area-efficient radio design is an important catalyst for developing small sensor applications, seamlessly integrated into the environment. Implementing an ultra-low power radio will increase the autonomy of the sensor device, increase its quality, functionality and performance and enable the reduction of the battery size, resulting in a smaller device, which in case of wearable systems, adds to user’s comfort.”

When most ICs were used in devices and systems that were powered by line current there was no advantage to minimizing power consumption, and so digital CMOS circuits could be designed with billions of transistors switching billions of times each second resulting in sufficient brute-force power to solve most problems. With power-consumption now a vital aspect of much of the demand for future chips, this year’s ISSCC offered the following tutorials on low-power chips:

  • “Ultra Low Power Wireless Systems” by Alison Burdett of Toumaz Group (UK),
  • “Low Power Near-threshold Design” by Dennis Sylvester of University of Michigan, and
  • “Analog Techniques for Low-Power Circuits” by Vadim Ivanov of Texas Instruments.

Then on Thursday the 26th, an entire short course was offered on “Circuit Design in Advanced CMOS Technologies:  How to Design with Lower Supply Voltages.” with lectures on the following:

  • “A Roadmap to Lower Supply Voltages – A System Perspective” by Jan M. Rabaey of UC Berkeley,
  • “Designing Ultra-Low-Voltage Analog and Mixed-Signal Circuits” by Peter Kinget of Columbia University,
  • “ACD Design in Scaled technologies” by Andrea Baschirotto of University of Milan-Bicocca, and
  • “Ultra-Low-Voltage RF Circuits and Transceivers” by Hyunchoi Shin of Kwangwoon University.

µW SoC Blocks

Session 5.10 covered “A 4.7MHz 53µW Fully Differential CMOS Reference Clock Oscillator with -22dB Worst-Case PSNR for Miniaturized SoCs” by J. Lee et al. of the Institute of Microelectronics (Singapore) along with researchers from KAIST and Daegu Gyeongbuk Institute of Science and Technology in Korea. While many SoCs for the IoT are intended for machine-to-machine networks, human interaction will still be needed for many applications so session 6.7 covered “A 2.3mW 11cm-Range Bootstrapped and Correlated-Double-Sampling (BCDS) 3D Touch Sensor for Mobile Devices” by L. Du et. al. from UCLA (California).

As indicated by the low MHz speed of the clock circuit referenced above, the only way that these ICs can consume 1/1000th of the power of mainstream chips is to operate at 1/1000th the speed. Also note that most of these chips will be made using 90nm- and 65nm-node fab processes, instead of today’s leading 22nm- and 14nm-node processes, as evidenced by session 8.3 covered “A 10.6µA/MHz at 16MHz Single-Cycle Non-Volatile Memory-Access Microcontroller with Full State Retention at 108nA in a 90nm Process” by V.K. Singhal et al. from the Kilby Labs of Texas Instruments (Bangalore, India). Session 18.3 covered “A 0.5V 54µW Ultra-Low-Power Recognition Processor with 93.5% Accuracy Geometric Vocabulary Tree and 47.5 Database Compression” by Y. Kim et al. of KAIST (Daejeon, Korea).

In the Low Power Digital sessions it was natural that ARM Cortex chips were the basis for two different presentations on ultra-low power functionality, since ARM cores power most of the world’s mobile processors, and since the RISC architecture of ARM was deliberately evolved for mobile applications. Session 8.1 covered “An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications” by J. Myers et al. of ARM (Cambridge, UK). In the immediately succeeding session 8.2, W. Lim et al. of the University of Michigan (Ann Arbor) presented on the possibilities for “Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic.”

nW Beyond Batteries

Session 5.4 covered “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems” by A. Shrivastava et al. of PsiKick (Charlottesville, VA). PsiKick’s silicon-proven ultra-low-power wireless sensing devices are based on over 10 years of development of Sub-Threshold (Sub-Vt) devices. They are claimed to operate at 1/100th to 1/1000th of the power budget of other low-power IC sensor platforms, allowing them to be powered without a battery from a variety of harvested energy sources. These SoCs include full sensor analog front-ends, programmable processing and memory, integrated power management, programmable hardware accelerators, and full RF (wireless) communication capabilities across multiple frequencies, all of which can be built with standard CMOS processes using standard EDA tools.

Extremely efficient energy harvesting was also shown by S. Stanzione et al. of Holst Centre/ imec/KU Leuven working with OMRON (Kizugawa, Japan) in session 20.8 “A 500nW Battery-less Integrated Electrostatic Energy Harvester Interface Based on a DC-DC Converter with 60V Maximum Input Voltage and Operating From 1μW Available Power, Including MPPT and Cold Start.” Such energy harvesting chips will power ubiquitous “smarts” embedded into the literal fabric of our lives. Smart clothes, smart cars, and smart houses will all augment our lives in the near future.

—E.K.

Directed Self Assembly Hot Topic at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

At this week’s SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly.

Extreme-ultraviolet lithography continues to command much attention, yet this conference is awash in papers about DSA, which dominates the “Alternative Lithographic Technologies” track of technical sessions. The two-day poster sessions feature 15 posters about DSA. Thursday’s conference sessions include three separate sessions devoted to “DSA Design for Manufacturability” and one for “DSA Modeling.”

With semiconductor industry anxiety rising at the prospect of quadruple-patterning and the slow yet steady progress of EUV technology, directed self-assembly is being hailed and recognized as a way to simplify chip manufacturing at the low end of the nanoscale era.

Before the conference got under way, imec reported on making significant progress in DSA technology, specifically reducing the defectivity associated with the process. Working with Tokyo Electron Ltd. (TEL) and Merck, which acquired AZ Electronic Materials last year, imec has come up with a DSA solution for a via patterning process that they say is compatible with the 7-nanometer process node. The partners are targeting the manufacture of DRAMs using 193nm immersion scanners.

“Over the past few years, we have realized a reduction of DSA defectivity by a factor 10 every six months,” imec’s An Steegen said in a statement. “Together, with Merck and Tokyo Electron, providing state-of-the-art DSA materials and processing equipment, we are looking ahead at two different promising DSA processes that will further improve defectivity values in the coming months. Our processes show the potential to achieve single-digit defectivity values in the near future without any technical roadblocks lying ahead.”

Kurt Ronse of imec describes DSA as utilizing two polymers to get molecules to array in lines or spaces. The issue has been to avoid the creation of holes that don’t fit the guided pattern, resulting in defects.

“All the big [chip] companies are having their internal developments on DSA,” Ronse said at SPIE. “All the memory companies are interested; Micron is in our program.”

While DSA is being implemented with 193 immersion equipment at the outset, there is the possibility of working with EUV scanners in the future, according to Ronse, and imec has an extensive EUV research and development program, he noted.

DSA started to emerge as a technology of note at the 2011 SPIE Advanced Lithography conference, Ronse said, which resulted in imec initiating its program in the field. There has been a significant amount of progress in the past two years, he added.

The momentum behind DSA R&D led to the establishment of the 1st International Symposium on DSA, scheduled for October 26-27, 2015, in Leuven, Belgium. Partnering with imec on the conference are CEA-Leti, EIDEC, and Sematech.

DSA – it’s one TLA you’ll hear a lot about in the years to come.

Solid State Watch: February 13-19, 2015

Friday, February 20th, 2015
YouTube Preview Image

5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

thumbnail

By Ed Korczynski, Sr. Technical Editor

#mce_temp_url#

At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Solid State Watch: December 12-19, 2014

Saturday, December 20th, 2014
YouTube Preview Image

Research Alert: December 16, 2015

Tuesday, December 16th, 2014

Stacking 2-dimensional materials may lower cost of semiconductor devices

A team of researchers led by North Carolina State University has found that  stacking materials that are only one atom thick can create semiconductor junctions that transfer charge efficiently, regardless of whether the crystalline structure of the materials is mismatched – lowering the manufacturing cost for a wide variety of semiconductor devices such as solar cells, lasers and LEDs.

“This work demonstrates that by stacking multiple two-dimensional (2-D) materials in random ways we can create semiconductor junctions that are as functional as those with perfect alignment” says Dr. Linyou Cao, senior author of a paper on the work and an assistant professor of materials science and engineering at NC State.

“This could make the manufacture of semiconductor devices an order of magnitude less expensive.”

Schematic illustration of monolayer MoS2 and WS2 stacked vertically. Image: Linyou Cao.

Schematic illustration of monolayer MoS2 and WS2 stacked vertically. Image: Linyou Cao.

For most semiconductor electronic or photonic devices to work, they need to have a junction, which is where two semiconductor materials are bound together. For example, in photonic devices like solar cells, lasers and LEDs, the junction is where photons are converted into electrons, or vice versa.

All semiconductor junctions rely on efficient charge transfer between materials, to ensure that current flows smoothly and that a minimum of energy is lost during the transfer. To do that in conventional semiconductor junctions, the crystalline structures of both materials need to match. However, that limits the materials that can be used, because you need to make sure the crystalline structures are compatible. And that limited number of material matches restricts the complexity and range of possible functions for semiconductor junctions.

“But we found that the crystalline structure doesn’t matter if you use atomically thin, 2-D materials,” Cao says. “We used molybdenum sulfide and tungsten sulfide for this experiment, but this is a fundamental discovery that we think applies to any 2-D semiconductor material. That means you can use any combination of two or more semiconductor materials, and you can stack them randomly but still get efficient charge transfer between the materials.”

Currently, creating semiconductor junctions means perfectly matching crystalline structures between materials – which requires expensive equipment, sophisticated processing methods and user expertise. This manufacturing cost is a major reason why semiconductor devices such as solar cells, lasers and LEDs remain very expensive. But stacking 2-D materials doesn’t require the crystalline structures to match.

“It’s as simple as stacking pieces of paper on top of each other – it doesn’t even matter if the edges of the paper line up,” Cao says.

Scientists measure speedy electrons in silicon

The entire semiconductor industry, not to mention Silicon Valley, is built on the propensity of electrons in silicon to get kicked out of their atomic shells and become free. These mobile electrons are routed and switched though transistors, carrying the digital information that characterizes our age.

An international team of physicists and chemists based at the University of California, Berkeley, has for the first time taken snapshots of this ephemeral event using attosecond pulses of soft x-ray light lasting only a few billionths of a billionth of a second.

While earlier femtosecond lasers were unable to resolve the jump from the valence shell of the silicon atom across the band-gap into the conduction electron region, the new experiments now show that this transition takes less than 450 attoseconds.

“Though this excitation step is too fast for traditional experiments, our novel technique allowed us to record individual snapshots that can be composed into a ‘movie’ revealing the timing sequence of the process,” explained Stephen Leone, UC Berkeley professor of chemistry and physics.

Leone, his UC Berkeley colleagues and collaborators from the Ludwig-Maximilians Universität in Munich, Germany, the University of Tsukuba, Japan, and the Molecular Foundry at the Department of Energy’s Lawrence Berkeley National Laboratory report their achievement in the Dec. 12 issue of the journal Science.

Century-old discovery observed

Leone notes that more than a century has elapsed since the discovery that light can make certain materials conductive. The first movie of this transition follows the excitation of electrons across the band-gap in silicon with the help of attosecond extreme ultraviolet (XUV) spectroscopy, developed in the Attosecond Physics Laboratory run by Leone and Daniel Neumark, UC Berkeley professor of chemistry.

In semiconducting materials, electrons are initially localized around the individual atoms forming the crystal and thus cannot move or contribute to electrical currents. When light hits these materials or a voltage is applied, some of the electrons absorb energy and get excited into mobile states in which the electrons can move through the material. The localized electrons take a “quantum jump” into the conduction band, tunneling through the barrier that normally keeps them bound to atoms.

These mobile electrons make the semiconductor material conductive so that an applied voltage results in a flowing current. This behavior allows engineers to make silicon switches, known as transistors, which have become the basis of all digital electronics.

The researchers used attosecond XUV spectroscopy like an attosecond stop watch to follow the electron’s transition. They exposed a silicon crystal to ultrashort flashes of visible light emitted by a laser source. The subsequent illumination with x-ray-pulses of only a few tens of attoseconds (10-18 seconds) in duration allowed the researchers to take snapshots of the evolution of the excitation process triggered by the laser pulses.

Unambiguous interpretation of the experimental data was facilitated by a series of supercomputer simulations carried out by researchers at the University of Tsukuba and the Molecular Foundry. The simulations modeled both the excitation process and the subsequent interaction of x-ray pulses with the silicon crystal.

Electron jump makes atoms rebound

The excitation of a semiconductor with light is traditionally conceived as a process involving two distinct events. First, the electrons absorb light and get excited. Afterwards, the lattice, composed of the individual atoms in the crystal, rearranges in response to this redistribution of electrons, turning part of the absorbed energy into heat carried by vibrational waves called phonons.

In analyzing their data, the team found clear indications that this hypothesis is true. They showed that initially, only the electrons react to the impinging light while the atomic lattice remains unaffected. Long after the excitation laser pulse has left the sample – some 60 femtoseconds later – they observed the onset of a collective movement of the atoms, that is, phonons. This is near the 64 femtosecond period of the fastest lattice vibrations.

Based on current theory, the researchers calculated that the lattice spacing rebounded about 6 picometers (10-12 meters) as a result of the electron jump, consistent with other estimates.

“These results represent a clean example of attosecond science applied to a complex and fundamentally important system,” Neumark said.

The unprecedented temporal resolution of this attosecond technology will allow scientists to resolve extremely brief electronic processes in solids that to date seemed too fast to be approached experimentally, says Martin Schultze, who was a guest researcher in Leone’s lab last year, visiting from the Ludwig-Maximilians Universität München. This poses new challenges to the theory of light-matter interactions, including the excitation step, its timescale and the interpretation of experimental x-ray spectra.

“But here is also an advantage,” Schultze added. “With our ultrashort excitation and probing pulses, the atoms in the crystal can be considered frozen during the interaction. That eases the theoretical treatment a lot.”

Holst Centre and imec develop thin-film hybrid oxide-organic microprocessor

Holst Centre, imec and their partner Evonik have realized a general-purpose 8-bit microprocessor, manufactured using complementary thin-film transistors (TFTs) processed at temperatures compatible with plastic foil substrates (250°C). The new “hybrid” technology integrates two types of semiconductors—metal-oxide for n-type TFTs (iXsenic, Evonik) and organic molecules for p-type TFTs—in a CMOS microprocessor circuit, operating at unprecedented for TFT technologies speed—clock frequency 2.1kHz. The breakthrough results were published online in Scientific Reports, an open access journal from the publisher of Nature.

Low temperature thin-film electronics are based on organic and metal-oxide semiconductors. They have the potential to be produced in a cost effective way using large-area manufacturing processes on plastic foils. Thin-film electronics are, therefore, attractive alternatives for silicon chips in simple IC applications, such as radio frequency identification (RFID) and near field communication (NFC) tags and sensors for smart food packaging, and in large-area electronic applications, such as flexible displays, sensor arrays and OLED lamps. Holst Centre’s (imec and TNO) research into thin-film electronics aims at developing a robust, foil-compatible, high performance technology platform, which is key to making these new applications become a reality.

The novel 8-bit microprocessor performs at a clock frequency of 2.1 kHz. It consists of two separate chips: a processor core chip and a general-purpose instruction generator (P2ROM). For the processor core chip, a complementary hybrid organic-oxide technology was used (p:n ratio 3:1). The n-type transistors are 250°C solution-processed metal-oxide TFTs with typically high charge carrier mobility (2 cm2/Vs). The p-type transistors are small molecule organic TFTs with mobility of up to 1 cm2/Vs. The complementary logic allows for a more complex and complete standard cell library, including additional buffering in the core and the implementation of a mirror adder in the critical path. These optimizations have resulted in a high maximum clock frequency of 2.1kHz. The general-purpose instruction generator or P2ROM is a one-time programmable ROM memory configured by means of inkjet printing, using a conductive silver ink. The chip is divided into a hybrid complementary part and a unipolar n-TFT part and is capable of operating at frequencies up to 650 Hz, at an operational voltage of Vdd=10V.

Interested companies can join Holst Centre’s R&D program on organic and oxide transistors, exploring and developing new technologies for producing thin-film transistors (TFTs) on plastic foils.

thin film microprocessor

NFC IGZO TFT for Game Cards

Thursday, November 20th, 2014

By Ed Korczynski, Senior Technical Editor, SemiMD

Thin-film transistors (TFT) made with indium-gallium-zinc-oxide (IGZO) can perform significantly better than TFTs made with low-temperature-poly-silicon (LTPS), and can be made ultra-thin and flexible for integration into a wide variety of devices. Researchers at the Holst Centre—an R&D incubator launched by the Belgian imec and the Dutch TNO in 2005—have been working on flexible TFTs for many years for many applications include flexible displays, intelligent food packaging, and paper identification (ID) documents. Now Holst Center is collaborating with Cartamundi NV, a world leader in production and sales of card and board games, to develop ultra-thin flexible near field communication (NFC) tags for game cards. The goal is an enhanced gaming experience that is interactive and intuitive.

Cartamundi creates specialized game cards such as these, and has been working on cards with embedded silicon NFC chips for many years. (Source: Cartamundi)

Cartamundi has been working on “iCards” that provide a connection between the physical products and the digital world for many years, and has recently claimed traction with games for the “connected generation”. By working with the Holst Centre to create IGZO TFTs on plastic, Cartamundi aims to lower overall costs while also creating both a thinner and a more robust NFC chip. Currently, Cartamundi NV embeds silicon-based NFC chips in their game cards, connecting traditional game play with electronic devices such as smartphones and tablets. The advanced IGZO TFT technology should improve and broaden the applicability of interactive technology for game cards, compared to the currently-used silicon based NFC chips.

Chris Van Doorslaer, chief executive officer of Cartamundi, said, “Cartamundi is committed to creating products that connect families and friends of every generation to enhance the valuable quality time they share during the day. With Holst Centre’s and imec’s thin-film and nano-electronics expertise, we’re connecting the physical with the digital which will enable lightweight smart devices with additional value and content for consumers.”

“Not only will Cartamundi be working on the NFC chip of the future, but it will also reinvent the industry’s standards in assembly process and the conversion into game cards,” says Steven Nietvelt, chief innovation and marketing officer at Cartamundi. “All of this is part of an ongoing process of technological innovation inside Cartamundi. I am glad our innovation engineers will collaborate with the strongest technological researchers and developers in the field at imec and Holst Centre. We are going to need all expertise on board. Because basically what we are creating is game-changing technology.”

The major challenges are two-fold:  low-temperature formation of the IGZO layer, and integration of the IGZO into a complex NFC circuit on plastic. Control of surface states and defect densities is always essential for the production of any working semiconductor device, and defects act as traps for electrons flowing through circuitry. Consequently, for TFT instead of bulk crystal devices the precise control of the many deposited thin-films is essential.

Holst Centre, imec and Cartamundi engineers will look into NFC circuit design and TFT processing options, and will investigate routes for up-scaling of Holst processes to run on large production presses. By keeping the IGZO TFT manufacturing costs low, the flexible chips are intended to be a critical part of Cartamundi’s larger strategy of developing game cards for the connected generation.

“Imec and Holst Centre aim to shape the future and our collaboration with Cartamundi will do so for the future of gaming technology and connected devices,” says Paul Heremans, Department Director Thin Film Electronics at imec and Technology Director at the Holst Centre. “Chip technology has penetrated society’s daily life right down to game cards. We are excited to work with Cartamundi to improve the personal experience that gaming delivers.”

While game cards may not seem as important as healthcare and communications, flexible NFC integration into cards could generate IGZO TFT production volumes that are game changing.

—E.K.

Solid State Watch: October 23-30, 2014

Friday, October 31st, 2014
YouTube Preview Image

Research Alert: June 24, 2014

Tuesday, June 24th, 2014

imec joins Graphene Flagship

To coincide with Graphene Week 2014, the Graphene Flagship announced that today one of the largest-ever European research initiatives is doubling in size. Sixty-six new partners are being invited to join the consortium following the results of a €9 million competitive call. While most partners are universities and research institutes, the share of companies, mainly SMEs, involved is increasing. This shows the growing interest of economic actors in graphene. The partnership now includes more than 140 organizations from 23 countries. It is fully set to take “wonder material” graphene and related layered materials from academic laboratories to everyday use.

“Imec aims to show that graphene can form the basis of practical optoelectronic devices, such as high speed modulators and detectors, for use in low power optical interconnects,” said Cedric Huyghebaert, team leader of imec’s graphene group. “During the past five years, we have built a strong knowledge in graphene device making, focused on the generic building blocks like contacting, doping and gate engineering, which are essential to progress in any graphene application. This knowledge, combined with our unique experience in integrating novel materials into CMOS-processes, and our optoelectronic silicon waveguide platform, makes imec a very suitable place to develop hybrid-silicon-graphene optoelectronic devices compatible with CMOS.”

Collecting light with artificial “moth eyes”

All over the world researchers are investigating solar cells which imitate plant photosynthesis, using sunlight and water to create synthetic fuels such as hydrogen. Empa researchers have developed such a photoelectrochemical cell, recreating a moth’s eye to drastically increase its light collecting efficiency. The cell is made of cheap raw materials – iron and tungsten oxide.

Rust – iron oxide – could revolutionize solar cell technology. This usually unwanted substance can be used to make photoelectrodes which split water and generate hydrogen.  Sunlight is thereby directly converted into valuable fuel rather than first being used to generate electricity. Unfortunately, as a raw material iron oxide has its limitations. Although it is unbelievably cheap and absorbs light in exactly the wavelength region where the sun emits the most energy, it conducts electricity very poorly and must therefore be used in the form of an extremely thin film in order for the water splitting technique to work. The disadvantage of this is that these thin-films absorb too little of the sunlight shining on the cell.

Empa researchers Florent Boudoire and Artur Braun have now succeeded in solving this problem. A special microstructure on the photoelectrode surface literally gathers in sunlight and does not let it out again. The basis for this innovative structure are tiny particles of tungsten oxide which, because of their saturated yellow colour, can also be used for photoelectrodes. The yellow microspheres are applied to an electrode and then covered with an extremely thin nanoscale layer of iron oxide. When external light falls on the particle it is internally reflected back and forth, till finally all the light is absorbed. All the entire energy in the beam is now available to use for splitting the water molecules.

In principle the newly conceived microstructure functions like the eye of a moth, explains Florent Boudoire. The eyes of these night active creatures need to collect as much light as possible to see in the dark, and also must reflect as little as possible to avoid detection and being eaten by their enemies. The microstructure of their eyes especially adapted to the appropriate wavelength of light. Empa’s photocells take advantage of the same effect.

In order to recreate artificial moth eyes from metal oxide microspheres, Florent Boudoire sprays a sheet of glass with a suspension of plastic particles, each of which contains at its center a drop of tungsten salt solution. The particles lie on the glass like a layer of marbles packed close to each other. The sheet is placed in an oven and heated, the plastic material burns away and each drop of salt solution is transformed into the required tungsten oxide microsphere. The next step is to spray the new structure with an iron salt solution and once again heat it in an oven.

A silicon replacement? USC Viterbi School of Engineering overcomes major issue in carbon nanotube tech

When it comes to electronics, silicon may one day have to share the spotlight. In a paper recently published in Nature Communications, researchers from the USC Viterbi School of Engineering describe how they have overcome a major issue in carbon nanotube technology by developing a flexible, energy-efficient hybrid circuit combining carbon nanotube thin film transistors with other thin film transistors. This hybrid could take the place of silicon as the traditional transistor material used in electronic chips, since carbon nanotubes are more transparent, flexible, and can be processed at a lower cost.

Electrical engineering professor Dr. Chongwu Zhou and USC Viterbi graduate students Haitian Chen, Yu Cao, and Jialu Zhang developed this energy-efficient circuit by integrating carbon nanotube (CNT) thin film transistors (TFT) with thin film transistors comprised of indium, gallium and zinc oxide (IGZO).

“I came up with this concept in January 2013,” said Dr. Chongwu Zhou, professor in USC Viterbi’s Ming Hsieh Department of Electrical Engineering. “Before then, we were working hard to try to turn carbon nanotubes into n-type transistors and then one day, the idea came to me. Instead of working so hard to force nanotubes to do something that they are not good for, why don’t we just find another material which would be ideal for n-type transistors—in this case, IGZO—so we can achieve complementary circuits?”

Carbon nanotubes are so small that they can only be viewed through a scanning electron microscope. This hybridization of carbon nanotube thin films and IGZO thin films was achieved by combining their types, p-type and n-type, respectively, to create circuits that can operate complimentarily, reducing power loss and increasing efficiency. The inclusion of IGZO thin film transistors was necessary to provide power efficiency to increase battery life. If only carbon nanotubes had been used, then the circuits would not be power-efficient. By combining the two materials, their strengths have been joined and their weaknesses hidden.

Zhou likened the coupling of carbon nanotube TFTs and IGZO TFTs to the Chinese philosophy of yin and yang.

“It’s like a perfect marriage,” said Zhou. “We are very excited about this idea of hybrid integration and we believe there is a lot of potential for it.”

Next Page »