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Posts Tagged ‘IEDM’

The Week in Review: May 30, 2014

Friday, May 30th, 2014

Applied Materials, Inc. introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package, a packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

The Semiconductor Industry Association announced that global semiconductor industry leaders reached an agreement at the 18th annual meeting of the World Semiconductor Council (WSC) last week on a series of policy proposals to strengthen the industry through international cooperation.

The 60th annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

SEMI announced that SEMICON West 2014 will feature Bob Metcalfe, professor at the University of Texas at Austin, as the Silicon Innovation Forum’s keynote speaker.

Blog review January 21, 2014

Tuesday, January 21st, 2014

Zvi Or-Bach, President and CEO of MonolithIC 3D weighs in on the battle of Intel vs TSMC in the foundry space, after conflicting stories appeared. One said that Intel had a huge pricing advantage over TSMC, and a second story noted TSMC’s boast that it was “far superior” to Intel and Samsung as a partner fab.

Adele Hars looks back at 2013 from the SOI perspective. In this “Part 2” post, she focuses on developments that last year brought in the areas of RF-SOI and SOI-FinFETs. Part 1 focused on the general SOI picture. Stayed tuned for a look at 2014.

Phil Garrou reports on some of the key 3DIC presentations from the IEEE Internal Electron Devices Meeting (IEDM), held in December in Washington, D.C. , focusing on papers from Micron, TSMC, Tohoku Univ., NC State and ASET. He said that Micron’s Naga Chandrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking, noting that he does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

Solid State Watch: Dec. 6-12, 2013

Friday, December 13th, 2013
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The Week in Review: Dec. 13, 2013

Friday, December 13th, 2013

A new type of transistor that could make possible fast and low-power computing devices for energy-constrained applications such as smart sensor networks, implantable medical electronics and ultra-mobile computing is feasible, according to Penn State researchers. Called a near broken-gap tunnel field effect transistor (TFET), the new device uses the quantum mechanical tunneling of electrons through an ultrathin energy barrier to provide high current at low voltage. Penn State, the National Institute of Standards and Technology and IQE, a specialty wafer manufacturer, jointly presented their findings at the International Electron Devices Meeting in Washington, D.C. The IEDM meeting includes representatives from all of the major chip companies and is the recognized forum for reporting breakthroughs in semiconductor and electronic technologies.

Based on a honeycomb network of carbon atoms, graphene could generate a type of electronic surface wave that would allow antennas just one micron long and 10 to 100nm wide to do the work of much larger antennas. While operating graphene nano-antennas have yet to be demonstrated, the researchers say their modeling and simulations show that nano-networks using the new approach are feasible with the alternative material.“We are exploiting the peculiar propagation of electrons in graphene to make a very small antenna that can radiate at much lower frequencies than classical metallic antennas of the same size,” said Ian Akyildiz, a Ken Byers Chair professor in Telecommunications in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. “We believe that this is just the beginning of a new networking and communications paradigm based on the use of graphene.”

This week, industry leaders and experts have gathered in Washington D.C. at the 59th annual IEEE International Electron Device Meeting (IEDM) conference. The IEDM presents more leading work in more areas of the field than any other technical conference, encompassing silicon and non-silicon device technology, molecular electronics, nanotechnology, optoelectronics, MEM/NEMS, energy-related devices and bioelectronics. The 59th annual IEDM conference includes a strong overall emphasis on circuit-device interaction, advanced semiconductor manufacturing, and biomedical devices. Solid State Technology‘s Pete Singer is on site all week, and we will be getting insight from bloggers and industry partners. Browse our slideshow of highlights from abstracts being presented this week.

The penetration of gallium nitride-on-silicon (GaN-on-Si) wafers into the light-emitting diode (LED) market is forecast to increase at a compound annual growth rate (CAGR) of 69 percent from 2013 to 2020, by which time they will account for 40 percent of all GaN LEDs manufactured, according to a new report from IHS Inc. In 2013, 95 percent of GaN LEDs will be manufactured on sapphire wafers, while only 1 percent will be manufactured on silicon wafers. The growth in the manufacturing of GaN-on-Si LEDs between 2013 and 2020 will take market share from both sapphire and silicon carbide wafers.

Soitec announced this week that the European Commission has approved the financing for the Guépard program, coordinated by Soitec. This program was launched to develop a new generation of highly efficient photovoltaic cells. It was selected in April 2012 by the “Invest for the Future” (Investissements d’Avenir) program, which is managed by the French environment and energy management agency (ADEME – Agence de l’Environnement et de la Maîtrise de l’Energie). As well as Soitec, Guépard brings together the French Alternative Energies and Atomic Energy Commission (CEA), and an SME, InPACT. For all these partners together it represents total investment of €68.9 million over five years. The European Commission’s notification to the French government of its funding approval will give Soitec access to €21.3 million in government support.

Invensas Corporation announced that it is partnering with Tezzaron Semiconductor Corp. a pioneer and producer of 3D Integrated Circuit (3D-IC) semiconductor devices, in order to build a wide range of 3D-IC customer products. Robert Patti, CTO of Tezzaron said: “We can produce complete high-quality 2.5D and 3D silicon devices, but the final packaging flows are lacking. Invensas’ 3D-IC packaging expertise and existing pilot assembly line capability will enable us to ramp our unique products into full production. The Invensas combination of technology development and low volume manufacturing capabilities are unlike anything else available.”

Blog Review: November 25, 2013

Monday, November 25th, 2013

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs about a recent announcement by Intel CEO Brian Krzanich on company expansion focused on a foundry plan. Or-Bach said that if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of the other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

Vivek Bakshi, EUV Litho, Inc. reports on work presented at the 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland), including data on the readiness of 50 W EUV sources to support EUVL scanners. At the meeting, keynoter Vadim Banine of ASML said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field. ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

At the GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Phil Garrou reports on the workshop, including presentations from Ron Huemoeller of Amkor and David McCann of GLOBALFOUNDRIES.

Pete Singer provides a preview of a special focus session at the upcoming IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013. The session covers many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Dr. Lianfeng Yang of ProPlus Design Solutions, Inc., blogs that these days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

The Week in Review: Oct. 16

Wednesday, October 16th, 2013

NY’s Marcy Nanocenter, the largest remaining shovel-ready, greenfield site in New York State’s Tech Valley near Utica, is another step closer to the goal of attracting major semiconductor manufacturing companies. The computer chip packaging consortium will work inside the Quad C Complex now under construction on the SUNYIT campus, which is due to open in late 2014.

SEMI believes that the semiconductor materials market will trend with the device market, resulting in an increase of one percent this year and a seven percent increase in 2014, resulting in a materials market approaching $50 billion in 2014.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 9-11 in Washington, D.C., IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Dow Electronic Materials announced availability of its SOLDERON BP TS 6000 Tin-Silver Plating Chemistry for use in lead-free solder bump plating applications.

Semiconductor capital spending has increased significantly among pure-play foundries as more IDMs shift to a fabless/fab-lite business model and as new foundry participants intensify competition among the old guard.


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