By Mark LaPedus
After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility.

The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a little less than five years to develop the production tools for 450mm fabs, which are expected to cost a whopping $10 billion or more. Based in Albany, N.Y., the G450C has five members—GlobalFoundries, Intel, IBM, Samsung and TSMC.

But between now and 2018, there is a staggering amount of work to be done. Based on the current progress for select equipment, fab technologies and standards, the path towards 450mm will be a bumpy road and it’s unclear if the industry can meet the 2018 target.

The most obvious problem is lithography. For example, ASML Holding is not expected to deliver a production-worthy, 450mm version of its extreme ultraviolet (EUV) lithography scanner until 2018. Other challenges include lithographic cost-of-ownership and throughput.

On the wafer-processing front, Applied, Lam, TEL and others are moving full speed ahead in 450mm. TEL also is proposing an “open platform” standard—a move that has received a lukewarm response. Meanwhile, there is some movement in metrology, as a new consortium has recently been formed to address the challenges in 450mm.

And the industry is still debating over various 450mm fab standards, such as aisle space and ceiling height. There is even a debate over the type of cranes needed to install 450mm tools. Other standards, such as gas interface boxes, cooling water manifolds, and hookups for power, are also in the works.

That’s just the tip of the iceberg. The goal for the G450C is not only to help develop these technologies, but it also has the arduous task of getting the various players to synchronize on the roadmap. “It’s going to require a collaborative and concerted effort to introduce (450mm technology) in an efficient manner,” said Steve Johnston, director of external programs and technology strategy in the Technology Manufacturing Engineering Group at Intel, at a recent SEMI event. “All of this requires flawless and synchronized execution across the industry and at multiple levels.”

Avoiding past mistakes
Indeed, the industry hopes to avoid past mistakes. In the mid-1990s, the IC industry wanted to make the shift from 200mm to 300mm fabs. The equipment industry had the 300mm tools ready in the late 1990s, but chipmakers pushed out their 300mm fabs amid an IC downturn. Equipment vendors ended up holding the bag and lost a fortune. Shortly thereafter, chipmakers began to ramp up their 300mm fabs, but the events left a bad taste in vendors’ mouths.

Recently, Intel, Samsung and TSMC have been pushing for 450mm fabs. The argument is that the industry needs to make a wafer transition every 15 years to stay on Moore’s Law. Moving to 450mm wafers will give chipmakers a 2.25x boost in wafer area and a 30% cost reduction, according to chipmakers.

For some time, however, fab tool vendors were lukewarm about 450mm. There are only a handful of customers who would buy 450mm tools, and it’s unclear who will foot the R&D bill for the technology.

More recently, 450mm has become a reality. Intel and TSMC have outlined plans to build 450mm fabs. And in 2011, the G450C was established at the College of Nanoscale Science and Engineering’s NanoTech Complex. The G450C recently opened a cleanroom. Its roadmap also calls for 450mm pilot lines in 2015 and 2016, with high-volume production targeted for 2018.

“Synchronization and collaboration are very important to avoid the same type of issues we ran into in the late 1990s with the transition to 300mm,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials.

There are other issues, namely supply-chain readiness, return-on-investment and R&D funding. “The (R&D funding) issue requires a very different business model,” Hasserjian said. “That has not been completely resolved. We have the consortium activities, which have provided some level of funding.”

Fab tool challenges
The industry has moved to fund at least one technology, namely lithography. Intel, Samsung and TSMC recently invested in ASML, in an effort to accelerate ASML’s efforts in 450mm and EUV. And with separate funding from Intel, Nikon is developing a 193nm immersion scanner for 450mm.

ASML itself has initiated 450mm programs on two separate platforms and four wavelengths, including EUV. The goal is to deliver “early version tools” in 2015 to 2016, with 450mm production systems due out by 2018, said Jim Koonmen, general manager of Brion Technologies, a division of ASML.

The development of a 450mm EUV scanner is expected to be a herculean effort. Today, ASML is struggling to deliver 300mm EUV tools amid delays with the power sources. Cost is also an issue, as ASML’s pre-production EUV scanners cost $100 million or more per unit today.

Throughput is also an issue. The throughput for a 450mm scanner in general is projected to be only about one-half of a 300mm tool, Koonmen said. A 300mm tool has a throughput of about 250 wafers per hour (wph), while a 450mm system can run 100-125 wph at 1.1x the cost, he said.

“If you look at the entire semiconductor process, there are steps that do get a lot of leverage from larger wafer sizes and can realize cost reduction,” he said. “Unfortunately, with lithography, there simply isn’t that much of a benefit in going to larger wafer sizes. We are scanning as fast as we can. The number of fields is going to increase when we go to larger wafers, but that just means your throughput for each 450mm wafer is going to go down. So you’ve got double the number of fields, but you are going at half the throughput. That in itself is not easy to do. In order to handle a 450mm wafer, you need to have larger stages with larger masks, and that creates a whole bunch of issues for us.”

Meanwhile, amid the problems with EUV, the industry is hedging its bets by developing 193nm immersion scanners for 450mm. Optical is a proven technology, but the solution is expensive. At 10nm or 7nm, chipmakers must also use expensive multiple patterning schemes.

Delivery schedules for 193nm immersion are more certain, however. “450mm is expected to be in production by 2018,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “We will ship development tools earlier than that.” By 2015, Nikon plans to ship “early learning tools” based on 193nm immersion for 450mm, Zarringhalam said. Nikon has already garnered “multiple orders” for the systems, he added.

On the wafer processing side, there are also some technical and cost challenges. “Prices could rise 30% to 50% for 450mm tools, as they did when the wafer size shifted to 300mm from 200mm,” said analyst David Motozo Rubenstein, who is also the author of a blog entitled “Chips and Dips.”

Applied, Lam, TEL and others are developing standalone 450mm tools. TEL also is proposing the idea of having an “open and modular platform” for 450mm. This would enable fab tool vendors to develop various plug-and-play process modules for the open platform, thereby reducing costs and development times. TEL and its rivals could develop modules for the platform. “The open platform is a concept for the 450mm high-volume manufacturing era,” said Aki Sekiguchi, vice president and general manager for SPE marketing at TEL.

The open platform could benefit smaller companies that don’t have the resources to develop standalone tools. But larger companies are not eager to endorse an open platform, because it will give its rivals a competitive edge. “We are looking at it,” said Applied’s Hasserjian. “We are not doing what TEL is doing and advocating a modular platform.”

Metrology challenges

Another challenge is the development of 450mm metrology gear. “There are not many companies that can invest six years in advance,” said Menachem Shoval, chairman of Metro450, an Israeli-based consortium that is developing 450mm metrology technology. “Even without going 450mm, there are huge challenges for metrology in terms of going down from 22nm to 14nm to 10nm to 7nm.”

This is especially true when moving from today’s planar devices to finFETs at 22nm and beyond. “Going to 3D has created numerous challenges for us,” said John Allgair, senior member of the technical staff at GlobalFoundries. “We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.”

One solution to the problem is to collaborate through a consortium, Metro450′s Shoval said. Last year, for example, the Metro450 consortium was formed by the following companies—Applied Materials, Nova, Jordan Valley, Nanomotion and Intel. The group also consists of four universities in Israel, with some 60% of the funding coming from the Israeli government.

“Each company develops its own technology,” Shoval said. “They are competing with each other. But we can collaborate on those parts which are common. We will work on platforms, but not on detection.”

One of the goals for the Metro450 group is to meet the design rule targets by 2017. It is also devising technologies that are 2.5x faster than 300mm, thereby meeting the cost requirements for 450mm. To reach its goals, the group is working on five specific technologies: wafer handling; sampling optimization; wafer damage and contamination; calibration; and data processing.

“We plan to complete our work in three years,” Shoval said. “So companies will still have about three years to complete the development of their high-volume manufacturing tools.”

By David Lammers
Two key areas of the semiconductor industry’s future—the 450mm wafer transition and EUV lithography—are the focus of the new NFX (NanoFab Xtension) building now under construction at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany.

Alain Kaloyeros

The cooperative research effort at CNSE and the Global 450 Consortium (G450C) could springboard New York into the 450mm fab era at some point, said Alain Kaloyeros, senior vice president and CEO of CNSE. The consortium, announced by New York Governor Andrew Cuomo in September 2011, includes IBM, Intel, GlobalFoundries, TSMC and Samsung, as well as CNSE.

Kaloyeros, in an interview at the NanoFab complex, said, “Now that there is a consensus that 450 is happening, our role is to create the environment, enable the resource innovation and the manufacturing innovation for the transition. The NFX facility is going to be heavily focused on tool development and demonstration, but at the end of the day, all this is going to be driven by innovation.”

With the 14nm node as the potential baseline at the NFX facility, half of the building is dedicated to the work of the G450C consortium, with the remainder for EUV-related programs which are part of an extension of the Center for Semiconductor Research (CSR), led by CNSE and IBM, with a focus on 14nm and beyond technologies.

The currently operating NanoFab North (NFN) building has an initial set of six 450mm tools within 4,000 to 5,000 square feet of cleanroom space. The early work has focused on automation development. To get ready for the tool and process development phases, the consortium is building a bank of 450 wafers to be shared by the members. The consortium has ordered 6,000 450mm wafers, at a per wafer price of $4,500, he said.

The new building will have 280,000 square feet of total space in a four-level building, with a total of 60,000 square feet of clean space, of which 45,000 square feet of cleanroom is on a waffle slab. The waffle slab in the NFX building is a reinforced 4-ft.-thick concrete structure capable of supporting 750 lbs. per square foot to obtain the load rating and vibration specification needed for the EUV NSE:3300 tool.

Interior view of the NFX clean room at CNSE. (Source: CNSE)

The 45,000 square foot cleanroom will have a single separation wall with the G450 space on one side and the CSR (Center for Semiconductor Research) EUV Center of Competency in the other. In addition, there is a quiet SEM/TEM room in the subfab on a 6-foot-thick slab, said Jonathan Holder, vice president for facilities and infrastructure at CNSE.

Construction of the building is expected to wrap up late this year; the schedule has been gated by delays to the EUV lithography source power modules. Tool hook-up work needed for the ASML NXE:3300 scanner will begin in October of this year with tool components arriving during the fourth quarter and into early next year. Installation of the dedicated gantry crane above the scanner is scheduled for July of this year.

The NFX building, at top center, is connected to CNSE Nanofab North.

EUV and 450

Kaloyeros said the G450C members are “working on a lithography solution, but we don’t know if it is going to be an early EUV tool or immersion 193 or imprint. We are in the process of having those discussions with the consortium members, and I can’t say now if they are contemplating one option or multiple options. But all of us understand that having a litho program is critical to the G450C.”

Despite the delays, Kaloyeros said the companies working at CNSE still see EUV as “very much a viable solution. They haven’t given up on it. A different question is: What litho technology is needed for a 450 fab? That could be EUV, or it could be by immersion litho being pushed. It could be immersion—who knows? The point is that by the time the 450 fabs are ready to be built if they don’t have EUV it is not going to kill construction of the 450mm fabs.”

A 450mm Fab in New York?

A decade ago Kaloyeros was critical of Intel for not doing much of its consortia R&D at CNSE. Now he is singing a different tune, happy that Intel is taking a leading role in the G450C effort based in Albany. “Intel was not a big player here. Now they are a big player. That is a big breakthrough for CNSE.”

Asked if Intel or other G450C member companies might build a fab in New York, Kaloyeros replied that “there is a very strong hope that when they are ready to build a 450 millimeter fab that they will consider New York. Governor Cuomo has said that New York really is open for business, and he personally has been leading this.”

By David Lammers

The late September news of the G450C collaborative effort swept over the Atlantic like a tsunami, starting in Albany, N.Y., and washing up on the Semicon Europa conference, where speakers questioned how European suppliers would be linked in to the Albany-based effort. With a vibrant equipment and materials industry, Europe seeks to play an active role in a transition being managed far from its shores. The issue is complicated by the lack of a single Europe-based IC vendor ready to embrace the larger wafers.

The Global 450 Consortium based in Albany, N.Y. (G450C) plans to have 50 tool types installed at its pilot line in the next few years, said Tom Jefferson, in charge of the ISMI 450 program which is being rolled into the G450C consortium. The G450C pilot line will swing into action in the second half of 2013 and 2014, with demonstrations targeted at “the 1X node.”

(Source: ISMI presentation at 2011 Semicon Europa)

At Semicon Europa, held in mid-October in Dresden, Germany, Jefferson said G450C  will provide “centrally aligned requirements” to suppliers, including a “well-defined method of testing tools and data sharing with the device makers which avoids duplication of data generation.”  (The following week, during ISMI Manufacturing Week in Austin, Texas, the 450mm equipment testing parameters were described at an all-day seminar.) The initial patterning will be performed by an EV Group 770 nanoimprint tool, now being modified at the EVG engineering center in Austria to handle the larger wafers.

Tom Jefferson

While stopping short of saying suppliers would be shut out from purchase orders if they fail to participate in the G450C effort, he said those vendors would receive “a lower priority.” With Jefferson holding out several carrots to the equipment and materials providers to participate, the equipment makers are still looking for assurances on timing as well as financial support.

Asked whether EUV would be a gating factor for 450mm development, Kirk Hasserjian, vice president of strategic programs at Applied Materials, said a successful transition to 450mm “has more to do with the sharing of risk” than whether 450-capable EUV tools are available. “The seeds are in place in New York for better collaboration. Hopefully, there will be some sort of cost sharing and risk sharing going forward.”

He said wafer fab equipment sales are “whiplashed by GDP fluctuations,” and called for “a synchronized transition to 450mm in terms of high-volume manufacturing,” and “a clear, published strategy by the litho suppliers.”

The 450mm progress review sessions at Semicon Europa, organized by Lothar Pfitzner of the Fraunhofer IISB, included 21 presentations over two full days. Jefferson kicked things off by telling the largely European audience that G450C welcomes participation by the European equipment and materials (E&M) industry, which accounts for a surprising 20-25 percent of the worldwide market (led by ASML). “I want to encourage equipment suppliers to participate,” Jefferson told the Semicon Europa audience, adding that they would have access to patterned and unpatterned wafers, shared metrology tools, shipping containers called MACs, and access to the engineers assigned to the G450C by the five device makers – IBM, Intel, GlobalFoundries, Samsung, and TSMC. For European equipment makers not able to ship a tool to Albany, Jefferson said that “participation does not necessarily mean that a tool must be on-site. We need to work out the details” on remote links.

Georg Kelm

Georg Kelm, head of the nanoelectronics sector at the European Commission, summed up the bifurcated European attitude to the 450mm transition: “The (European) materials suppliers are ready to join. The equipment suppliers are equally active, with a proactive attitude. But the IC manufacturers have made no commitments – not yet.”

While much of the EU’s research has gone towards the “More Than Moore” sectors of MEMS, LEDs, photonics, and related subjects, Kelm warned that a successful More Than Moore strategy depends on leading-edge fabs being started for “More Moore” device scaling.

“It would be a mistake to separate More Than Moore and More Moore,” Kelm said, adding that More Than Moore “will not provide a long holiday” for the European semiconductor industry. Much of the effort to link devices with 3D interconnects will end up being done on 450mm wafers, for example.

Kelm said that tool vendors at some point will stop developing new technologies on 300mm platforms. “The 8nm node likely will be for 450mm equipment the equivalent of 65nm for the 300mm equipment. That is when new technologies were 300mm only,” he said. And he predicted that all “post CMOS” manufacturing will be on 450mm tools.

“In 15 to 20 years even the mature technologies will be on 450mm,” Kelm said, adding that “it is possible that some product categories may never be produced in 450mm; however, provided volumes are there, even MEMS, specialized technologies and power could be made on 450mm wafers.”

However, public funding from the European Union cannot be divided long between 300mm and 450mm platforms – there is not sufficient money for that. And he noted that the European equipment and materials vendors – eager to remain competitive with 450mm offerings – employ more people in Europe than the European device makers, including STMicroelectronics, Infineon, and NXP Semiconductors.

“One of the three indigenous IC vendors definitely has to go to 450. The other possibility is that one of the inward investors – Intel or GlobalFoundries — will go to 450 millimeters,” Kelm said.

Hans Lebon, Imec’s vice president in charge of fab and process step development, said “all innovation will move to 450mm, though not in the next two nodes. Ten nanometer technology and beyond will largely be developed on 450, and 300mm will no longer be cost effective.”

Imec will develop the main 450mm process modules at an expanded cleanroom in Leuven, Belgium. Epitaxial deposition, atomic layer deposition, front-end-of-the line critical cleaning, lithography, and dry etching steps all will be developed on 450mm equipment at Imec, Lebon said. “We have a tremendous amount of work to do in a reasonable time frame to keep costs under control,” he told the Semicon Europa audience.

Michel Brillouet, senior advisor at CEA-Leti, predicted that by the 8nm node that some logic vendors will adopt a heterogeneous CMOS technology, in which a III-V material is used in the NFET channel and perhaps germanium in the PFET channel. By the 8nm node the MPU makers, for example, will not be using the same toolset employed today, he said.

Predicting that 450mm would reach volumes in 2018, Brillouet said it is likely that the semiconductor industry will be spread out over various technology generations then. One possible scenario, he said, is that MPU makers would be at the 8nm generation, foundries at 14nm, flash at 11nm and DRAM at 16nm. Leti will continue to work closely with Soitec, Mapper, and other vendors, cooperating closely with Imec on 450mm modules not available at the Leti research facilities in Grenoble.

Heinz Kundert, president of SEMI Europe, said about 40 European suppliers have participated in the EU-based EEMI 450 Initiative. A March 2011 SEMI Europe survey showed that half of the equipment and materials respondents said 450mm was “very important to my company.”

By Mark Lapedus and David Lammers

The State of New York is hoping that the Global 450 Consortium (G450C) announced last week will result in 450mm fabs being built in New York and more equipment purchased from vendors operating in the Empire State.

A 2010 “450.doc” proposal that circulated among New York’s politicians was designed to gain their support for the G450C effort, including additional state funding for the SUNY University of Albany College of Nanoscale Science and Engineering (CNSE), where the G450 consortium will build a 450mm demonstration line expected to go into operation in early 2013.

The 2010 proposal outlines a second phase, to be negotiated in 2013, in which the five members of the consortium – IBM, Intel, GlobalFoundries, TSMC and Samsung – would be encouraged to build a 450mm fab in New York at some point in the future.

“The Phase II agreement will contain provisions that if any Consortium member determines, directly or indirectly, to build a 450 plant anywhere in the world that at least one such 450 facility would be built at an appropriate site in NYS (New York State) reasonably acceptable to NYS and such consortium partner,” according to the proposal.

“The commitment of the consortium partners in Phase II would be subject to NYS continued investment but the consortium agrees that in light of the cluster value provided by NYS that the amount of such support as a percentage of the total project cost would be lower than that provided by NYS in prior transactions,’’ according to the document.

It is not known how much of the language in the “450.doc” proposal ended up in the final agreement. CNSE, Sematech, and the five chip makers will form the board of directors for the G450C effort.

The proposed Phase II part of the plan also includes a “Made in New York” initiative, which would call for the procurement of fab tools exclusively from “manufacturers located’’ in New York and “existing New York State vendors,” according to the proposal. Phase II would result in additional funding for the 450mm consortium and “the creation of a significant number of additional jobs’’ in New York, according to the document, a copy of which was obtained by SemiMD.

Of the five members — Intel, IBM, GlobalFoundries, TSMC and Samsung – only Intel and TSMC have separately announced “450mm-ready” fabs in various other locations. Intel has announced two 450mm-ready plants, including D1X in Oregon and Fab 42 in Arizona. TSMC plans to build a 450mm pilot line in Fab 12 in Hsinchu, Taiwan by 2013 or 2014. By 2015 or 2016 TSMC hopes to ramp a 450-mm production plant: Fab 15 in Taichung, Taiwan. The foundry’s management has recently expressed doubts that it can stay on that schedule.

IBM, GlobalFoundries and Samsung have not disclosed any 450mm fab plans.

Bob Bruck, vice president of Intel’s technology and manufacturing group, said Intel is not under any obligation to build a 450mm fab in New York or anywhere else. He praised New York’s effort to develop a chip manufacturing infrastructure in the state, including the CNSE Albany Nanotech Center, mentioning the names of the governor and others as active supporters of New York’s technology infrastructure.

However, Bruck said that Intel would follow its normal site selection process for any decision on a new fab site, 450mm or otherwise. “Whenever we plan to build a new fab we look on a global basis, and have a well-defined site selection process. That process has not changed” following announcement of the 450mm consortium, he said.

The five chip makers are expected to contribute at least $75 million each in the project over the next five years, according to the Business Review news site based in New York. Bruck called that level of investment a “starting point.”

In addition, IBM plans to invest $3.6 billion in its ongoing transistor development alliance and related packaging R&D, which will be directed to Albany Nanotech and other state facilities, according to a report from Albany-based Times Tribune newspaper. Much of that investment is already committed by the companies to support the ongoing efforts by IBM, GlobalFoundries, and Samsung Electronics (not including Intel or TSMC) to develop 22nm and 14nm technology, independent of the work on the 450mm wafer transition.

CSNE in Albany, N.Y. will serve as the headquarters for the 450mm consortium, and a spokesman for CSNE said each consortium member will provide employees and assignees to the group.

Fab construction firm M+W has been building a $300 million research center at the CNSE at the University at Albany, which will be the centerpiece of the Global 450 Consortium, according to the CNSE spokesman. That center, called the NanoFab West or NanoFab X building, is designed to handle 450-mm equipment, including the heavy EUV lithography tools.

Some $250 million for the center will come from the Empire State Development Corp., $100 million from the New York Power Authority, and $50 million from capital projects fund, according to the Times Tribune, citing Josh Vlasto, a spokesman for Gov. Andrew Cuomo, as its source.

Alain Kaloyeros

According to the report, CNSE President Alain Kaloyeros said the center would install between $2 billion and $2.5 billion worth of fab tools. The first tools will be installed by September 2012. The facility will be completed by the first quarter of 2013, according to the report, citing  Kaloyeros as its source.

By David Lammers and Mark LaPedus

The Global 450 Consortium, or G450C, will provide equipment suppliers with access to a test wafer bank on a “first-come, first-served basis,” depending on their in-kind investments and other contributions to the consortium, said Bob Bruck, vice president of Intel’s technology and manufacturing group (TMG).

The G450C announced this week includes five IC manufacturers – with IBM and GlobalFoundries joining the original “IST” members, Intel, Samsung, and TSMC. Those companies, along with Sematech and the SUNY-Albany College of Nanoscale Science and Engineering (CNSE), will sit on a board of directors that will govern the consortium.

The G450C demonstration line in Albany is targeted for 14nm design rules early 2013 with imprint technology used for test wafer patterning of over the first year. The first 450mm 193i optical litho tool for Albany is expected to arrive in late 2013, an Intel spokesman said. After that, each of the consortium’s members can determine their own schedule for 450mm development fabs, with 2015 remaining as the group’s overall target. Intel has not decided which node capability it will want for its own development line, because that will depend upon manufacturability progress of the 450  tool set, the Intel spokesman added.

Bob Bruck

While Bruck said early analyst estimates of a $5B total cost of the 450mm test wafers needed for the transition were too high, he agreed that test wafer costs will be a “substantial portion” of the cost of the 450mm wafer development program. “That in itself is an attractive element to pull the collaborators (suppliers) in. To the degree that they participate in the consortium, they will have access to the output, to the test wafers themselves. It will be first come, first served, and the allocation schemes have to be tied to the funding of it.”

CNSE is building a new fab for the G450C effort, named Nanofab West or Nanofab X, which looms over the highway that cuts through the Albany Nanotech campus. Construction is expected to be completed next year.

Bruck said while $75 million is roughly accurate for the five IC companies contribution “as a starting point,” the overall budget will go up over time, bolstered by investments from the suppliers and a $200 million contribution over five years from the Empire State Development organization, among other sources.

Bruck said the supplier contributions “are really going to evolve and be substantial as people see the structure take place.” Suppliers will support G450C because they will be able to interface with five customers in the same place, all seeking to develop standards and product requirements. That will provide the entire industry – including the tool suppliers – with a “huge amount of cost savings.”

The 300mm wafer transition did not go well because there were 17 different semiconductor manufacturing companies interfacing with the suppliers. While common 450mm development work will be done in Albany, tool suppliers with their own development centers will continue to do their own work at home. Bruck said he envisions Intel, for example, running a “virtual fab” that would involve Albany. Intel could run test 450mm wafers through the line at Albany, then air freight those wafers to a supplier which would run them through its proprietary tool, and then back to Albany for completion and testing.

“Suppliers can say, ‘I can do this work on my own and have five customers asking for five different things. Or I can do some of this work in one location with five customers working with me on requirements, standards and product definitions. That is a big change from previous wafer transitions, and substantially increases the value of investment in this facility, in lieu of doing investments elsewhere,” he said.

The ISMI 450 program has refined a request for proposal (RFP) process that will transfer over to the G450C effort, which will take over the ISMI 450 program. Bruck lauded the assignees to the ISMI 450 program and said the five member companies will add more “high quality” people to G450C going forward.

The G450C partners have engaged in “pretty substantial dialogue” with equipment and wafer suppliers, and Bruck said he expects a “very high degree of participation in their own centers and in the development line in Albany. Some suppliers may want to do some things in front of five customers, while for other things they may prefer to do those in a more proprietary manner in their own facility.”

At a Semicon West panel discussion on the 450mm wafer transition, tool suppliers said they were vexed by the mixed messages coming from the IST companies, with different schedules and technology targets for the transition.

Bruck said the G450C is targeting 14nm capability for the Albany 2013 development line tools. Compared with the 300mm transition, he said the 450mm transition will be “much more tightly coordinated,” both because of the consortial approach to development and because of industry consolidation among the IC manufacturers.

“From a process technology node point of view, we think the suppliers will be capable of dealing with both the wafer size and the node progression in this time frame. As for when the individual companies build their own fabs, it is like the question of when EUV comes in. It depends on when it is manufacturable. We had a false start on 300mm partly because the 17 announced customers were not aligned,” he said.

Bruck added that “lithography is its own animal. We prefer to have EUV healthy before we go to 450. Either way, there will also be a need for 193i at 450, and we need EUV at 300. As we continue to gain efficiencies in our 300mm fabs, that lays the groundwork for 450. We will figure out how many layers use EUV and immersion (on 300mm wafers), and we have got to do a lot of this work in parallel” with the 450mm transition, he said.

Bruck said he will moderate a panel of suppliers that will discuss the supplier’s role in the 450mm wafer transition at the SEMI International Trade Partners Conference in Hawaii, scheduled for Nov. 3-5. While some have expected that the device makers would set up a common pool of money for equipment development, Bruck said, “It is not about who we are going to hand money out to. We can’t just throw money at the problem,” he said.

By David Lammers and Mark LaPedus

In a major shift, the Sematech ISMI 450 program will become part of the Global 450 Consortium announced yesterday by New York governor Andrew Cuomo, Sematech officials said Wednesday (Sept. 29).

(Source: Sematech ISMI 450 program presentation)

Since 2006, the Sematech ISMI organization has been in charge of the early stages of the 450mm transition, including developing standards for the wafers, automation, and getting the ball rolling for development of the 450mm processing tools. Last year, the entire ISMI organization moved to Albany, N.Y., from Austin, Texas, and the state of New York invested an estimated $300 million in the 450mm program at ISMI. Intel assignee Tom Jefferson headed up the ISMI 450 program, with another Intel assignee, Tom Abell, serving as the point man for many of the negotiations with the tool suppliers.

In a parallel track, Intel, Samsung and TSMC – the so-called IST group of device makers supporting the 450mm transition – began plotting a timeline for 450mm-capable pilot and production lines.

The announcement of the Global 450 Consortium consolidates the 450 effort into one consortium, with access to the new CNSE Fab West building now under construction at the CNSE campus.

Fab construction firm M+W is building a $300 million research center at the University at Albany’s College of Nanoscale Science and Engineering (CNSE) at the University at Albany, which will be part of the Global 450 Consortium, according to a spokesman for the CNSE.

The building will be ready to install the fab equipment by July 2012, according a report from The Business Review, an Albany-based  news Web site, citing Alain Kaloyeros, senior vice president and CEO of the Albany Nanotech complex, as its source. The new building, according to the report,  will include a 50,000 square ft. cleanroom and have room for 800 employees.

A Sematech spokeswoman sent out a statement, which indicated the Sematech ISMI 450 program “has built the foundation for where the industry is today in the transition to 450mm, and our program is now a part of the new initiative, which will build on and expand our efforts.”

Bob Johnson, a Gartner analyst, said the transition from a Sematech-led 450 program to a separate consortium using the CNSE facility makes good sense. The overall 450 program is moving into a more expensive phase, where beta tools must be developed and tested, and a comprehensive process flow must be proved out. That will take many billions of dollars, and duplicating efforts is not an option.

“This is an example of where the four big companies – Intel, GlobalFoundries, TSMC, and Samsung – decided to step up to the plate and get this going in ways the 450 program couldn’t do,” Johnson said, adding that Toshiba remains the only large chip manufacturer outside of the new consortium. Micron Technology and Elpida also are mulling their 450 options, he noted.

The CNSE Nanotech operation has proven its ability thus far to protect IP, even where competing firms are operating side-by-side, he noted.

Gartner’s team of analysts has created a timeline which foresees a 450mm volume fab going into operation in 2018-2019. The major equipment companies, such as Applied Materials and Novellus Systems, may have beta tools ready next year, Johnson said. The new Global 450 Consortium may support some of the beta tool development efforts, he added.

The pilot line at Albany Nanotech will move into operation in 2013, with the participating companies working out the bugs from the process. The major device makers will set up their own pilot lines around 2016-2017, he said.

“The companies have to make sure that their processes yield chips at the same rate on 450 wafers as they do on 300 millimeter wafers,” he said.

One important question is how the lithography tool vendors will handle the 450 transition. Any 450 line will need both EUV and 193nm tools. And the throughputs must improve so that the device makers will see the cost savings which drive the move to the larger wafer size.

The Global 450 Consortium is “an efficient way to do the R of the 450 R and D. It is a way to go from concept to a feasible set of tools and processes,” he said.