By Ed Korczynski, Sr. Technical Editor
Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.
We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.
So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.
Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.
In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”
Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.
Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.
Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.