By Mark LaPedus
Enterprise-based bring your own device (BYOD) programs continue to become more commonplace. In fact, 38% of companies expect to stop providing devices to workers by 2016, according to a global survey of CIOs by Gartner.

What would happen if half of all global DRAM production, two-thirds of NAND flash manufacturing and 70% of the world’s tablet display supply suddenly disappeared from the market? For high-tech companies, this could be the outcome if current tensions escalate to the point of war on the Korean peninsula, resulting in the disruption of South Korea’s technology manufacturing base, says IHS iSuppli.

Intel telegraphed its future directions. The chip giant has named Brian Krzanich as its next chief executive, succeeding Paul Otellini. Krzanich, Intel’s chief operating officer since January 2012, will become the sixth CEO in Intel’s history. As announced, Otellini will step down as CEO. In a research note, Hans Mosesmann, an analyst with Raymond James, said: “We are not entirely shocked by the news but note that some investors preferred an external option on the belief that new blood was needed. Giving Krzanich’s manufacturing background we think the appointment is an indication that Intel will continue Paul Otellini’s strategy of building bigger/better fabs to attack the market. We also believe the move toward better manufacturing processes (like the 450mm transition) will remain front and center.” Added RBC Capital analyst Doug Freedman: “The move to appoint Renee James (as president) is likely in support of the vision of Krzanich’s and the board has laid out for the future of Intel. This appointment validates the increasing importance of on-going software development to Intel’s future, whether it be internally or in collaboration with partners.”

Microsemi has inked a foundry deal with Intel. Microsemi is currently engaged with customers and has started designs utilizing Intel’s 22nm tri-gate technology. Product delivery is anticipated to begin in late 2014 to early 2015.

Infineon and GlobalFoundries announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology. The cooperation will focus on technology development based on Infineon’s eFlash cell design and manufacturing of automotive and security microcontrollers with 40nm process structures.

GlobalFoundries has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20nm and 14nm. GlobalFoundries is using the Cadence Pattern Classification and Pattern Matching Solutions.

SEMI announced that Philip Yeo, chairman of Spring Singapore, and Lee Kok Choy, country manager of Micron Technology Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry. The awards will be presented during festivities held at Semicon Singapore 2013 on May 7.

Soitec has finalized a ZAR 1,000,000,000 (more than $100 million) solar financing bond issued by CPV Power Plant No.1 Bond SPV, an affiliate of Soitec Solar GmbH. The bonds will finance the construction of a 44 MWp utility-scale concentrator photovoltaic (CPV) solar power plant in Touwsrivier, South Africa.

Applied Materials and The Center for Science Teaching and Learning (CSTL) announced the San Francisco Bay Area grand-prize winning team and nine finalist teams in the 2013 Clean Tech Competition.

Rudolph has purchased selected assets related to 3D metrology from Tamar Technology.

Proteus Digital Health has completed a second closing of its Series F financing, raising $62.5 million in total. New corporate investor Oracle joins Otsuka, Novartis, Sino Portfolio and others in this funding round. Proteus is working to create a new category of products. Called Digital Medicines, these new pharmaceuticals will contain a tiny sensor that can communicate, via a digital health feedback system, vital information about an individual’s medication-taking behavior and how their body is responding.

Is Mindspeed Technologies on the block? The supplier of semiconductor solutions for communications has retained Morgan Stanley as a financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Spansion has acquired the microcontroller and analog business of Fujitsu Semiconductor for approximately $110 million, plus approximately $65 million for inventory.

Amkor Technology announced that Stephen Kelley has been appointed to serve as president and CEO. He succeeds Ken Joyce, who previously announced his intention to retire.

ASE remained the world’s largest OSAT in 2012, according to the new rankings from Gartner.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
New research reveals that 53% of office workers with computers are opting to either fix their own computer problems, or ask a co-worker or someone else for help, instead of relying on an IT professional/helpdesk. The nationwide survey, conducted online by Harris Interactive on behalf of Crucial.com, also revealed that 29% of office computer users cite computer problems (lost files, slowness, crashes, etc.) as the top reason for reduced productivity in the office. Office computer problems trumped co-workers (25%), workload (22%), management (22%) and customers/clients/vendors (15%) when it comes to negatively affecting worker productivity in the office.

Big banks may be considered too big to fail, but their size and operational complexity create performance drags that could also make them too big to succeed, according to Gartner. Bank CIOs and COOs must innovate in IT and operations to negate a problem Gartner has identified as the “law of diminishing IT returns.”

Intel announced its annual equipment and materials supplier awards. The awards provide an insight regarding the fab suppliers at Intel, which normally declines to comment about the identity of its vendors. The winners are interesting, but it’s even more interesting to see which vendors failed to make the list. Meanwhile, Intel announced the eight winners of the company’s most prestigious award for equipment and materials suppliers, the Supplier Continuous Quality Improvement (SCQI) award. In addition, Intel announced that 17 equipment and materials companies will receive the 2012 Intel Preferred Quality Supplier (PQS) award.

DARPA has achieved world record power output levels using silicon-based technologies for millimeter-wave power amplifiers. The power amp was based on a multiple-stacked, 45nm silicon-on-insulator (SOI) CMOS device.

Electronic components distributor Digi-Key announced the signing of a global distribution agreement with Adesto Technologies, a developer of nonvolatile memory chips. One of Adesto’s investors is Applied Ventures, the venture capital arm of Applied Materials.

The global semiconductor materials market decreased 2% in 2012 compared to 2011, while worldwide semiconductor revenues declined 3%, according to SEMI.

For the Southeast Asia region, SEMI expects to see capital equipment investment to bottom out in the first half of 2013 and a mild pickup in the second half followed by a strong recovery in 2014. Overall front-end fab equipment spending is expected to double next year from $810 million in 2013 to $1.62 billion in 2014, according to SEMI.

Mentor Graphics announced various hardware and software solutions to accelerate the verification of Serial Attached SCSI (SAS) second-generation (Gen 2) products. Using the Mentor verification solutions, designers can test their SAS Gen2 devices integrated on their SoC designs, and develop and test their software drivers and applications prior to silicon being available.

Entegris, a supplier of contamination control and materials handling solutions, has acquired the assets of Jetalon Solutions, a California-based supplier of fluid metrology products.

Avago announced the execution of a definitive agreement to acquire CyOptics, a supplier of indium phosphide (InP) optical chip and component technologies for the data communications and telecommunications markets, for an aggregate acquisition price of approximately $400 million in cash.

2012 was a miserable year for the semiconductor market, with only 8 of the top 25 chipmakers managing to eke out revenue growth. Among the top 25 suppliers, the only companies to expand revenue in 2012 were No. 2 Samsung, No. 3 Qualcomm, No. 9 Broadcom, No. 11 Sony, No. 14 NXP, No.15 nVidia, No.18 MediaTek and No. 24 LSI.

Worldwide PC shipments totaled 79.2 million units in the first quarter of 2013, a 11.2% decline from the first quarter of 2012, according to preliminary results by Gartner. Global PC shipments went below 80 million units for the first time since the second quarter of 2009.

3D printing, touted as an enabling platform for applications ranging from personalized medicine to personal drones, will grow to an $8.4 billion market in 2025, up from $777 million in 2012. However, consumer applications will have limited upside, according to Lux Research, while industrial uses generate the most value.

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus
Sara Volz, 17, of Colorado Springs, Colo., won $100,000—the top award—from the Intel Foundation for her research on algae biofuels. Algae produces oil that can be converted into a sustainable, renewable fuel. Volz, who built a home lab under her loft bed, sleeps on the same light cycle as her algae.

For years, the investment community has demanded that ASM International (ASMI) should break up the company into two pieces. This week, ASMI finally caved in, leaving some to wonder if the company is the next takeover target in the semiconductor equipment business. ASMI intends to sell a stake in ASM Pacific Technology, valued at between 8% to 12%. Following the planned divestment, ASMI will own between 40% and 44% of the shares in ASM Pacific, a supplier of wirebonders.

A TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in a cross section. What does this all mean? According to Applied, it’s a breakthrough in reflow to push interconnect boundaries beyond 20nm.

Applied Materials was named by the Ethisphere Institute, a business ethics think-tank, as one of the 2013 world’s most ethical companies.

MEMC, a supplier of silicon and SOI wafers, announced a plan, subject to shareholder approval, to change its name to SunEdison. The name change reflects its recent efforts in the solar industry. MEMC competes in both the semiconductor and solar industries. Does the name change reflect that semis are passé or does MEMC have an identity crisis?

Specialty foundry TowerJazz is seeing significant customer engagements and market share gain in the fast growing RF front-end module market. For Skyworks and others, TowerJazz is providing RF SOI, RF CMOS and SiGe processes.

ALTIS Semiconductor announced the finalization of a foundry agreement with IBM Microelectronics. Under the terms, ALTIS will be the foundry partner for the IBM 180nm RF SOI technology.

SEMI reported that worldwide sales of semiconductor manufacturing equipment totaled $36.93 billion in 2012, representing a year-over-year decrease of 15%.

Cadence has agreed to buy Tensilica, setting the battle over IP into high gear among EDA vendors.

Mentor Graphics announced the Nucleus SmartFit product, a cost-effective, binary version of the Nucleus RTOS optimized to fit the limited internal memory of 32-bit MCUs.

ST-Ericsson, a joint venture of STMicroelectronics and Ericsson, announced that Didier Lamouche, president and chief executive, has decided to resign from the company to pursue other opportunities. And following those events, Ericsson and STMicroelectronics this week announced an agreement on the fate of ST-Ericsson. Ericsson will take on the design, development and sales of the LTE multimode thin modem products, including 2G, 3G and 4G multimode. ST will take on the existing ST-Ericsson products, other than LTE multimode thin modems, and related business as well as certain assembly and test facilities. The companies will close down the remaining parts of ST-Ericsson.

China’s Advanced Micro-Fabrication Equipment (AMEC) will make its solid-state lighting market debut with a new multi-reactor metal organic chemical vapor deposition (MOCVD) cluster tool. The Prismo D-Blue MOCVD platform enables high-volume manufacturing of GaN, InGaN and AlGaN structures required for high-brightness LEDs.

Nanoplas announced a new dry-etch process that offers unlimited etch selectivity for removing dielectric films. Nanoplas’s new Atomic-Layer Downstream Etching (ALDE) processing allows etching rate and selectivity to be controlled independently.

According to IHS, the steady increase in PC capabilities that has justified the upgrade cycle and fueled the long-term growth of the PC market is undergoing a historical deceleration.

Household adoption and spending on consumer technology products is shifting faster than expected in favor of gadgets and services that are portable or mobile, according to a recent survey by Gartner.

By Mark LaPedus
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node.

Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts to introduce their initial finFET processes at 14nm. And the foundries are already defining their next-generation finFETs at 10nm.

Chipmakers face numerous challenges in terms of ramping up their first- and next-generation finFETs. But the challenges, and costs, could pale in comparison when vendors extend finFET technology to the 7nm and 5nm nodes—or perhaps beyond.

Starting at 7nm, chipmakers plan to inject finFETs with various and exotic III-V materials in the channels to boost the mobility, which refers to how fast the electrons can move through a device. Currently, the industry has narrowed the options down to about five leading candidates for the high-mobility finFET era: finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET.

The two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs. “Conventional thinking currently suggests that we will see a Ge PFET and an InGaAs NFET at 7nm,” said Dean Freeman, an analyst with Gartner. “If the industry could make a silicon nanowire, and create a transistor using silicon and high-k/metal-gate, then we could see the industry move in that direction.”

The III-V materials themselves exist today, but many of the associated manufacturing techniques are in their infancy or simply don’t exist. Bringing up compound semiconductor materials in silicon fabs is a monumental task. And the ability to design and integrate III-V finFETs in a cost-effective manner is easier said than done. “This is not a straightforward process,” said Luc Van den hove, chief executive of IMEC. “We are talking about materials with different lattice constants.”

The challenges leave some observers wondering whether chipmakers should skip the high-mobility finFET era and move directly to the more exotic technologies like carbon nanotubes and graphene. Perhaps the best avenue is the pursuit of stacked 2.5D/3D devices.

Looking into his crystal ball, Gary Patton, vice president of IBM’s Semiconductor Research and Development Center, predicts the two 3D-like approaches, finFETs and stacked die, will have a long and viable future. “The 3D era should carry us well into the 2020 timeframe,” Patton said. “I expect finFETs will last a decade. But then at some point, we hit the atomic dimension limit. Then, we’re talking about silicon nanowires and carbon nanotubes. And to deal with the interconnect issues, we have to talk about integrating photonics on the chip and stacking multiple chips together. That’s really in the next decade.”

Take III-V
Today, the industry is moving towards an inflexion point. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects. So, at 14nm, foundries will introduce finFETs, which have better short-channel electrostatic characteristics than planar.

Today’s finFETs will likely scale at least two generations to 10nm, said Subramani Kengeri, vice present of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V materials to provide a mobility boost, Kengeri said.

The next roadblock is that today’s strained-silicon technology is under stress. For some time, chipmakers have used a silicon-germanium (SiGe) alloy stressor in the channel to boost carrier mobility. “Starting from the 90nm and 65nm nodes, the source-drain areas have been grown using a SiGe epi process in order to bring strain into the device,” said IMEC’s Van den hove. “With strain, we can increase the drive current and device mobility. In the finFET structure, we can do that as well. But this space is very limited, because of the [difficulties] to introduce enough strain into those tiny channels. An alternative way to boost the drive current is by using materials that have intrinsically higher mobilities. This will reduce power consumption.”

The first of these high-mobility devices is expected to appear at 7nm, with the emergence of a finFET with Ge in the p channel and tensile silicon in the n channel. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,400cm-square-over-Vs for silicon.

“But germanium in the p channel is not a straightforward process,” said Aaron Thean, director of the logic program at IMEC. “Germanium tends to move around once exposed to temperature. So the challenges are defects and the structural stability of the device. The surface passivation (for the high-k/metal-gate stack) is also very tricky.”

Following this device, the industry will move to a next-generation high-mobility finFET at 7nm. The first option is a finFET with Ge for both the p and n channels. The second option is Ge for the p channel and indium gallium arsenide (InGaAs) for the n channel. InGaAs has an electron mobility of 12,000cm-square-over-Vs.

“Those two options are competing,” Thean said. “The germanium-germanium option requires compressively strained Ge in the p channel and relaxed Ge in n channel. There are issues with the gate stack and dopant activation.”

Intel and others are leaning toward the Ge-InGaAs option. “InGaAs is our front-up option. It can offer mobilities up to 10X and higher. It’s a better-understood III-V material. I wouldn’t say InGaAs is easy in terms of processing, but it is not as challenging of a material to handle,” Thean said.

The other 7nm candidate is the gate-all-around (GAA) finFET, which can have two or more gates that are wrapped around by a nanowire channel. Purdue University, for one, recently demonstrated GAA finFET with 20nm channel lengths and a sub-threshold swing of 63mV/decade. “There are still lots of challenges with GAA,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.”

Intel and others also have shown interest in the TFET, which may appear at 5nm. In TFET, a tunnel barrier is created at the source-channel contact to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5 volts, said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “TFETs enable steeper sub-threshold voltages,” he said.

There are other options, such as exotic III-V materials for both NFET and PFET. Other III-V materials, including indium antimonide (InSb), are still in R&D. The Sb materials are promising, but have narrow band gaps.

Tool gaps
All of the futuristic, high-mobility finFET devices suffer from the same problem—they are expensive and difficult to manufacture. The most obvious problem is lithography. It’s still unclear if extreme ultraviolet (EUV) lithography will be ready for the 7nm node, meaning the industry may need to extend 193nm immersion and multiple patterning.

Patterning is only one piece of the finFET puzzle. “Lithography has been the story for at least the last 10 years,” said Mike Splinter, chairman and chief executive of Applied Materials. “Now, we are seeing many of the bottlenecks in interface engineering, precision materials and how are you going to get the low-k values.”

For example, RF chipmakers have been fabricating III-V chips in trailing-edge fabs at smaller wafer sizes. At 7nm, the challenge is to grow III-V materials on 300mm or 450mm silicon wafers with good yields and throughput.

It’s unclear which technology, bulk or FD-SOI, will prevail at 7nm and beyond. STMicroelectronics says FD-SOI can extend to at least 10nm and perhaps beyond. “We are continuing to look at SOI,” said IMEC’s Thean. “The nice thing about fully-depleted devices on SOI is that they have excellent isolation.”

In one emerging SOI effort, Ed Nowak, device chief designer at IBM, recently described a fin-on-oxide (Fox) technology that could scale to 5nm. Fox enables a finFET technology with oxide dielectric isolation. Like SOI, Fox enables the finFET manufacturer to produce a controlled fin height, thereby reducing variability. Silicon wafer maker MEMC recently rolled out SOI substrates based on Fox.

The integration between III-V and silicon is perhaps the biggest issue. “In III-V, for example, we use gold as a contact material,” said Raj Jammy, vice president of emerging technologies at Sematech. “Gold is a poisonous material for silicon. So, you need to come up with a new contact metal scheme.”

There is also a need for new metrology tools to find defects in III-V finFETs. New tools are also are required for GAA finFETs with nanowires. “When it comes to gate all-around, you need selective ALD processes,” Jammy said. “For fin/gate fidelity, this requires selective III-V/Ge epi. For etch, we might not be able to use the processes we have today. We are looking into ALD etch.”

The industry is making progress on one front. “One of the areas we are looking at is a low damage conformal 3D doping technique, which we call monolayer doping,” he said. “This enables selective and very shallow junctions. We have solutions with arsenic and phosphorous. What is exciting about this is that the fins that have monolayer doping don’t have any damage.”

All told, high-mobility finFETs promise to enable chip scaling, but the challenges and costs are steep. “There is no free lunch,” he added.

By Mark LaPedus
Is the cell phone market cooling down? Worldwide mobile phone sales totaled 1.75 billion units in 2012, a 1.7 percent decline from 2011 sales, according to Gartner. The last time the worldwide mobile phone market declined was in 2009. On the bright side, smartphones continued to drive overall mobile phone sales, and the fourth quarter of 2012 saw record smartphone sales of 207.7 million units, up 38.3% from the same period last year.

Egypt’s Si-Ware Systems, a fabless chipmaker, has licensed its MEMS FT-IR spectrometer technology to Hamamatsu Photonics. The FT-IR spectrometer is the world’s first single-chip spectrometer. The technology is based on Si-Ware’s Silicon integrated Micro Optical System Technology (SiMOST). With the technology, multiple optical MEMS structures can be patterned and etched on SOI wafers using deep reactive ion etching. The structures are then wafer-level packaged and diced to create a one-chip optical system. 4

Applied Materials reported its Q1 results for fiscal 2013. Orders grew 44% sequentially led by demand for semiconductor and display equipment.

In its conference call, Mike Splinter, chairman and CEO of Applied, said: “We now believe the 2013 wafer fab equipment will be flat to down 10% relative to 2012 spending of around $30 billion.”

Applied also announced that Charlie Gay, president of Applied’s Solar division, has been elected to the National Academy of Engineering (NAE) for his contributions to the development of the global solar industry.

Worldwide silicon wafer revenues declined by 12% in 2012 compared to 2011 according to SEMI. Worldwide silicon wafer area shipments declined 0.1% in 2012 when compared to 2011 area shipments.

Pure, part of Imagination Technologies, has used Mentor Graphics’ technology and services to create its digital TV recorder 3D user interface.

Cadence announced the election of Young Sohn, president and chief strategy officer of Samsung Electronics, to its board of directors.

2013 has barely started, but various research firms already are making predictions for this year and next. For example, Semiconductor Intelligence has revised its 2013 chip forecast to 7.5% growth. The firm is holding its 2014 forecast at 12%. The firm also compares its predictions with other recent forecasts for 2013 and 2014.

Ten product categories, led by tablet MPUs and cell-phone application MPUs, are forecast to exceed the 6% growth rate forecast for the total IC market this year, according to IC Insights.

OEM spending on semiconductors for wireless applications is set to rise by 13.5% this year to reach a value of $69.6 billion, up from $62.3 billion in 2012, according to the IHS.

Revenue in 2013 for the worldwide outsourced manufacturing industry is forecast to reach $404.5 billion, up 4.5% from $387.0 billion last year, according to the IHS.

By Mark LaPedus
In New York, Saratoga County is booming. Saratoga counts on several growth engines, including semiconductors. In the county, GlobalFoundries is ramping up a new fab and recently announced an R&D center. In addition, there is a new push to build casinos in the county to further boost the local economy. But the local mayor is apparently against the idea, according to reports.

Samsung overtook Apple as the top worldwide semiconductor buyer in 2012, according to Gartner.

In 2012, Samsung almost doubled its foundry sales and surpassed UMC to become the third-largest IC foundry in the world, according to IC Insights. IC Insights believes that Samsung will challenge GlobalFoundries for the No. 2 spot in the rankings in 2013.

Synopsys announced immediate availability of its EDA solutions for finFET-based semiconductor designs. GlobalFoundries and Samsung are collaborating with Synopsys in the arena.

Soitec announced its results for the third quarter. The mobility-driven markets continue to offset PC segment weakness.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.92 in December, up from 0.79 in November, according to SEMI. “Both bookings and billings increased in December, but remain below figures reported one year ago,” said Denny McGuirk, president and CEO of SEMI. “While uncertainty remains regarding the 2013 equipment outlook, the foundry and advanced packaging segments are the key investment drivers at the beginning of the year.”

SEMI announced that Rudy Kellner, vice president of the Industry Group at FEI, has joined the SEMI North American Advisory Board (NAAB).

The new edition of the International Technology Roadmap for PV (ITRPV) will be presented and published at the upcoming PV Fab Managers Forum, according to SEMI.

The Chinese end market dominated shipments of solar photovoltaic (PV) panels during the final quarter of 2012 with 33% of global end-market demand, according to NPD Solarbuzz.

Solar PV equipment spending was $3.6 billion for 2012, a 72% decline from the peak of $12.9 billion in 2011, according to NPD Solarbuzz. Finlay Colville, vice president at NPD Solarbuzz, said: “Spending for 2013 is forecast to decline even further to $2.2 billion, levels not seen in the industry since 2006.”

Mentor Graphics announced a hardware emulation solution for ARM Cortex-A9 MPCore processor-based system-on-chip (SoC) designs.

After two straight years of contraction, the global DRAM market has the opportunity to rebound to double-digit growth in 2013, according to IHS iSuppli.

A new generation of lower-cost and more appealing ultrabooks is expected to help cause global shipments of solid-state drives (SSDs) to more than double in 2013, according to IHS iSuppi.

With emerging economies such as China and India slowing down, the Southeast Asian nations are emerging as key destinations for multinational companies, both as markets for their products as well as a source for new technologies, according to Lux Research.

By Mark LaPedus
In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations.

Dual damascene remains the workhorse process flow in the fab since its fabled introduction. But more recently, there are questions regarding the extendibility of the trusty dual damascene flow as the IC industry moves towards the 14nm node and beyond.

It all boils down to the interconnect. Copper interconnects—the tiny wiring schemes in devices—are becoming more compact at each node, causing an alarming increase in the resistance-capacitance (RC) delay. “The interconnect scaling roadmap looks like a looming disaster,” said Rob Aitken, an ARM fellow. “We want the materials to save us.”

The problem is that the dual damascene flow may extend to 10nm—and then could promptly run out of steam, according to some experts. Then, at 7nm, the industry may need to switch gears and move to a new flow—the single damascene process.

At 5nm, chip makers may need to switch again and re-visit the subtractive reactive ion etch (RIE) process for copper. Ironically, the industry explored the development of subtractive copper etch a decade ago, but the technology never got off the ground and was shelved.

Still others believe the risk-averse industry would rather extend the current technology as long as possible before moving to a new process. “I think dual damascene will extend to 10nm and probably the 7nm node,” said Daniel Edelstein, a fellow and manager of BEOL technology strategy at IBM. Edelstein was also the original project leader for IBM’s groundbreaking dual damascene efforts in the 1990s.

“I regard single damascene as a backup, not a front-up roadmap point,” he said. “Copper RIE is just one component of a subtractively etched multilevel copper wire and via integration, which I think is unworkable for copper.”

Beyond 7nm, the industry is looking at dual damascene, single damascene and copper RIE. In parallel, the industry is taking a different approach to the RC problem by working on stacked 2.5D and 3D chips. And for the distant future, the industry is looking at new transistor schemes, photonics and other technologies.

The looming crisis
For years, the industry has been grappling with a crisis in the interconnect. The industry averted a disaster in 1997, when IBM rolled out its CMOS 7S process, a 0.22-micron technology using the industry’s first dual damascene flow.

Until then, leading-edge logic devices deployed aluminum interconnects using an aluminum subtractive etch process. But as the industry moved towards 0.25-micron geometries and beyond, aluminum was unable to withstand the higher current densities in logic. And copper was (and still is) about 40% less resistive than aluminum, and it is less vulnerable to electromigration.

More recently, DRAM makers have made the transition from aluminum to copper. The shift towards copper requires a dual damascene process, which takes place at the back-end-of-the-line (BEOL) in the manufacturing flow. The process enables the formation of two main parts of the interconnect: metallization and low-k dielectrics.

In the dual damascene process, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin layer of barrier of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper seed barrier via PVD. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).

In the single damascene process, the trenches and vias are formed one step at a time. In contrast, they are formed simultaneously in dual damascene. Fewer steps make dual damascene a less expensive approach. And in a completely different flow, the copper subtractive process makes use of RIE tools.

Dual damascene, meanwhile, continues to extend and evolve. PVD, the workhorse tool technology for the metallization process in dual damascene, may extend to at least 10nm. But if PVD should stumble, the industry is evaluating rival tool technologies like chemical-vapor deposition (CVD) and atomic-layer deposition (ALD).

In the low-k part of the equation, however, the technology remains stuck. “The RC delay is increasing,” said Dean Freeman, an analyst with Gartner. “To improve the RC delay, you need lower k materials. But to get lower k, you need to add more porosity or air to the dielectric material. That compromises the structural integrity of the dielectric. It also makes it more difficult to keep the copper from diffusing into the dielectric and causing shorts, or leakage between metal lines.”

There are also challenges in the metallization process. “The resistance of the copper is also increasing. As you get smaller and smaller vias and lines, you get smaller and smaller grains. A smaller grain/crystal means that you have more electron scatter, which increases the resistance and the heat in the device. This is why the device manufacturers are trying to keep the metal lines as wide as possible where they can,” Freeman said.

At 14nm, in fact, the interconnect is headed toward an “inflection point,” in which copper resistivity increases exponentially, said Mehul Naik, a distinguished member of the technical staff at Applied Materials.

“The question is how long you can extend copper damascene,” Naik said. “From a resistive perspective, how can you get more and more copper inside the trenches and how can you design your materials so you get rid of scattering issues that increase the copper resistivity. It’s maximizing the volume and minimizing the scattering of copper. If we can achieve that, we can extend damascene as far as possible. But that goes back into how you pattern the copper and get the fine pitch, and what kinds of issues you run into when you get a fine pitch.”

If dual damascene runs out of steam, the industry is looking at single damascene technology and subtractive copper etch. In theory, the single damascene approach could potentially enable smaller gaps with higher aspect ratios, but it is more expensive, Naik said.

Unlike single damascene, which may use existing tool technologies and materials, the industry may need to start from scratch in subtractive copper etch. “There are no tools (in the market),” he said. “So, you would need to develop a copper etch process.”

What’s next?
Looking into his crystal ball, IBM’s Edelstein sees dual damascene extending to at least 7nm and predicts a cloudy future for copper RIE. “Single damascene would be the backup with penalties if dual damascene breaks irreparably,” he said.

“Copper RIE discussions always seem to neglect the classic copper integration problems that would come with it.  These problems were circumvented by going to damascene in the first place,” he said. “Why would bringing those unsolved problems back be any easier at vastly smaller dimensions? How would you propose to make a viable subtractive-etched multilevel copper BEOL line/via integration at competitive pitches, with all the needs for copper passivation, via contact, electrical and corrosion insulation, while at the same time retaining competitive cost, performance and reliability?”

Beyond 7nm, there are new and conventional approaches on the table. Even before 7nm, the industry is developing 2.5D/3D stacked chips to circumvent the RC delay problem. But advanced chip stacking has a number of challenges and is still a few years away from mass production

There are other and more futuristic technologies in R&D, many of which are exotic and expensive. The candidates include carbon nanotubes contacts, graphene, photonics, network-on-a-chip architectures, smart interconnects and others, said Jon Candelaria director of interconnect and packaging sciences at the Semiconductor Research Corp. (SRC).

For example, using a single damascene process, IMEC, TEL and others recently described 150nm diameter contacts filled with carbon nanotubes and a copper top metal. Carbon nanotubes before metallization reduced the single contact hole resistance from 4.8 kΩ down to 2.8 kΩ.

In a separate effort, Japan’s AIST recently fabricated multi-layer graphene interconnects directly on silicon dioxide by annealing sputtered amorphous carbon with a cobalt catalyst layer. A resistivity of around 500 μΩcm was obtained after cobalt removal.

And for years, the industry has been talking about the use of optical interconnects. “The bottom line is that the RC delay is increasing and there are no great solutions on the horizon other than copper and low-k,” said Gartner’s Freeman. “Ideally, the industry would like to go to a material with lower resistance, such as gold or carbon nanotubes for the interconnect. Unfortunately, gold is a bit too expensive and does not provide significant improvement over copper.”

Graphene is also expensive and involves some tough integration problems. “While nanotubes have demonstrated great promise, they have high resistance where they make contact to the metal lines. But IMEC has suggested that we are further along than people think on this topic,” Freeman said. “Optical interconnects are still a ways out. The big issue here is creating the laser and the collector in silicon, or on silicon. Intel continues to research this and I think they are getting close on chip-to-chip, but we are still a ways away from the technology.”