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Posts Tagged ‘Fujitsu’

Blog review February 24, 2014

Monday, February 24th, 2014

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. But as Pete Singer blogs, he also said: “In the end, if this isn’t cheaper, no one is going to do it,” he said.

Adele Hars of Advanced Substrate News reports that body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages.

Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc., says the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation. This is putting more emphasis on high sigma yield.

Jamie Girard, senior director, North America Public Policy, SEMI President Obama touched on many different policy areas during his State of the Union talk, and specifically mentioned a number of issues that are of top concern in the industry and with SEMI member companies. Among these are funding for federal R&D, including public-private partnerships, trade, high-skilled immigration reform, and solar energy.

Phil Garrou finishes his look at the IEEE 3DIC meeting, with an analysis of presentations from Tohoku University, Fujitsu’s wafer-on-wafer (WOW), ASE/Chiao Tung University and RTI. In another blog, Phil continues his review of the Georgia Tech Interposer conference, highlighting presentations from Corning, Schott Glass, Asahi Glass, Shinko, Altera, Zeon and Ushio.

Pete Singer recommends taking the new survey by the National Center for Manufacturing Sciences (NCMS) but you may first want to give some thought as to what is and what isn’t “nanotechnology.”

The Week in Review: February 14, 2014

Friday, February 14th, 2014

Worldwide silicon wafer revenues declined by 13 percent in 2013 compared to 2012 according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments increased 0.4 percent in 2013 when compared to 2012 area shipments.

Silicon wafer area shipments in 2013 totaled 9,067 million square inches (MSI), slightly up from the 9,031 million square inches shipped during 2012. Revenues totaled $7.5 billion down from $8.7 billion posted in 2012. “Annual semiconductor silicon shipment levels have remained essentially flat for the past three years,” said Hiroshi Sumiya, chairman of SEMI SMG and general manager of the Corporate Planning Department of Shin-Etsu Handotai Co., Ltd. ”However, industry revenues have declined significantly for the past two years.”

Rudolph Technologies, Inc. announced this week the sale of its first NSX 320 TSV Metrology System to CEA-Leti, a research organization based in Grenoble, France, which, in the frame of the Nanoelec Research Technology Institute (Nanoelec RTI) program, is developing three-dimensional integrated circuit (3DIC) technologies that use through silicon vias (TSVs) to conduct signals among vertically-stacked chips. The new NSX 320 TSV system includes integrated 3D metrology that enables specialized measurements critical to the TSV process.

Honeywell announced today that it has introduced new RadLo low alpha plating anodes based on proprietary technology to help reduce alpha particle radiation that can lead to data errors in semiconductors. The new plating anodes for semiconductor packaging wafer bumping applications expand Honeywell’s RadLo offerings and employ proprietary Honeywell metrology and refining techniques.

At this week’s International Solid State Circuits Conference (ISSCC2014), imec and Holst Centre, together with Olympus, demonstrated a low-power single channel implantable electrocardiography (ECG) acquisition chip with analog feature extraction, which enables precise monitoring of the signal activity in a selected frequency band. Leadless Pacemakers with ultra-small size and ultra-low power consumption are emerging, improving analysis and clinical research of the intra-cardiac rhythm, and as a result, improving patients’ quality of life. The new low-power ECG acquisition chip advances the state-of-the-art by consuming only 680nA when all features are active, and also provides competitive performance, such as input SNR>70dB, CMRR >90dB, PSRR >80dB without any external passive components. By equipping an ultra-low power analog feature extractor, the new chip is capable of assisting digital signal processor platforms for the implementation of low-power heartbeat detection algorithms.

SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets today announced the opening of a new office in Korea. The new SPTS Korea office is situated in Pangyo and will be the central base of operations for sales, field process and engineering staff. The new facility will also carry essential and critical spares inventory to support SPTS’ system installed base.

Fujitsu Laboratories Ltd. and imec Holst Centre this week announced that they have developed a wireless transceiver circuit for use in body area networks (BAN) for medical applications that adheres to the 400 MHz-band  international standard. While the subject of high expectations for medical applications, wireless monitoring of brainwaves or other vital signs has in the past required over a dozen milliwatts (mW) of electric power. Now, however, by optimizing the architecture and circuitry, Fujitsu Laboratories and imec Holst Centre have succeeded in reducing the electric power requirements of wireless transceiver front-ends, to just 1.6 mW when receiving data and 1.8 mW when transmitting.