By David Lammers
Throwing in its hat as a third path to scaling alongside finFETs and fully depleted SOI, SuVolta Inc. claims it has developed transistor processing techniques which support significant improvements in both active and leakage power, and on a planar bulk CMOS platform.
Scott Thompson
The startup has attracted a team of highly regarded former Intel and AMD technologists, including chief technology officer Scott Thompson, who spent a dozen years at Intel. Several well-known venture capitalists, notably Forrest Baskett, Bill Joy, and Andy Rappaport, are among the financial backers.
Fujitsu Semiconductor is an initial licensee, with early plans to quickly improve the power consumption of several 65nm designs by applying the SuVolta technology.
SuVolta rolled out its technology Monday (June 6) with supportive comments from several companies, including ARM, Broadcom, and Cypress Semiconductor. Several technology analysts said they are taking seriously SuVolta’s claim that it offers an alternative to finFETs and fully depleted SOI, the two presumed successors to partially depleted planar bulk CMOS technology at advanced technology nodes.
Thompson said SuVolta’s “PowerShrink” platform involves carefully controlling the dopants in the areas just below the inversion region to create what SuVolta is calling a “Deeply Depleted Channel” or DDC. He said the largely undoped channel allows the inversion charge to move from source to drain without scattering from dopant atoms, which kill mobility, particularly at reduced Vdd’s.
SuVolta claims better control of threshold voltage variation.
The company claims its approach also allows for extremely tight control of the threshold voltage. For high performance SoCs, tight threshold voltage is required to avoid variation in the gate overdrive, which leads to performance variation, he said.
The Deeply Depleted Channel transistor is manufactured with “near atomic layer dopant control, without the need for an ALD tool,” Thompson said. The near atomic layer dopant control allows the depletion layer to be controlled far more precisely than in a conventional MOSFET, or in a spacer-defined or lithography defined finFET. “A well-controlled depletion layer width allows for the nominal depletion depth to be deeper than in a conventional MOSFET which in turn allows simultaneously for an undoped channel layer and improved threshold voltage setting, both of which are key for low-power operation,” Thompson said.
Asked if thinness of the channel was key to the SuVolta approach, Thompson said with the deeply depleted technology “there is much less variation in the depletion layer compared with a conventional device. They key part of this is controlling the depth of the depletion layer. That is what gives us the good sigma Vt (variability) that we see with the 65nm devices today.”
SuVolta is aiming at what is now the dominant growth engine for the semiconductor industry: low-voltage SoCs for mobile devices, said Bruce McWilliams, SuVolta’s CEO, who earlier worked for Tessera Inc., another company which relies on a licensing model for its revenues.
McWilliams said SuVolta’s initial mobile SoC customers can achieve half the power at the same performance, with no changes to the mask set, no new tooling, and no change in their IP cores.
The company also has an engineering team in place which is developing the basic libraries and core IP that will deliver additional power savings for companies using the SuVolta technology from scratch. The engineering team has taped out test circuits and is running foundry shuttles now, sharing the results with potential customers.
“We have 28nm Ion/Ioff data. It matches our expectations for higher mobility from the undoped DDC channel. And the mobility advantage increases at the lower power supply voltages,” Thompson said in an e-mail exchange.
For higher-performance SoCs which need low-power operation, SuVolta’s technology will take advantage of the body coefficient, which supports a fourth terminal in planar CMOS. Planar bulk CMOS platforms, Thompson said, “allow more flexibility in designs by enabling power modes to leverage a wide range of threshold voltages and dynamic threshold voltages, using body bias techniques which are used now for SOCs in general. These techniques are especially important for high-performance SOC operation with low-power supply voltage modes of ~ 0.5 to 0.7V, resulting in active power modes in the ~ 100 mW range.”
McWilliams said Transmeta used a similar technique to lower the power consumption of its x86 core, while the StrongARM processor also employed the body coefficient to raise or lower the voltage. “It is an old technique, but we came up with a structure to greatly boost that, to dramatically cut leakage or boost performance,” McWilliams said, adding that the biasing approach will become critical at 0.5V operation.
Thompson said the first products employing the SuVolta technology will not use biasing. As companies move to more aggressive low-power modes they will adopt reverse biasing to gain “another factor of ten reduction in leakage.”
SRAM at 0.42V
SuVolta presented some data on a test SRAM, manufactured by Fujitsu, showing the minimum (0.42V) operating voltage, leakage, and local threshold voltage matching (AVT/sigma VT).
SuVolta claims a potential 300 mV reduction in SRAM Vdd.
The SRAM supports read/write operation down to 0.42V, without circuit, layout, or mask changes, Thompson said. Normal operation would be at 0.7-0.8V, which compares with about 1V-1.1V for most 65nm technologies.“This represents a greater than 300mV improvement in supply voltage scaling compared to a typical foundry technology. The tight threshold voltage control leads to five times lower leakage power,” Thompson said.
“With our 65nm device targets, we show a 2X improvement in Vt variability, both globally and locally. We believe we can do even better at future nodes. The improvement gets larger at lower voltages, which is helpful for SRAM cell stability,” Thompson said. SuVolta has device data down to the 25nm range. Modeling, Thompson said, “gives us confidence that we can take this approach all the way down to 14nm with good mobility, leakage, and threshold matching.”
The SuVolta CTO said the most difficult-to-control source of threshold voltage variation is local mismatch, which is driven by random dopant fluctuations. Since traditional fabrication techniques do not control the location and number of dopants at the atomic level, Thompson said the number and position of the dopants vary device-to-device. SuVolta is claiming that local threshold voltage control is “as good as the best FD-SOI research devices,” he said.
SuVolta’s claims might engender acute skepticism were it not for the pedigree of the team. McWilliams said he and Thompson came to the startup two years ago, and Thompson came up with a completely different approach to achieving the low-power goals using planar CMOS. After leaving Intel, Thompson worked as a professor at the University of Florida, but is now on leave from the university and is spending all of his time at SuVolta.
Two other top engineers from Intel have joined SuVolta. Lucian Shifren, director of device and modeling, was a lead device engineer at Intel for many years, doing much of the TCAD modeling for Intel’s FinFET technology. Pushkar Ranade, director of process integration, was a lead integrator of Intel’s 45nm and 22 nm technologies, taking those technologies from early pathfinding and development to high-volume manufacturing.
Nick Kepler, who earlier held senior technology management positions at AMD, left GlobalFoundries to manage SuVolta’s product development team. Thomas Hoffman, another well-connected ex-Intel technologist who spent several years as a director at Imec, also recently joined SuVolta.
McWilliams said the chip industry will stick with planar CMOS as long as possible. “We can reuse the existing IP, which we think is key to adoption. People don’t want to go back and redo their libraries.”
Jeff Lewis, senior vice president of business development, said SuVolta is in discussions with foundries. Besides the announced relationship with Fujitsu, Lewis said “we are working with quite a few companies, at both advanced and older nodes. 65 nanometers is a perfect place for us to start, especially for companies looking for a mid-life kicker where they immediately have high volumes. But certainly we are working with the major companies at 28 and 40 nanometers.”
McWilliams added that he believes Fujitsu, which also serves as a foundry, will have a SuVolta-enhanced product “on the market in the next year, along with their customers.”
SuVolta had an unusual rollout for a startup, including supporting statements from companies which normally hold their cards relatively close to their vests.
For example, Pieter Vorenkamp, Broadcom’s senior vice president of engineering and operations, went on the record as saying that “SuVolta’s low-power platform could have a dramatic impact on the industry. The substantial device matching improvement of core and IO devices, enhanced body effect and perceived ‘simple’ integration with a digital CMOS manufacturing could have a dramatic impact on reducing power and cost of highly-integrated SoCs.”
Krisztian Flautner, the vice president research & development at ARM, said, “ARM continues to monitor new technologies that may yield significant power or cost reduction in advanced SoC designs. The aim is to avoid excessive upgrade costs in new fabrication facilities or circuit design. SuVolta’s platform offers a promising approach to extending the scaling of CMOS transistor technology.”
T.J. Rodgers, the founder of Cypress Semiconductor, also issued a statement in support of SuVolta.
SuVolta will compete with finFETs and FD-SOI technologies.
