By Mark LaPedus
For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence.

The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skipping” in the fabless-foundry world could reach new heights.

Two foundry vendors, GlobalFoundries and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), recently accelerated their respective 14nm-class finFET shipment schedules by a year or so. In effect, the companies have shrunk the process cadence between their planar 20nm and 3D-like finFET technologies to roughly a year.

Samsung is expected to follow a similar path. In many respects, the foundries appear to be luring customers into making the giant leap from 28nm (or above) processes to finFETs, thereby skipping 20nm. The reason is largely due to lackluster demand for 20nm planar, and they are aggressively marketing their finFET technologies right now.

Rival United Microelectronics Corp. (UMC) has a different strategy. UMC will move directly from 28nm planar to 14nm-class finFETs, bypassing the 20nm planar node. UMC recently licensed finFET technology from IBM, but it will stick with bulk CMOS. For its part, IBM will ramp up finFETs using silicon-on-insulator (SOI) technology.

The foundries are speeding up their finFET efforts for several reasons. First, there is a perception that the foundries are falling further behind Intel. The chip giant rolled out finFETs at 22nm and is offering the technology to select foundry customers. Intel plans to begin ramping up its 14nm finFET process by the fourth quarter of 2013.

Some chipmakers have been openly critical about the 20nm foundry planar process, saying the technology puts the industry behind the traditional performance curve. “I know some customers want more,” acknowledged Morris Chang, chairman and chief executive of TSMC, in a recent conference call.

So, at 20nm and beyond, chipmakers are weighing their options and exploring the trade-offs. “There will be customers that will skip 20nm to get to (finFETs),” Chang said. “I think there will be customers that will be light on one (process technology) and heavy on another.”

The benefits of finFETs are clear, but the industry is finally coming to grips with the challenges associated with the transistor technology. Cost, patterning and variation are just a few of the issues. The complexity will require more and deeper collaboration between foundries and their customers. “The challenge for us is to work across the ecosystem with our partners and have earlier tapeouts that are fully debugged and tested,” said Gregg Bartlett, senior vice president and chief technology officer at GlobalFoundries.

All told, the fabless-foundry model is still alive and well, but the business continues to change. Going forward, leading-edge foundries will offer fewer process derivatives. Customers will have fewer choices. And in the future, expect possibly one foundry to exit from the leading-edge process race, with more consolidation seen on the horizon.

Skipping around the IC world
At one time, most leading-edge chipmakers followed the natural progression of process technology nodes. The dynamics began to change starting around the 90nm node, when chipmakers migrated towards sub-wavelength lithography, low-k, design-for-manufacturing (DFM) and other technologies.

IC design and manufacturing costs began to soar. As the complexity and cost escalated at each process node, it was no longer a clear-cut decision to follow the natural cadence of process nodes. Chipmakers weighed the various technical and economic trade-offs.

Starting at 90nm, node skipping among chipmakers became the rule instead of the exception. For example, Netronome is currently shipping communications processors based on a 65nm process from TSMC. Instead of moving to 40nm or 28nm, Netronome recently decided to make a giant leap from 65nm to Intel’s 22nm finFET foundry technology. The decision, according to Netronome, was based on density, power consumption and cost.

Node skipping is expected to reach new heights at the 20nm planar process. The so-called “time-to-market” IC makers, such as AMD, Altera, Nvidia, Qualcomm, Samsung, and Xilinx, likely will make the traditional progression from 28nm to the 20nm planar node before moving to finFETs.

Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

With that in mind, there is a temptation to skip 20nm and migrate to finFETs. FinFETs take the traditional 2D planar design and turn the conductive channel on its side, resulting in a 3D “fin” structure surrounded by a gate that controls the flow of current.

Compared to 32nm planar, finFET transistors enable a 37% performance increase at low voltages and a power reduction of 50% or more, according to Intel. Intel’s own Tri-Gate transistor enables a steeper sub-threshold slope at around 80 mV/decade or below, compared to 100 mV/decade for leading-edge planar transistors, said Mark Bohr, senior fellow at Intel, at a recent event.

“Vdd scaling has slowed down. Leakage is an issue as geometries shrink,” said Srinivas Nori, director of SoC marketing at GlobalFoundries. “The value (that finFETs) bring is that it enables one to lower the Vdd. Leakage is better controlled. The variation of the Vt is also much better controlled.”

The benefits are easy to grasp, but the hard part is obvious. “If I was a designer, I would be worried,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is promoting SOI. “If you go back to the standard way of doing things in bulk, and you want a transistor with a different Vt and that drives a different current, you printed different line widths. You just made a fatter transistor. And you paid a little a bit of a penalty in the capacitance,” Mendez said. “How the heck can do you that in finFETs? It’s impossible. So, to make finFETs, you go in quantum steps. The way you actually do this is that you put down one fin, two fins or three fins on a structure.”

Besides the quantum issues, there are other problems. “The fin height is now a huge variable. In a junction-isolated fin, I don’t know how that is accurately controlled. So, from my perspective, this is a tricky thing for an SoC guy to get around. I would imagine you would need pretty stiff design rules to account for this,” he said.

Because of fin height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. The SOI proponents are pushing fully-depleted SOI (FD-SOI), claiming the technology can reduce the process steps and variability with little or no cost penalty.

New roadmaps
The foundries are still pushing bulk, but they have changed their roadmaps. In September, GlobalFoundries rolled out its finFET technology, dubbed 14nm-XM, based on a “modular fin” approach. GlobalFoundries opted to marry a 14nm front-end fin with a 20nm planar BEOL flow. In doing so, the company has accelerated its finFET process by a year. Product tape-outs are expected in 2013, with production slated for 2014.

“Today, customers, IP vendors and the whole ecosystem can actually start working on finFETs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “There are about 7,000 design rules that will carry over from 20nm planar to finFET. From a design point of view, the very early PDKs are almost the same as 20nm.”

Earlier this year, TSMC thought 20nm planar would become a popular node and announced a 20nm pilot line to prepare for the big ramp. But initial 20nm demand is lukewarm. TSMC claims to have 50 tape-outs for the technology, roughly one-fifth compared to that of 28nm.

TSMC’s 20nm pilot line is still on track for 2013. But last month TSMC accelerated its finFET risk production schedule from February 2014 to November 2013. Mass production is slated a year after its 20nm planar process. “This is a somewhat faster cadence than the previous generation,” TSMC’s Chang said.

Meanwhile, UMC said it has developed 20nm planar capability, but the company is not pursuing it as a mainstream process offering. Instead, it is more or less skipping 20nm and pursing finFETs. “After 28nm, finFET will be our focus,” said Shih-Wei Sun, chief executive of UMC, during a recent conference call.

Executives described challenges and opportunities facing the semiconductor industry, at the Semico Summit, held in early May in Phoenix.

Gregg Bartlett, GlobalFoundries: The Economics of Innovation

The convergence of mobility, communication and computing has produced multifunctional end applications that are placing huge demands on semiconductor manufacturers.  These new devices require low power, high performance, and a lot  of advanced manufacturing capacity at a low cost.

At the 2011 Semico Summit, Gregg Bartlett, Senior Vice President of Technology and Research and Development, GlobalFoundries talked about the economics of innovation, highlighting the daunting economic and technology challenges to bring products to market.  Just a few of the major costs include the following:

• $1-2 billion in leading edge process technology development,
• 3-4 years of development,
• $40-$50 million in chip design costs,
• $250 million for design enablement such as libraries and IP,
• $5-$7 billion for an advanced 300mm fab.

Today’s market is a high stakes game.  Its no wonder that the industry has embraced a collaborative environment at all levels.

Bartlett stated that the 20nm node signals an inflection point in the development of technology.  The process will be tightly coupled with the end market application needs.  GlobalFoundries is already working on 20nm and is planning on offering different techniques and options which will allow the customer to optimize the final solution.  But that also means early stage engagements to define the needs.

GlobalFoundries is leveraging the consortia approach in its development of EUV.   The first tool will be installed in their new Malta fab in the second half 2012.  Bartlett stated that double patterning has actually lowered the barrier to entry for EUV.  Foundries such a GlobalFoundries, offer higher product diversity which means there will be some very low volume products.  The cost of double patterning including the amortized cost of the mask could be prohibitive, forcing EUV into the picture.

It’s now becoming evident that the economics of innovation are influenced by the limitations of existing options.   Those with foresight already see the limitations of 300mm.

By Joanne Itow, Managing Director, Manufacturing, Semico Research

Ganesh Moorthy, Microchip Technology: The Invisible Computers in Our Lives

Ganesh Moorthy, Chief Operating Officer of Microchip Technology, examined how much embedded computing permeates our lives.  But he also pointed out how much more opportunity there is for microcontrollers.

Mr. Moorthy showed how several applications that have evolved from very simple solutions to solutions that utilize sensors and intelligence.  This has enabled products that are adaptable, have more security, simplified user experience, improved energy efficiency and more.  Among these are developments in automotive, lighting, thermostats and appliances.  There are new applications for microcontrollers providing support management in personal computing, data centers, handsets, asset tracking & management and personal medical equipment.  Embedded computing is found throughout various applications within the smart power grid.

Mr. Moorthy cited several innovation enablers.

• More integrated features, lower cost
• Higher performance, lower power
• Smaller size
• Wired and Wireless connectivity
• High quality, low cost graphics
• Touch – buttons, sliders, screens
• Energy Efficiency building blocks

Chip vendors need to invest in customer support.  There are more software engineers than hardware engineers involved in the development of MCUs.  A chip vendor cannot just produce silicon, it must also help system designers with tools and expertise.  Today’s applications are just the tip of the iceberg, according to Mr. Moorthy.  There are many more innovations yet to come.

By Tony Massimini, Chief of Technology, Semico Research

Bob Krysiak, STMicroelectronics: Doing Well by Doing Good

STMicroelectronics presented its view on shaping the semiconductor future.  Bob Krysiak, Executive VP and GM of the Americas Region, spoke on how ST and the semiconductor industry is “doing well by doing good.”

Mr. Krysiak pointed out the demographic changes that are occurring.  There is increasing world population with most of this growth in non-Western countries.  By 2050 there will be nearly 10 billion people, an increase of 3 billion over today.  In addition we have an aging population.  This puts pressure on many resources.

The theme of his presentation, “doing well by doing good,” presents the internet and connectivity as key elements in addressing these issues.  He noted that the internet and connectivity have become the plumbing of our world and industry.  There are a growing number of online users, many in China.

We will depend more on the internet and connectivity for increases in productivity and security.  Human productivity will depend more on mobility and wireless.  Banking will be transformed by this, but then security becomes more important.  This will lead to growth in brand authentication, protection and trusted platform security.

With an aging population countries need to deal with healthcare management.  Mr. Krysiak pointed out that in developed countries 12-18% of GDP is for healthcare spending.  Much of this is for chronic disease management, such as diabetes.  Remote monitoring and wellness are the next big explosion of content.  Connectivity will play a major role in this.  Semiconductor technology, including MEMS, offers more affordable solutions, with greater reliability and precision.

The Smart Grid applies IT and networking expertise to deliver energy efficiently.  This includes smart meters, photovoltaics, electric vehicles and Home Area Networks (HAN) working together for energy efficiency by balancing supply and demand.  Network security plays an important role.

The semiconductor industry offers the intelligent control and high performance analog technology to make all of this happen.

By Tony Massimini, Chief of Technology, Semico Research

Tom Dietrich, Freescale Semiconductor: Sensors Changing the Way We Do Business

Freescale’s Senior VP and GM of the RF, Analog & Sensor Group, Tom Dietrich, described Freescale’s vision of a sensor-based future.

Over the next few years Freescale sees the future changing the world, and Freescale will be leading the change as they focus on four growth markets: Automotive, Networking, Industrial, and Consumer while they leaverage three growth trends: The Net Effect, Health & Safety, and Going Green.

For the consumer market we can see how sensors are changing the way we interact with our electronics just by looking at the iPhone and the top ranking apps.  Games now rely on the touchscreen, some rely on tilting the phone, others respond to shaking.  Add this in with networking and we have Cloud Computing.  For example in Japan, a good way to use sensors in cell phones is to have an earthquake app that can combine data from everyone’s phone to a central hub where the data will be analyzed to predict more accurately when and where the next earthquake will occur.  And considering that seismologists are warning of another magnitude-8 quake, this is a feature of sensors that can save lives.

Another feature for the consumer market Tom discussed was Augmented Reality for games.  For example, with sensors, a gamer at home may compete with the pros on the course, using the pros real time moves to compete against in their game.

In the automotive industry, Tom discussed how sensors will help cars, namely with radar, to have a cooperative highways, where cars will proactivity monitor other cars’ locations in order to stop accidents before they can occur. Another life saving feature changing the way we interact with hardware.

Even the healthcare industry benefits from sensors, with in-home monitoring becoming more widely available, allowing doctors and nurses to monitor a patient’s health and quickly react to changes.

While all these ideas are exciting to the average consumer, for Freescale, sensors are a puzzle to solve in how to add more capability to sensors, while continuing to rely on minimal power.  And it looks like they’ve done it.

By Michell Prunty, Consumer Analyst, Semico Research

Paolo Gargini, Intel Corp.: Technology Takes Time

Paolo Gargini—Intel Fellow, Technology and Manufacturing Group and Director of Technology Strategy for Intel—highlighted the time gap between when an idea is formed, to when the science, technology and engineering are able to make that idea a reality.  The incubation time for an idea to become real has shortened from several hundred years for satellites, to 12-15 years now for many ideas.

The driving technology in the semiconductor industry to date has been the ability to scale CMOS transistors.  The Nanoelectronics Research Initiative (NRI) is a consortium begun by Semiconductor Industry Association member companies to run a university-based research program to determine what will come next after the limits of CMOS scaling have been reached.  The National Institute of Standards and Technology (NIST) joined as a full participant in 2007.  NRI’s goal is to have a demonstrable solution by 2020.  The solution is supposed to show benefits in power, performance, density and/or cost in order to continue the cost and performance gains from traditional scaling.  There are four main branches of the NRI-NIST program:  Western Institute of Nanoelectronics (WIN) headed by UCLA, the Institute for Nanoelectronics Discovery and Exploration (INDEX) headed by SUNY-Albany, the SouthWest Academy for Nanoelectronics (SWAN) headed by UT-Austin, and the Midwest Institute for Nanoelectronics Discovery (MIND).

Science, technology and engineering companies have been working together to invent the next new product that we all can’t live without.  The semiconductor industry has relied on Moore’s Law to set a sustainable pace for the past 40 years.  As chips have integrated more functions, become more dense with transistors, and become available in large quantities, multiple end-product waves have been able to occur.  New technologies are being developed by groups such as NRI which promise to continue the pace of new chip introductions we have experienced so far.  Problems occur when the chips can’t meet the products’ required functionality, but that’s when other similar products can be repurposed in order to drive the eventual success of the end product.

By Adrienne Downey, Director of Technology Research, Semico Research

Danny Biran, Altera:  Device Boundaries Blur

Danny Biran, Senior VP of Marketing at Altera, discussed new opportunities as the boundaries between semiconductor logic device types become blurred.

According to Mr. Biran, the boundary between FPGAs, ASICS, ASSPS and CPUs (MPUs, MCUs and DSPs has until recently been extremely well defined.  FPGAs were customer programmable standard products.  Programming was developed for and owned by the customer.  ASICs used a standard cell design methodology.  The design was owned by the customer.  ASSPs were a standard high-volume product developed by the semiconductor vendor for sale to multiple customers.  MPUs, MCUs and DSPs were standard products, but the software needed to implement an application was developed by the customer.  Now, the boundaries between those categories are becoming blurred.

Various semiconductor vendors are offering FPGAs with an on-board MPU, ASICs that include an FPGA block or ASSPs with multiple processing cores.   Altera’s Stratix V FPGA is an example of this trend.  It combines high speed transceivers, hard IP, soft IP, logic blocks, memory arrays and advanced DSP blocks on one IC.

There are several factors driving this trend, including increasing levels of integration, the high cost of developing leading edge ASICs and the availability of IP (Intellectual Property).   Another factor is the availability of integration tools, such as Altera’s Qsys system integration tool.

There is more to the blurring of boundaries between device types than just the availability of advanced ICs.  There are a wide variety of system integration tools, intellectual property blocks, floating point IP libraries and other tools available to today’s design engineer.  This requires a fundamental change in the way that system engineers approach their tasks.

Mr. Biran made the point that system companies should not be trapped into thinking about design solutions in terms of IC categories:  FPGAs, ASICs, ASSPs or processors.  Instead, they should think about the combination of technologies that provides the best solution.  This may require reorganization or the acquisition of new skills.  For example, the emphasis might shift from standard cell design skills to programming skills. The optimum solution for a part of the design might be an FPGA.  The optimum solution for another part of the design might be an MPU or a DSP.  The significant change is that both of these, the FPGA and the processor, or other device types, can now be integrated onto one IC.

This requires another change in thinking.  In the past, a system company might begin coordinating with vendors relatively late in the design cycle.  Now, with the boundaries blurring, a system company can achieve a better solution by consulting with a vendor from the very beginning of the design cycle.

As we all know, the number of transistors per IC is increasing, in accordance with Moore’s law.  This is making it possible to combine several functionalities on one IC.  In fact, according to Mr. Biran, the record for the number of transistors on an IC is held by an FPGA, not a microprocessor.  This can lead to better design solutions, but only if system companies recognize the trend and alter their design concepts to take advantage of the possibilities,

By Morry Marshall, VP Strategic Technologies, Semico Research

Sandeep Vij, MIPS Technologies: Consumer Electronics Driving Requirments

Sandeep Vij, President and CEO of MIPS Technologies made some very interesting observations regarding Consumer electronics applications and their use of memory resources.

We all know that the feature sets and functionality of devices aimed at Consumer applications have been increasing over the last 3-4 years. This is driven by the requirements of users of these devices for OEMs to deliver ever-increasing amounts of functionality like HD quality video, video downloads, touch screens, multiple HD cameras, personal video conferencing and multiple types of integrated sensors. Future requirements will include, but are not limited to, medical sensors, 100’s if not 1000’s of apps run in the devices, 3D-HD video, etc.

These new levels of functionality must be fulfilled by placing higher levels of complexity into these silicon solutions to provide the right feature sets consumers desire. All this takes an increasing amount of resources to deliver the right user experience.

MIPS is the second largest CPU IP vendor next to ARM and is one of the first companies to see what these new levels of functionality demand in terms of the compute and system resources that must be placed into the system. The message here is that as the demand for compute power increases so to must the resources to service the new performance levels increase.

In the case of Consumer devices, this is prompting a move to 64-bit CPU cores geared to deliver much higher performance to meet the much higher levels of complexity in these devices. However, that is not the end of the story since memory is one of the primary system resources that computing power requires to function efficiently. The reality is now that memory densities must also increase, moving beyond 1GB and approaching 4GB and even 8GB in some cases. This will put added emphasis on embedded memory IP vendors and even discrete memory vendors to reduce power consumption to the lowest possible levels while still providing the right mix of density and performance to the CPU elements in the system.

It is Semico’s view that, even though system OEMs will not like to hear the news that memory densities are going to increase in next generation Consumer devices, it is probably an inescapable conclusion that they must do so if they are to provide the right level of functionality to meet consumer requirements.

It is our belief MIPS is very prescient in pointing out this trend and is demonstrating a leadership role in creating solutions to deliver the right mix of compute performance and functionality to meet the challenge of these next generation applications. Their move to introduce 64-bit, multi-threading and multicore CPU cores is in answer to the market needs that are just emerging and provides ample evidence that MIPS is one of the premier CPU IP companies in the world today.

By Rich Wawrzyniak, senior analysts, Semico Research

Moshe Gavrielov, Xilinx: FPGAs a Fast Moving Sector

Tthe CEO of Xilinx Corporation, Moshe Gavrielov, delivered a presentation on developments in the Programmable Logic market.

Gavrielov made several points: Today, FPGA companies are usually the first to move to doing designs on cutting edge process geometries.

• Large ASIC and SoC development costs have cut down on the willingness of Venture Capitalists to invest in new, start-up companies since they need ever larger investments just to deliver their first products to market cutting down on the VC’s returns.
• It is possible today to acquire a 20M gate, ARM-based SoC with multiple, high bandwidth SerDes channels that incorporates $2.00 to $7.00 worth of Mixed Signal functionality: all for around $15.00 in volume. That part just happens to be an FPGA from Xilinx. In essence, a SoC with a programmable fabric built around it.

This last point is perhaps the most surprising in that, for the first time, an FPGA company would refer to one of its products as a SoC with programmability and not as a programmable logic part with some SoC-like functions included. In Semico’s opinion this has been prompted by the unrelenting march of many end markets towards requiring higher levels of complexity and the demands of the users of products aimed at those markets for better, richer user experiences.

As the old adage says, “it takes more to do more.”

The FPGA market, and specifically Xilinx, has taken this to heart in the creation of new families of products that deliver much higher capability at the 28nm process node with a corresponding minimal increase in cost structure than in previous generations.

Semico believes the main message to be taken from all this evolution is that FPGAs are leading the way towards delivering new levels of functionality at reasonable price points and thus opening the door for a host of new applications to surface in the markets. This is something sorely needed as development costs approach and exceed $100M for complex, first time efforts at the 28nm node and below.

The semiconductor industry is built on three basic premises: the development of amazing technology, the ability to turn the amazing technology into products we all want and can afford and the creation of even more new applications based off of the amazing technology, all to drive continued development of the amazing technology we all crave. Xilinx, and others, have met the challenges of these premises and are delivering great, timely products that are creating new demand and enabling new applications over the mid-term.

By Rich Wawrzyniak

Len Perham, MoSys: The GigaChip Interface

Len Perham CEO, MoSys, Inc. discussed looming problems in the processing of Internet traffic and offered a solution.

According to Mr. Perham, Internet traffic will increase exponentially over the next three years, driven by applications such as video streaming, IPTV, P2P, cloud computing, social networking and VoIP + video.  Today’s traffic routing methods will not be able to keep up with that growth, and memory is the bottleneck.  The problem is that today’s 40Gbps and 100Gbps packet processor line cards address memory on parallel connections, which will not be adequate at faster speeds beyond 100Gbps.  Routing data at those speeds will require a serial connection to the memory, not a parallel connection.

MoSys has developed the GigaChip™ Interface, which is now an open standard supported by the GigaChip Alliance.  The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance.   It provides a fundamental performance breakthrough similar to the breakthrough achieved by DDR (Double Data Rate) DRAM.   The GigaChip Interface, using differential SerDes technology, is the next breakthrough in network processor to memory connections.  It allows a multiple-processor network processor to address multi-bank, multi-partitioned memory, so that each processor has access to memory without waiting.

Mr. Perham also discussed the advantages offered by 1T-SRAM®, a memory architecture originally invented by MoSys .  1T-SRAM has the approximately the same latency as the standard  6T SRAM cell generally used in today’s high speed applications, but because it has one transistor per cell as opposed to six per cell for standard SRAM’s the ultimate memory area is approximately one third that of the standard SRAM.     The MoSys Bandwidth Engine® IC Roadmap anticipates a BE-3, utilizing the 1T-SRAM architecture, which will have a memory capacity of 1Gb and an access speed of 7.4Gbs.

Memory access has been a continuing problem for network processors over the past several years as Web traffic has increased, requiring ever faster processing speed.  Various schemes have been used to speed up access times on parallel interfaces.  Now, parallel access appears to have run out of steam.  Serial access, using the GigaChip standard shows promise as a solution going forward.  The 1T SRAM may have found a home in this application, an applications that needs the 1T SRAM’s unique combination of access speed, high density and low power.

By Morry Marshall

Joe Sawicki, Mentor Graphics: Dual Paths Down the Cost Curve: Scaling and 3D

Joe Sawicki, VP and GM of the Design-to-Silicon Division for Mentor Graphics, joined us at the Semico Summit on Tuesday to discuss scaling and the conversion to 3D.  He focused on a motto of “Willful Optimism” for the future.

Moore’s Law has been a cornerstone of our industry for 40 years, and a trend the speakers at the 2011 Summit were discussing was “More than Moore,” an idea that we are moving away from density to integration.  Joe Sawicki addressed this idea by discussing how scaling can only get us so far with advancing our speed and storage capabilities.  By 2026, he said, if we hold to Moore’s Law, we’ll be holding half a year’s movie collection on our phone.

In the future, Mentor Graphics believes we may be seeing the “e-Cube,” where we’ll have cubes of semiconductors instead of a die.

In discussing transitioning to 3D, there are cost and thermal issues, regardless of the advantages.  As a stepping stone, the industry can obtain many of the advantages of 3D by using 2.5D, a cost effective method to swing into the next generation.

For Mentor Graphics, the question becomes how ICs will be created in the future to continue the advancements we’ve seen under the last 40 years with Moore’s Law – and they have some interesting ideas on how to get there – but we’ll need standards to accomplish their innovative ideas.

By Michell Prunty, Consumer Analyst

By David Lammers

Any full recovery for Japan’s semiconductor industry will have to deal with Japan’s bifurcated power transmission network. In the eastern half of the country, including metropolitan Tokyo, power is sent at 50 hertz, while in the western half, where many of the larger chip fabs are located, electricity moves along transmission lines at 60 Hz.

There is a limited amount of conversion capability to transfer power from the western half, which often has a surplus of power, to the eastern half, which includes the 25 million people who live in the world’s most-populated metropolitan area: Tokyo.

Power transmission is further complicated by the presence of nine different electric power companies, which have agreements to share power in times of surplus or need. In the case of the stricken Fukushima Daiichi (No. 1) nuclear power facility, owned by Tokyo Electric Power Co. (TEPCO), the power generated there does not serve the nearby towns and cities of northeast Japan, known as the Tohoku region. Power from TEPCO moves down to greater Tokyo, while it is Tohoku Electric Power Co. which provides power to cities near the quake-ravaged area: Sendai, Fukushima, Aizu-Wakamatsu, and others.

While that may prove to be a blessing for the semiconductor fabs, equipment, and materials companies operating northeast of Tokyo, the disaster at the Fukushima facility makes the job of restoring regular power to Tokyo all the more difficult.

Tokyo and its surrounding environs is not where manufacturing gets done, by and large. Most large chip fabs are west of Tokyo, or far south in Kyushu. Nevertheless, Japan’s business and financial communities are centered in Tokyo, and any full recovery of business in Japan depends on people in Tokyo being able to ride (electrically powered) trains to work and back home, operate computers and other equipment, and manage factories in far-flung locations around the world.

Reliable Three-Phase Power

Andy Beers, principal at ABM Consulting (Austin), said semiconductor fabs need “reliable three-phase power, especially to run implanters and diffusion equipment. Those tools take a lot of power, and any time you have a power burp diffusion wafers have to be scrapped.”

Fabs suffer from power outages in myriad ways. The air handling equipment can go down when power is unreliable, putting particles into the fab, Beers said.

Materials suppliers face even bigger challenges. If power goes down at a chemical plant, Beers said, the results can be disastrous, ranging from ruined batches to explosions. “There are gas and fire risks when power goes down. The recovery of Japan’s whole material supply chain is a wild card, and power is a big factor.”

Beers said he believes the March 11 earthquake and tsunami , which occurred relatively near the Freescale Sendai fab (a former joint venture between Toshiba and Freescale), could result in that 6-inch fab not re-opening. Freescale announced last year that the Sendai fab would close by the end of this year, and the accelerometers and other products made at Freescale Sendai are in the process of being transitioned to Freescale’s MOS 11 fab in the Oak Hill section of Austin.  “Sendai was on high enough ground that there was no flooding. But still, this may hasten its closure,” Beers said.

Among all chipmakers, Texas Instruments may face the greatest challenges from the May 11 quake, Beers said. Not only was the TI Miho fab damaged, but TI will face delays in ramping production at a 200-mm fab purchased from Spansion Inc. last year.

TI plans to make analog and other products at the Aizu-Wakamatsu 200-mm fab, using it to complement production at TI’s DMOS 5 fab in Dallas, Beers said. Those plans will go forward but may see some delays, Beers said. TI also owns a 300-mm fab at Aizu-Wakamatsu that it bought from Spansion, and is in the process of transferring production equipment from the former Spansion 300-mm facility to the TI “R Fab” in Richardson, Texas, a 300 mm facility dedicated to analog production.