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Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015


By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types. (Source: Mentor Graphics)

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how data can move through the supply chain. (Source: Texas Instruments)

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.


Design and Manufacturing Technology Development in Future IC Foundries

Tuesday, September 16th, 2014


By Ed Korczynski, Sr. Technical Editor

Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem

Q1:  The fabless-foundry relationship in commercial IC manufacturing was established during an era of fab technology predictability—clear litho roadmaps for smaller and cheaper devices—but the future of fab technology seems unpredictable. The complexity which must be managed by a fabless company has already increased to justify leaders such as Apple or Qualcomm investing in technology R&D with foundries and with EDA- and OEM-companies. With manufacturing process technology integrating more materials with ever smaller nodes, how do we manage such complexity?

ANSWER:  Gregg Bartlett, Senior Vice President, Product Management, GLOBALFOUNDRIES

The vast majority of Integrated Device Manufacturers (IDMs) have either gone completely fabless or partnered with foundries for their leading-edge technology needs instead of making the huge investments necessary to keep pace with technology. The foundry opportunity is increasingly concentrated at the leading edge; this segment is expected to drive 60 percent of the total foundry market by 2016, representing a total of $27.5 billion. Yet there are fewer high-volume manufacturers that have the capabilities to offer leading-edge technologies beyond 28nm, even as the major companies have accelerated their technology roadmaps at 20nm and 14nm and added new device architectures.

This has led to a global capacity challenge. Leading-edge fabs are more expensive and fewer than ever. At the 130nm node, the cost to build a fab was just over $1B. For a 28nm fab, the cost is about $6B and a 14nm fab is nearly $10B. Technology development costs are rising at a similar rate, growing from a few $10M’s  at 130nm to several $100M’s at 28nm.

On top of these technology and manufacturing challenges, product life cycles are shrinking and end users are expecting more and more from their devices in terms of performance, power-efficiency, and features. Competing on manufacturing expertise alone is no longer a viable strategy in today’s semiconductor industry, and solutions developed in isolation are not adequate. The industry must work closer across all levels of the supply chain to understand these dynamics and how they put demands on the silicon chip.

Fortunately, the fabless/foundry model is evolving to accommodate these changing dynamics. We have been promoting this idea for years with what we like to call “Foundry 2.0.” In the 1970s/1980s, the industry was dominated by the IDM. Then the foundry model was invented and grew to prominence in the 1990s and early 2000s, but it was much more of a contract manufacturing model. A fabless company developed a design in isolation and then “threw it over the wall” to the foundry for manufacturing. There was not much need for interplay between the two companies. Of course, as technology complexity has increased in the past decade, this dynamic has changed dramatically. We have entered the era of collaborative device manufacturing. Collaboration is a buzz word that gets thrown around a lot, but today it really is critical and it needs to happen across all vectors, including design flow development, manufacturing supply chain, and customer engagement.

Q2:  3D in packaging started with wire-bonded-chip-stacks and now includes silicon-interposers (a.k.a. “2.5D”) and the memory-cube using through-silicon via (TSV). How about the complexity of 3D products using chip-package co-design, and many players in the ecosystem being needed hroughout design-ramp-HVM?

ANSWER:  Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Silicon Systems Group of Applied Materials

Enabling 3D requires the participation of the extended ecosystem. These include contributions from CAD, design tools for die architecture, floor plan, and layout circuit design test structures, as well as methodology wafer level process equipment and materials, wafer-level test assembly and packaging stacked die and package level testing.

Q3:  Due to challenges with lithographic scaling below 45nm half-pitch, how does the need to integrate new materials and device structures change the fabless-foundry relationship? How much of fully-depleted channels using SOI wafers and/or finFETs, followed by alternate channels can the industry afford without commited damand from IDMs and major fabless players for specific variants?

ANSWER:  Adam Brand, Director of Transistor Technology, Silicon Systems Group of Applied Materials

New materials and device structures are going to play a key role in advancing the technology to the next several nodes.

With EUV delayed, multi-patterning is growing in use, and new materials are enabling the sophisticated and precise extension of multi-patterning to the 7nm node and beyond.  The multi-patterning schemes however bring specific restrictions on layout which will affect the design process.

For device structures, Epi in particular is going to enable the next generation of complex device designs with improved mobility and by supporting very thin precisely defined channel structures to scale to smaller gate length and pitch. For these next generation devices, the R&D challenges will be high, but the industry cannot afford to skimp on R&D to find the winning solution to the low power transistor technology required for the 7nm and 5nm and beyond nodes.

Q4:  Mobile consumer devices now seem to drive the leading edge of demand for many ICs. However, the Internet-of-Things (IoT) is often spoken of needing just 65nm node chips to keep costs as low as possible, and these designs are expected to run in high volume for many years. How will these different devices that will continue to evolve in different ways get integrated together?

ANSWER: Michael Buehler-Garcia, Senior Director of Marketing, Calibre Design Solutions of Mentor Graphics

IOT has become the new industry buzz word.  What it has done is spotlight the multiple elements of a complete solution that do not require emerging process technologies for their chip design. Moreover, while a chip may use a well established process node, the actual design may be very complex. For example Mentor is participating in the German RESCAR program to increase the reliability of automotive electronics using our Calibre PERC solution. The initial reliability checks written are targeted for 180nm and older process nodes. Why? Because today’s 180nm and older node designs are much more complex than when these nodes were mainstream digital nodes and as such require more advanced verification solutions. Bottom line:  as opposed to a strategy of only moving to the next process node, chip design companies today have multiple options.  It is up to the ecosystem to provide solutions that allow the designers be able to make trade-offs without major changes in their design flows.

FIGURE: Reliability simulation as part of “RESCAR” program. (Source: Fraunhofer IZM)

Blog Review: November 25, 2013

Monday, November 25th, 2013

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs about a recent announcement by Intel CEO Brian Krzanich on company expansion focused on a foundry plan. Or-Bach said that if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of the other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

Vivek Bakshi, EUV Litho, Inc. reports on work presented at the 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland), including data on the readiness of 50 W EUV sources to support EUVL scanners. At the meeting, keynoter Vadim Banine of ASML said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field. ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

At the GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Phil Garrou reports on the workshop, including presentations from Ron Huemoeller of Amkor and David McCann of GLOBALFOUNDRIES.

Pete Singer provides a preview of a special focus session at the upcoming IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013. The session covers many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Dr. Lianfeng Yang of ProPlus Design Solutions, Inc., blogs that these days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

From SEMICON West 2013: Paul Boudre of Soitec

Thursday, October 24th, 2013
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Soitec’s COO Paul Boudre talks about the competitiveness of full-depleted planar with full-depleted finfet; capacity issues for SOI in light of ST’s open foundry model; and growth of High Resistivity SOI in the RF implementation on smart phones.

Solid State Watch: September 27-October 3

Friday, October 4th, 2013
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Forecast for 2013

Saturday, December 1st, 2012

By Pete Singer

Nobody can predict the future, of course, but 2013 is shaping up to be a good year for the semiconductor industry and its suppliers. According to SEMI, total fab spending for equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size could increase 16.7 percent in 2013 to reach a new record high of $42.7 billion. The estimate includes new equipment, used equipment, or in-house equipment but excludes test assembly and packaging equipment (which, if included, would bring the number up to about $50 billion). The market for semiconductor manufacturing materials, which was $48.6 billion this year, is expected to grow 4% to more than $50 billion in $2013.

There’s been some hand-wringing in 2012 about continued consolidation and the number of companies that will be moving to 450mm: most pundits guess that only 5-7 companies will be able to make the move. However, that’s a limited view of the industry, since there are hundreds of facilities around the world cranking out chips, LEDs, optoelectronics, power devices, MEMS and other components. The latest edition of the SEMI World Fab Forecast lists over 1,150 facilities (including 300 opto/LED facilities), with 76 facilities starting production in 2012 and in the near future.

There’s sure to be much talk in 2013 about technology requirements at the leading edge, including the 450mm transition, progress in EUV, 3D integration and FinFET optimization. Sustainability will be key, with an emphasis on reducing power consumption, which means lower leakage currents and reduced Vdd.

The demand for semiconductors will never be higher, particularly as the middle class rise on dominance in places such as Brazil, Russia, India and China. First on the wish list it seems, after shelter, food and clothing, is a smart phone.
After a trip to imec in Leuven, Belgium, I’m particularly bullish on opportunities in healthcare, which range from body area sensor networks to amazingly advanced labs-on-a-chip that can screen 20 million blood cells per second to find a single tumor cell in 5 billion blood cells. It is these kinds of applications that could lead to a new revolution in how electronics are designed and manufactured.

IEDM Preview: 20nm and Below

Sunday, November 11th, 2012

By Pete Singer

As the industry works to perfect 28nm devices in volume manufacturing and early 20nm processes, attention is focusing on next-generation 14nm and below technologies.

There have been three primary drivers in the semiconductor industry for the last four decades: Area, power/performance and cost. The well-known push to cram more functionality onto a single chip through continued scaling — or into a single package through 3D integration and other advanced packaging techniques — has been well documented. Today, with the exception of Intel, the industry’s leading edge devices in high volume manufacturing have critical dimensions of 28nm. Intel, racing ahead, introduced the 22nm IvyBridge chip in 2011 and has announced plans to have 14nm by the end of 2013. How long this kind of scaling can continue is the subject of some debate, with most recognizing the EUV lithography will be required at some point, most likely for the 10nm generation (Intel has said it doesn’t need it for 14nm).

It’s clear, though, that continued scaling is running out of steam, and that the industry most look for other means by which to say on the path defined by the proverbial “Moore’s Law.” Those advances are one of the primary focal points of the upcoming 58th annual IEEE International Electron Devices Meeting (IEDM), which will take place December 10-12, 2012 at the San Francisco Hilton Union Square. The conference will be preceded by a day of short courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.
As reported in last month’s issue, highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to ever smaller sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

Following, we’ve assembled a list of the “be sure not to miss” papers and sessions slated for IEDM 2012.

Invited papers

In the plenary session, imec’s Luc Van den hove, will describe how ultimate transistor and memory technologies are the core of a sustainable society. He says that several key societal challenges in domains such as healthcare, energy, urbanization and mobility call for sustainable solutions that can be enabled by combining various technologies. These solutions will be backboned by wireless sensor systems, smart mobile devices and huge data centers and servers, the key constituents of a new information universe. They will require extreme computation and storage capabilities, bound by (ultra)low-power or heat dissipation constraints, depending on the application. This drives the need, he says, to keep on scaling transistor technologies by tuning the three technology knobs: power/performance, area and cost. To get to ultra-small dimensions, advanced patterning integration, new materials such as high-mobility Ge and III-V materials, and new device architectures such as fully depleted devices are being introduced. This comes along with an increasing need for process complexity reduction and variability control. Equally important are the continued R&D efforts in scaling memory technologies. NAND Flash, DRAM and SRAM memories are now approaching the point where new scaling constraints force exploration of new materials, cell architectures and even new memory concepts. This opens opportunities for resistance based memories such as resistive RAM, phase-change RAM or spin-torque transfer magneto resistive RAM.

In another invited paper, in the regular sessions, researchers from Micron and Intel will discuss scaling directions for 2D and 3D NAND Cells. They note that many 2D NAND scaling challenges are addressed by a planar floating gate (FG) cell, which has a smaller aspect ratio and less cell to cell interference. Figure 1 compares a wrap FG cell (left) and a planar FG cell (right). The wrap cell is limited by a required aspect ratio of >10 for both the wordline and the bitline direction in a sub-20nm cell. The planar cell eliminates this limitation.

Of course, not all IEDM presentations are focused on leading-edge logic and memory. In the plenary session, John Rogers from the University of Illinois at Urbana-Champaign, will talk on bio-integrated electronics. He notes that biology is curved, soft and elastic, while silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. He plans to cover ideas for electronics, sensors and actuators that offer the performance of state-of-the-art, wafer-based systems but with the “mechanical properties of a rubber band.” He’ll explains the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ’tissue-like’ devices with unique diagnostic and therapeutic capabilities, when conformally laminated onto the heart, brain or skin.In the third plenary talk, Joo-Tae Moon of Samsung Display will give a talk titled “State of the Art and Future Prospects in Display Technologies.” There are two parts which satisfy this vision, he notes. One is the picture quality and the other is design of the display. From picture quality point of view, bigger screen size and higher pixel density are the main factors. The need for a bigger screen size requires expediting technologies with lower RC delay and higher transistor performance. Higher pixel density mandates a smaller unit pixel area and each unit pixel has the dead space for the transistor and metal line which is protected from the light by the black matrix. Clearly, the design factor is the one of the main driving forces for the changes from CRT era to flat panel display era, he says.

Notable papers

imec, in a paper titled “Ultra Thin Hybrid Floating Gate and High-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology,” will describe — for the first time — a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. Figure 2 is a TEM image of a polysilicon/TiN HFG cell. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al2O3) and an n-type polysilicon CG.

In a paper jointly authored by GLOBALFOUNDRIES and Samsung, titled “Stress Simulations for Optimal Mobility Group IV p- and n-MOS FinFETs for the 14 nm Node and Beyond,” researchers provide calculations of stress enhanced mobilities for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond. Results indicate that both for nFETs and pFETs, Ge is “very interesting,” provided the correct stressors are used to boost mobility. Figure 3 is a XTEM of a Ge-channel FET with SiGe source/drain. They conclude that strained channels grown on a strain relaxed buffer is effective for 14nm nodes and scalable to future nodes. TCAD simulation trends are experimentally confirmed by nano-beam diffraction (NBD).

Luncheon presentation

Ajit Manocha, CEO, GLOBALFOUNDRIES, Inc. is sure to provide an interesting luncheon talk on Tuesday, December 11th, addressing some recent jabs from Intel’s Mark Bohr. The title of Manocha’s talk: “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!”

Manocha says that industry experts and observers have predicted for a long time that the fabless model has some cracks in it, and may in fact be headed for extinction at some point. “We in the foundry industry dismissed such chatter as we continue to enjoy growth rates that outpace the overall semiconductor industry,” he notes in his pre-conference abstract. “But it wasn’t until an executive from — surprise — Intel officially declared the fabless model is collapsing recently that many of us really got our feathers ruffled. We firmly believe that the rumors of its death are greatly exaggerated. Evidence would seem to support that it is actually the IDM model which is dead, survived only by a very small number of anomalies that have either the financial wherewithal or stubbornness to continue down this path.”

The foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together, says Manocha. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy. Recent talks of fabless companies investing in their own fabs, and of foundries developing single company fabs’ underscore the sense of urgency. “Clearly, we must change – Call it Foundry 2.0,” he says.

Unprecedented technical and business challenges have driven semiconductor manufacturing to this new fork in the road. On the one side is the option to ‘go it alone’, an option available to less than a handful of companies. The temptation here is to circle the wagons, dig deep into the bank and develop an optimized, but relatively closed, solution that will hopefully work for most every need. Manocha said a second option, ironically, is a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies. “With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration ‘early, often and deep’ is really the only practical approach given the cost and complexities involved,” he said.

Evening panel

One of the two evening panels on Tuesday at 8pm is titled “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” The moderator will be Suresh Venkatesan of GLOBALFOUNDRIES. He notes that the 22nm node spelled the dawn of the fullly-depleted device architecture with the implementation of FinFETs as the workhorse of the technology. However, projecting out to the 10nm node and beyond the scalability of the FinFET architecture, the materials systems used to create it, and the fundamental electrostatics and parasitic components associated with the transistor once again loom large as significant challenges that need to be overcome.

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