By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: What does hybrid metrology accomplish in the process control flow?
Allgair: The structures are becoming so complex. You are trying to measure a particular application on a 3D device, where you have a lot of variations that already took place prior to the measurement step. Hybrid is one of the ways to address that challenge. For us, it enables us to use a lot of the information that is collected upstream for the measurement event you are actually doing. It allows us to understand, as much as we can, about the structure in terms of how it was processed and what it looks like prior to that measurement step. And then, for the variables you are trying to measure, it helps reduce some of the uncertainty of those variables you may not understand from that particular process step you are measuring. Again, that information can be thickness, compositional and CD.

SMD: Do you think directed self-assembly (DSA) will succeed? And does the industry have an inspection/metrology solution for DSA?
Allgair: As we keep driving litho, there is a decent chance that DSA will happen. We will probably try to postpone it as long as we can, and try and get through what we’re currently using. When it does happen, it may end up being a different type of solution than we thought. After SPIE, and looking at one of the papers from MIT, it looks like there might be a way to measure the structures that were used to pattern your DSA. It might be that we monitor that structure. Then, we will have some confidence that the DSA activity takes place and works. All told, if we can get a DSA system that works well, and there is a cost advantage to it, that could drive an earlier adoption for DSA. That is a big component to DSA.
Heidrich: We certainly see the promises. The cost reduction is there, but the challenges of proving low defectivity and performance still remain. Certainly, in the case of memory and related types of processes, where you have redundancy, DSA will get adopted earlier. There has been work on contact holes, where you can do reduction with DSA. When the yield is proven, and if the cost benefit is there, DSA will get adopted. But I think that is still quite a few years away.
Newcomb: DSA is just one of the options available. We have all been in the industry long enough to know there are multiple options. But DSA is the one you want to try to avoid as long as possible because there are many unique challenges. Will it happen? Maybe not. If it does, you have to put all of the pieces together to bring it into high volume production. The challenge comes down to defectivity and integration.
Shetty: DSA is exciting. DSA will most likely happen, but cost would be the biggest challenge in terms of making it production-worthy.

SMD: The industry is in need of new inspection/metrology breakthroughs and tools. Do you agree? And how does the industry fund the development of new tools when there are not enough R&D dollars?
Allgair: It is apparent that we have a need for some new techniques. The ones we’ve talked about are multi-beam e-beam inspection, CD-SAXS, helium ion and a higher resolution CD tool. These are addressing defect-inspection resolution, CD resolution, scatterometry and compositional analysis. The problem that we are trying to grasp is the people that use these new tools are the ones on the leading edge. Those are for devices at 14nm and beyond. There are not a lot of companies in that space. So, it’s not clear how many tools would get ordered at the leading edge. And the other problem is chipmakers like GlobalFoundries, Intel and others may not have provided a clear and concise message in terms of what our future tool needs are to the toolmakers. Regarding GlobalFoundries, as well as my peers at Intel, TSMC and others, we all need to get a little better organized in terms of defining our problem statement to the tool vendors. The second piece is how do you fund a new tool development program? That one is challenging. We’ve seen other funding models, where we have joined other companies and put money together to drive the development of a new tool in litho or to drive a consortium. It’s possible that chipmakers can get together and try to drive something along that line. Another possibility is that each customer could buy the first generation of new tools from vendors. That might be enough for suppliers, who can then seek funding on their own.
Heidrich: We see two things that are challenging from the R&D point of view. One is the rapid consolidation from our end-customer base. We have fewer than a dozen major customers left. In the near- or long-term, that number will likely get smaller. So you have to have fewer customers to absorb the R&D for all the products you need to develop. Secondly, we have very diverse and complex process flows that different customers are adopting. This could be a finFET flow, vertical memory flow, or a 3D device integration flow. So you have more demands on your R&D. Right now, we need to make sure the R&D dollars solve the hard problems and we leverage that learning across all the different end customers. What that means is that if someone has a unique challenge, it gets harder and harder to provide a custom solution.

SMD: What about VC-backed startups like Qcept?
Newcomb: If you go way back, the industry had lots of startups. You had tier-one customers of course, but you also had a plethora of tier-two and tier-three fabs in the world. Now, as an equipment maker, you are not going to get funding that easily, because there are maybe 12 or less major customers in the world. It also takes more money to develop products. The dynamics are also different. You have new memory and logic requirements. We are tying together the OSATs and fabs with 3D TSV integration. In addition, the industry is moving towards two major suppliers on the equipment side and a handful of customers on the device side. That dynamic makes it very difficult. The big challenge is how will the industry keep investing and address those types of needs?

SMD: What’s the solution to this problem?
Newcomb: In one possible solution, companies on the device side could pre-buy the technology rights to the first tool to help fund some of the required investment and R&D. Or maybe, we can better integrate the university work into a model that can be funded and driven into the industry to solve a problem.
Shetty: R&D is becoming expensive. The device nodes are shrinking quickly. And customers’ expectations are increasing. Across the industry, everyone is pushing to get a lower cost-of-ownership and higher productivity. That’s just a fact of life. There are maybe 12 customers out there. But between the joint ventures and consortia, there are maybe four or five R&D centers out there. Today, it is very important that you are involved with these R&D fabs very early in the process. Then, the tool evolves with the process. So when customers move into production, the tool is already mature and ready to go. On the other hand, the devices are changing so much. And in a lot of cases, the customers themselves don’t know what’s going to happen.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
Altera has entered into an agreement for the future manufacturing of its FPGAs based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant. That puts the processor giant on a collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC

The Altera-Intel deal could change the landscape in the foundry business, in which Intel will likely become a much bigger player in the arena. But does Intel have staying power to remain in the foundry business? Added John Vinh, an analyst from Pacific Crest Securities: Altera’s “foundry agreement with Intel is exclusive for the foreseeable future. We believe Altera will have exclusive access versus Xilinx at 14nm and effectively have the right of first refusal at 10nm. Strategically, we believe this is likely the most significant aspect of this agreement in that it prevents Xilinx from having access.”

At SPIE, ASML Holding disclosed various milestones with its extreme ultraviolet (EUV) lithography technology. ASML’s EUV production tool, dubbed the NXE:3300B, has demonstrated resolutions of 13nm for lines and spaces and 18nm contact holes. In addition, ASML demonstrated a 40-Watt source with dose control and under good collector protection conditions in six 1-hour runs. It also demonstrated a 55-Watt source in a 1 hour run. But that’s a far cry from the eventual goal. By 2015, ASML hopes to deliver a 250-Watt source for the NXE:3300B, thereby enabling a throughput of 126 wafers an hour.

With the help of self-aligned double patterning (SADP), sometimes called spacer, ASML’s NXE:3300B also demonstrated the ability to print lines and spaces down to 9nm. The work was done in conjunction with ASML, Applied Materials and Imec.

At the International Semiconductor Strategy Symposium in Europe (ISS Europe) on Feb. 24-26, the European semiconductor industry discussed 450mm fabs and other chip topics. In addition, European Commissioner Neelie Kroes floated the idea of creating an “Airbus for chips,” a European initiative for the semiconductor industry comparable to the launch of the Airbus in the aviation industry.

Also at ISS Europe, Malcolm Penn, chairman and CEO of Future Horizons, said that the decline of the major European chip makers has been a result of a defeatist attitude, not necessarily fundamental structural issues. He suggests European chip makers should build a 450mm fab jointly and operate it as a foundry.

SEMI has announced the release of “Global Trade War and Peace: Unified Approaches to a Global Solar Energy Solution,” a white paper containing recommendations to move beyond trade litigation and encourage an accelerated path towards dispute resolution.

In case your calendar has turned into a blur, take note: Semicon is near! SEMI, in collaboration with leading investment groups, has announced the Silicon Innovation Forum (SIF). The forum will bridge funding gaps for new and early-stage companies with manufacturing and technology solutions. SIF will be held in conjunction with Semicon West, on July 9 at the Moscone Center in San Francisco.

At the Mobile World Congress in Barcelona, Peregrine Semiconductor rolled out its latest version of its UltraCMOS process technology, dubbed Semiconductor Technology Platform 8 (STeP8). UltraCMOS is a variant of silicon-on-insulator (SOI) technology called silicon-on-sapphire (SoS).

Also in Spain, Skyworks Solutions said it is ramping several antenna-tuning products with leading smartphone manufacturers. The tuning devices are based on SOI technology.

The RATP Group, the fifth-largest urban transport operator worldwide, has awarded Soitec and Philips/Step an LED lighting contract for its metro and network stations.

Soitec and Medina College of Technology have signed a cooperative agreement for concentrating photovoltaic technology in Saudi Arabia.

GT Advanced Technologies has entered into a development and licensing agreement with Soitec to develop and commercialize a hydride vapor phase epitaxy (HVPE) system for producing GaN template substrates.

Mentor Graphics announced record financial results for the company’s fiscal fourth quarter and year ended Jan. 31.

During a conference call, Walden Rhines, chairman and CEO of Mentor, said the quarter was an all-time revenue and EPS record. Rhines also has a mixed forecast for the overall IC industry in 2013. “For next year, the analysts project mid-single-digit growth, but the general attitude is less positive,” he said.

Mentor Graphics rolled out the Kronos Cell Characterization and Analysis platform.

A blogger discusses Applied Materials, saying the company is at the cyclical trough and its prospects should improve with an increase in equipment spending.

Applied Materials announced that Bob Halliday has been named senior vice president and chief financial officer. Halliday previously was executive vice president and chief financial officer of Varian Semiconductor Equipment Associates prior to Applied’s acquisition of the company in November 2011.

Micron Technology announced the Tokyo District Court’s issuance of an order approving Elpida’s plan of reorganization. Elpida’s plan of reorganization calls for Micron to acquire Elpida. In addition, mixed-signal foundry specialist LFoundry has acquired Micron’s fab in Italy.

Whatever happened to Conexant Systems? The chipmaker recently went private to avoid a takeover. Now, the company this week implemented a restructuring agreement. As part of the plan, Conexant voluntarily filed protection under Chapter 11 of the United States Bankruptcy Code.

Photomask maker Photronics has announced its intent to acquire the shares of its majority-owned Taiwan subsidiary, PSMC.

After a loss and a proxy battle, Aetrium is considering options that may include a sale or other disposition of one or both of its reliability test and test handler product groups.

According to IHS, the competitive landscape of the cell-phone integrated circuits business has completely transformed over the past five years, with Qualcomm and Samsung capitalizing on the rise of smartphones and 4G.

By Mark LaPedus
The ongoing push towards green and energy-efficient systems is prompting the silicon foundries to jump on the bandwagon and devise their next-generation processes based on ultra-high voltage technology.

For some time, several foundries have offered 1- and 0.5-micron, ultra-high voltage processes with ratings up to 800 volts. But seeking to get a jump for the next wave of designs, the specialty foundries have taken a narrow lead in the process race over the larger players like GlobalFoundries, TSMC and UMC.

South Korea’s Dongbu HiTek and Germany’s X-Fab Silicon Foundries AG recently rolled out 0.35-micron processes with ratings at 700 volts as a means to reduce cost and power. X-Fab, for one, has moved from a 1-micron silicon-on-insulator (SOI) process to a 0.35-micron bulk technology, although the company is developing a 0.18-micron SOI scheme for 200 volt applications.

The other foundries also are working on ultra-high voltage processes at 0.35-micron and below. Ultra-high voltage processes fall into the broad category of power management and generally involve technologies from 600 volts and above. In the 600 to 800 volt segment, there is also an emerging collision course for various transistor types.

The main applications for 600 to 800 volts include AC-to-DC switching power supplies, LED lighting systems and power converters. For these systems, the market is migrating towards 0.35-micron geometries on 200mm wafers, said Thomas Hartung, vice president of marketing for X-Fab. “For analog and mixed-signal companies, we see 0.35-micron as the sweet spot,” Hartung said.

The shift towards 0.35-micron processes is expected to lower the manufacturing and product costs for systems. But the real problem has been evident for some time: How does the industry reduce or tame standby power?

In the home, for example, power supplies take AC power from a wall outlet and convert it into DC. Conventional power supplies based on older linear technology are cheap but inefficient. Appliances plugged into the wall still consume energy, or standby power, even when the product is not in use. Linear-based cell-phone chargers, for example, can consume between 0.8 to 2 Watts even when they are not connected to the phone, according to chipmaker Power Integrations Inc.

Some 5% to 15% of household electricity consumption worldwide is wasted in standby mode, according to the International Energy Agency. In the U.S. alone, standby power costs households over $5 billion in electricity a year, according to Lawrence Berkeley National Lab.

One solution to the problem is the advent of switch-mode power supplies, which are generally more efficient and expensive. For switching power supplies, the goal is to reduce costs through IC integration and finer geometries. The concept is similar for fly-back converters in LED lighting systems.

In these segments, power management chips are specified to withstand breakdown voltages at 600 volts in the event of a power surge or spike. Some vendors sell integrated power management devices at 725 volts. “You want your transistors (with ratings of at least) 600 volts to operate in the 220 AC range,” said Steve Ohr, an analyst with Gartner Inc. “You want to have tolerances at 600 volts to prevent the system from failing.”

The prevalent switching technology in these types of systems is the power MOSFET. But there are big changes within the 600 volt segment, as several transistor types are emerging in the arena. “At 600 volts, you will see a clash of the titans between a range of technologies,” Ohr said. “You will see IGBTs, bipolar, power MOSFETs, gallium-nitride (GaN) FETs, and silicon-carbide transistors.”

Foundries push ultra-high voltage
On the foundry front, there are more subtle changes taking place in the arena. In digital, most integrated device manufacturers (IDMs) have outsourced a growing percentage of their production to the foundries. In contrast, the power management IDMs tend to keep their production in-house and the foundry business is relatively smaller for high-voltage devices right now, said Robert Lineback, an analyst with IC Insights.

Still, the foundries are seeing gradual growth from an emerging crop of fabless vendors in the higher voltage segments. “For TowerJazz, 700 volts makes up approximately 20% of new power designs,” said Todd Mahlen, vice president of APAC sales and power business development for specialty foundry TowerJazz Inc. “It is a limited set of customers, compared to lower voltages. In the short term, margin numbers are better for 700 volt technology.”

The foundries do not offer a 700 volt process alone. Instead, they tend to provide a complete modular, multi-volt process, which includes low- (3.3-, 5 and 6.5 volt), medium- (20 and 30 volt) and high- and ultra-high voltage (450 and 700 volt) technologies. “6.5-, 5- and 3.3-volt are used in logic and small signal analog functions. 20 and 30 volts are ideal for gate driver voltages for high-voltage MOSFETs,” Mahlen said.

Andy Brown, vice president of foundry sales for South Korea’s MagnaChip Semiconductor, added: “People may also want 500 volts, because that is the voltage that can directly interface with an AC line. 700 volts is designed for fly-back architectures” and other systems.

Meanwhile, getting a jump on the market, Dongbu HiTek late last year claimed to offer the foundry industry’s first 700 volt process at 0.35-micron. The initial process comes without an epitaxial layer. It supports a range of voltages and maintains low on-resistance (RDSon) by using a reduced surface field technique.

Then, in May, X-Fab rolled out XU035, an 200mm, 0.35-micron process for ultra-high-voltage applications. Using bulk wafers, the process supports 20 , 40 and 700 volts with low RDSon. The total mask count ranges from 13 to 18 steps. The 0.35-micron process is ideal for integrated power-management devices, where cost and functionality are key. “The integrated solutions are becoming more and more popular,” X-Fab’s Hartung said.

Previously, X-Fab offered a 1-micron process for 650 volt applications. “That was an SOI and trench isolation architecture,” Hartung said. “But for high-volume 700 volt applications, we need bulk and 0.35-micron. It’s a cost-effective solution.”

X-Fab is developing a new 0.18-micron high-voltage process based on SOI. The applications for this process are 200 volts, which is ideal for power-over-Ethernet and ultrasound units, he said.

SOI also is getting traction in other analog and mixed-signal markets. STMicroelectronics, for example, recently rolled out a 0.16-micron, SOI-based version of its BCD process for use in medical equipment and hybrid vehicles. The process combines 1.8- and 3.3-volt logic CMOS circuits with power MOSFET transistors that can operate up to 300 volts.

“For RF, SOI is also cost-effective,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is looking to accelerate the use of SOI in the market. In RF switch applications, SOI reduces noise and cross-talk while maintaining signal power, he said.

Semiconductor Manufacturing & Design’s Mark LaPedus talks with Randhir Thakur, general manager of Applied Materials’ Silicon Systems Group, about what’s changing in the foundries, in the equipment necessary to create ICs, and in the structures and materials used in those ICs.

By David Lammers

KLA-Tencor executives said their company enjoyed a record burst of orders in recent weeks and is scrambling to fill them.

Rick Wallace

“The big story in December is that we saw a resurgence in bookings, up 95 percent compared with the September quarter,” CEO Rick Wallace said in a conference call Thursday, following release of fiscal second quarter results. Many of the orders for the December-ending quarter came in the final two weeks of the quarter, resulting in $950 million in bookings for the quarter, the second-highest in the company’s history. Revenues for the December-ending quarter were $642 million.

“We begin 2012 with great optimism,” Wallace said, adding that “our biggest challenge now is meeting demand.” Vendors are maxed out and “factories are full and trying to keep up,” he said. CFO Mark Dentinger added that KLA-Tencor is hiring again but plans to increase the work force by only 1 percent or so.

KLA-Tencor recently announced a suite of new and upgraded wafer inspection tools, covering the brightfield, darkfield, and e-beam wafer inspection sectors. The new tools coincide with foundry customers scrambling to figure out how to boost yields for 28nm wafers, he said.

Foundries face high expectations from customers in the smart phone and tablet markets, many of which are introducing 28nm SoC processors with larger die sizes than in previous generations. The larger die, and the challenges of finding defects and controlling processes at the tighter design rules, are proving challenging for foundries. That is driving them to buy more wafer inspection and metrology tools.

““Expectations for 28nm are overheated right now. It is imperative for the foundries to go after yield improvements, and we have the tools which can help them with that,” Wallace said.

After several years in which SoC die sizes have remained relatively constant, die sizes are increasing for logic ICs used in smart phones and tablets. And yields improvements are critical. That puts KLA-Tencor “right in the sweet spot” of where foundries are spending, Wallace said, noting that foundries accounted for 57 percent of the company’s business for the December quarter. NAND vendors also are spending more on metrology and process control, particularly as the NAND devices move to more vertical structures.

For logic, about half of KLA-Tencor’s bookings are from customers building PC and server processors, and half from foundries driven largely by smart phones and tablets. While the types of defects are similar to those seen in the 40nm generation, defects are smaller and often require new tools, he said.

One analyst asked if investments in process control will increase sharply as a percentage of total wafer fab equipment spending. Wallace said his company expects its served market opportunity to increase slightly this year to 14 percent of an expected WFE of roughly $30 billion this year. WFE capex for 2012 could be flat to down 10 percent for this year, with the macroeconomic picture making forecasting more difficult than usual. Process control and metrology will outperform the rest of the equipment industry this year, as it did last year, he said.

KLA-Tencor has about a billion dollars in orders which have not yet shipped, and one analyst asked if the company’s backlog could stretch out this year. Wallace said that, depending on the product, it takes from three to nine months for tools to ship after an order is placed.