By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.
SMD: What does hybrid metrology accomplish in the process control flow?
Allgair: The structures are becoming so complex. You are trying to measure a particular application on a 3D device, where you have a lot of variations that already took place prior to the measurement step. Hybrid is one of the ways to address that challenge. For us, it enables us to use a lot of the information that is collected upstream for the measurement event you are actually doing. It allows us to understand, as much as we can, about the structure in terms of how it was processed and what it looks like prior to that measurement step. And then, for the variables you are trying to measure, it helps reduce some of the uncertainty of those variables you may not understand from that particular process step you are measuring. Again, that information can be thickness, compositional and CD.
SMD: Do you think directed self-assembly (DSA) will succeed? And does the industry have an inspection/metrology solution for DSA?
Allgair: As we keep driving litho, there is a decent chance that DSA will happen. We will probably try to postpone it as long as we can, and try and get through what we’re currently using. When it does happen, it may end up being a different type of solution than we thought. After SPIE, and looking at one of the papers from MIT, it looks like there might be a way to measure the structures that were used to pattern your DSA. It might be that we monitor that structure. Then, we will have some confidence that the DSA activity takes place and works. All told, if we can get a DSA system that works well, and there is a cost advantage to it, that could drive an earlier adoption for DSA. That is a big component to DSA.
Heidrich: We certainly see the promises. The cost reduction is there, but the challenges of proving low defectivity and performance still remain. Certainly, in the case of memory and related types of processes, where you have redundancy, DSA will get adopted earlier. There has been work on contact holes, where you can do reduction with DSA. When the yield is proven, and if the cost benefit is there, DSA will get adopted. But I think that is still quite a few years away.
Newcomb: DSA is just one of the options available. We have all been in the industry long enough to know there are multiple options. But DSA is the one you want to try to avoid as long as possible because there are many unique challenges. Will it happen? Maybe not. If it does, you have to put all of the pieces together to bring it into high volume production. The challenge comes down to defectivity and integration.
Shetty: DSA is exciting. DSA will most likely happen, but cost would be the biggest challenge in terms of making it production-worthy.
SMD: The industry is in need of new inspection/metrology breakthroughs and tools. Do you agree? And how does the industry fund the development of new tools when there are not enough R&D dollars?
Allgair: It is apparent that we have a need for some new techniques. The ones we’ve talked about are multi-beam e-beam inspection, CD-SAXS, helium ion and a higher resolution CD tool. These are addressing defect-inspection resolution, CD resolution, scatterometry and compositional analysis. The problem that we are trying to grasp is the people that use these new tools are the ones on the leading edge. Those are for devices at 14nm and beyond. There are not a lot of companies in that space. So, it’s not clear how many tools would get ordered at the leading edge. And the other problem is chipmakers like GlobalFoundries, Intel and others may not have provided a clear and concise message in terms of what our future tool needs are to the toolmakers. Regarding GlobalFoundries, as well as my peers at Intel, TSMC and others, we all need to get a little better organized in terms of defining our problem statement to the tool vendors. The second piece is how do you fund a new tool development program? That one is challenging. We’ve seen other funding models, where we have joined other companies and put money together to drive the development of a new tool in litho or to drive a consortium. It’s possible that chipmakers can get together and try to drive something along that line. Another possibility is that each customer could buy the first generation of new tools from vendors. That might be enough for suppliers, who can then seek funding on their own.
Heidrich: We see two things that are challenging from the R&D point of view. One is the rapid consolidation from our end-customer base. We have fewer than a dozen major customers left. In the near- or long-term, that number will likely get smaller. So you have to have fewer customers to absorb the R&D for all the products you need to develop. Secondly, we have very diverse and complex process flows that different customers are adopting. This could be a finFET flow, vertical memory flow, or a 3D device integration flow. So you have more demands on your R&D. Right now, we need to make sure the R&D dollars solve the hard problems and we leverage that learning across all the different end customers. What that means is that if someone has a unique challenge, it gets harder and harder to provide a custom solution.
SMD: What about VC-backed startups like Qcept?
Newcomb: If you go way back, the industry had lots of startups. You had tier-one customers of course, but you also had a plethora of tier-two and tier-three fabs in the world. Now, as an equipment maker, you are not going to get funding that easily, because there are maybe 12 or less major customers in the world. It also takes more money to develop products. The dynamics are also different. You have new memory and logic requirements. We are tying together the OSATs and fabs with 3D TSV integration. In addition, the industry is moving towards two major suppliers on the equipment side and a handful of customers on the device side. That dynamic makes it very difficult. The big challenge is how will the industry keep investing and address those types of needs?
SMD: What’s the solution to this problem?
Newcomb: In one possible solution, companies on the device side could pre-buy the technology rights to the first tool to help fund some of the required investment and R&D. Or maybe, we can better integrate the university work into a model that can be funded and driven into the industry to solve a problem.
Shetty: R&D is becoming expensive. The device nodes are shrinking quickly. And customers’ expectations are increasing. Across the industry, everyone is pushing to get a lower cost-of-ownership and higher productivity. That’s just a fact of life. There are maybe 12 customers out there. But between the joint ventures and consortia, there are maybe four or five R&D centers out there. Today, it is very important that you are involved with these R&D fabs very early in the process. Then, the tool evolves with the process. So when customers move into production, the tool is already mature and ready to go. On the other hand, the devices are changing so much. And in a lot of cases, the customers themselves don’t know what’s going to happen.