By Mark LaPedus

The semiconductor equipment market continues to improve in 2012, prompting VLSI Research Inc. to raise its fab tool forecast for the second time in recent weeks.

Citing recent moves by Intel, Samsung and others to raise their respective capital spending this year, VLSI Research now predicts the semiconductor equipment market will reach $49.2 billion in 2012, down 7.1 percent over 2011. And in another positive move, VLSI Research also raised its overall IC forecast from 3.9 percent growth to 4.3 percent in 2012.

Not long ago, the research firm originally projected that the fab tool market would fall by a whopping 20.1 percent in 2012. Then, in February, VLSI Research raised its forecast and predicted the semiconductor equipment market would reach $45.6 billion in 2012, down 9.8 percent over 2011.

“Chip makers are generally optimistic and many of them are seeing positive trends in the market,” according to a new report from VLSI Research. “They expect a healthier business environment in the coming quarters. Foundries are at the forefront and investing aggressively as most of their leading-edge capacity is tapped out. The equipment industry is seeing a nice rebound following a weak Q4.”

There are some troubling signs as well. David Rubenstein, an analyst with Religare Capital Markets, an investment banking firm, sees an uphill battle for fab tool makers in 2012. “We project that capital spending will fall 12 percent year-over-year in 2012,” he said. “We forecast -19 percent FPD capex in 2012 and further declines in 2013.”

One of the problems is the ongoing memory downturn, which is hurting capital spending. “The memory sector remains a drag on the overall activity,” according to VLSI Research. “NAND orders are still soft as the industry burns some excess SDD inventory. DRAM activity remains pretty much frozen.”

Greg Wong, an analyst with Forward Insights, a research firm, sees a rebound in NAND flash. That market is “fairly weak right now due to seasonality. But it should starting improving in the second half with new smartphones, tablets and ultrabook launches,” Wong said.

Total inventories increased nearly 1 percent in February and are projected to jump by another 3 percent in March, according to VLSI Research. Total IC inventories in March will be 7 percent lower than from last year’s levels, according to the firm.

The fab tool vendors are also seeing a mixed picture. At the recent Applied Materials Inc. analyst event, Applied CEO Mike Splinter acknowledged that the company sees a challenging environment.

At the event, Applied guided fiscal 2012 revenues and EPS of $9.1-to-$9.5 billion and $0.85-to-$0.95, respectively, falling short of consensus of $9.6 billion and $0.96. This is “driven primarily by weakness in non-semi segments” like solar and displays, said C.J. Muse, an analyst with Barclays Capital.

“On the positive side, Applied is poised to benefit from several positive trends in semi,” including “increasing process steps in the move to 2Xnm/1Xnm, a move to 3D NAND, sustainability of wafer fab equipment spending, and growing capital intensity in display,” he said.

Samsung Electronics Co. Ltd. said it is planning to build its NAND flash fab in China in the city of Xi’an. On April 2, 2012, Samsung approved the investment for establishing the fab in China at a cost of $2.3 billion. That figure is part of the total investment amount of $7 billion to be invested over the next several years.

The company is considering establishing a 10nm-class NAND Flash memory production line in Xi’an, China to meet growing market demand for NAND products.

Xi’an, the capital of the Shaanxi province, is famous for the “Terracotta Army” site. This is a collection of terracotta sculptures depicting the armies of Qin Shi Huang, the first Emperor of China.

Samsung ”selected Xian because the city has sound industrial infrastructure such as water and electricity supply and can supply a talented workforce,” according to The Korea Herald, a newspaper and Web site. ”The city has a number of universities and research and development centers for IT firms.”

Last December, Samsung said it applied for the Korean government’s approval for establishing a NAND fab in China, but it did not announce the exact site. The idea behind the fab is to mass produce NAND products at 20 nanometer-class or below, according to Samsung. The company aims to start building the production line in 2012 and begin operation in 2013. The company plans to invest between 4 trillion won ($3.5 billion) and 5 trillion won on the fab, according to reports.

In 2012, Samsung’s capital expenditures are forecast to amount to 25 trillion won ($22.3 billion), in which 15 trillion won ($13.39 billion) will be invested in the semiconductor business.

By Mark LaPedus, SemiMD senior editor

Citing a slowdown in the IC industry, investment banking firm Barclays Capital has lowered its wafer fab equipment (WFE) forecast for 2012.

In a report issued Monday (Sept. 26), C.J. Muse, an analyst with Barclays, also lowered his forecasts for lithography tool and system-on-a-chip (SOC) testers. In the overall WFE sector, Muse sees “muted growth expectations for 2012.”

In total, the WFE market is projected to range between $26 billion to $29 billion in 2012, flat to minus 10 percent over 2011, Muse said in the report. In his previous forecast, the WFE market was projected to reach about the $29 billion level and would not go below that figure, he said. In 2011, WFE is expected to range from flat to plus 5 percent, according to the firm.

Barclays also projects that worldwide capital spending will hit $54.261 billion in 2011, up 17 percent over 2010. In 2012, Barclays projects that capital spending will reach $50.216 billion, down 7 percent over 2011.

The new forecast reflects a recent slowdown in the IC market. On the logic front, processors shipments are “stable” in the market, but DRAMs are in the midst of a slump, according to VLSI Research, a market research firm.

But suddenly, “DRAM supply in the spot market (continue) to tighten due to production cuts by Taiwanese manufacturers,’’ according to VLSI Research. “As a result, many suppliers have cut their DRAM shipments in the spot market, prompting significant price increases across the board. Memory module houses are also joining the pack by raising DRAM prices for the first time in more than six months.”

Gregory Wong, an analyst with research firm Forward Insights, said that NAND flash has weathered the storm thus far. “Flash demand continues to be driven by smartphones and tablets,” Wong said. “SSDs are another bright area for NAND flash demand.”

Barclays’ Muse projects that the overall IC market will grow 4 percent in 2011 and 6 percent to 8 percent in 2012.

The capital spending picture is mixed. “We now see 2011 capex up 15 percent 20 percent year-over-year,” Muse said. “Looking to 2012, our bottoms-up forecasts point to 2012 total capex of down 5 percent 10 percent year-over-year.

In lithography, Barclays believes that 248-nm tool shipments will range between 60 to 65 units in 2012, down from 90 to 100 units in 2011. The firm predicts that 193-nm “dry” lithography shipments will be flat in 2012 over 2011. In 2011, Barclays predicts that 193-nm “dry” tool shipments will range from 10 to 12 units.

“However, given the pull-back in both foundry and logic, we now believe immersion shipments are tracking to 110 to 120 units (in 2011), versus our earlier estimate of 120 to 125,” Muse said. “Immersion shipments are likely to decline to (about) 80 to 90 units (in 2012),’’ he said.

Barclays is also lowering its outlook for SoC tester demand in 2012. The SoC tester market is projected to hit about $2 billion in 2011. “We now look for a more muted recovery in 2012, as we now model SoC test at (about) $2.3 billion (versus the) previous estimate of (about) $2.5 billion,” he added.

Worldwide chip revenue has slowed in 2011. The semiconductor market is on pace to have revenue total of $299 billion, a decline of 0.1 percent from 2010, according to Gartner Inc., a market research firm. This outlook is down from Gartner’s previous projection in the second quarter for 5.1 percent growth this year.

“Three key factors are shaping the short-term outlook: excess inventory, manufacturing overcapacity and slowing demand due to economic weakness,” said Bryan Lewis, research vice president at Gartner.

“Semiconductor companies’ third-quarter guidance is well below seasonal averages. The current guidance by vendors points to flat to down third-quarter growth,’’ he said. “Typically, we see guidance for 8 to 9 percent growth in the third quarter because of back-to-school and the holiday build. The supply chain is also showing significant slowdown, and semiconductor-related inventory levels are still elevated.”

What about 2012? “2012 is the wild card. We have lowered our 2012 semiconductor forecast from 8.6 percent to 4.6 percent due to a worsening macroeconomic outlook,” Lewis said. “However, the odds of a double-dip U.S. recession continue to rise and are raising fear that sales prospects will deteriorate further.”

Meanwhile, in 2011, PC production unit growth has decreased. Last quarter, Gartner estimated PC production growth of 9.5 percent, but that has now been reduced to 3.4 percent.

Gartner has lowered its forecast of mobile phone production unit growth from a second-quarter projection of 12.9 percent growth to 11.5 percent growth in this most recent outlook.

DRAM has been impacted by reduced PC demand and falling prices and is now expected to decline 26.6 percent in 2011. NAND flash and data processing ASIC are the fastest-growing device areas in 2011, with about 20 percent growth.

by Ed Korczynski

Resistance-change Random Access Memory (RRAM or ReRAM) devices continue to be developed at labs and fabs around the world, as seen by more than 40 papers at the spring Materials Research Society (MRS) spring meeting which was held April 25-29 in San Francisco, California. RRAMs are based on resistive switching in metal oxides, such as titantia and niobia, that show memristor properties. With single-digit nanosecond switching-speeds and 10-year non-volatile data retention, RRAMs may represent the future of solid-state memory after DRAM and Flash devices eventually reach scaling limits below 22nm half-pitch.

Technically, the other devices competing with RRAM for the future of memory are themselves based on changes in resistance. Phase-change memory (PCM) using GST material switches between low- and high-resistance states, but requires large drive currents to heat the material to effect the phase-change. Spin-transfer-torque RAM (STT-RAM) is also read as a change in resistance, but the cell size is relatively large. RRAM devices built using cross-point arrays could provide the smallest, fastest, leanest, and cheapest non-volatile memory chips.

Between oral presentations and posters, the Spring 2011 MRS Meeting showed many different groups using different switching materials for RRAMs:

8 – TiO

7 – NiO

6 – Zn0:metal

4 – SiO:Cu

3 – HfO:metal

3 – TMO:metal

3 – polymers

2 – TaO

2 – SrTiO

1 – CuO

1 – HfSiO

1 – WO

1 – solid electrolyte

42 + 11 more novel materials in session Q10

= 53 total RRAM presentations.

HP Labs RRAM Update

Stan Williams’ group at HP Labs has led the world in memristor and RRAM R&D using the titania family of materials as the switch since 2006. They claim that their champion device switches in <2ns, and has world-record endurance of >1.2E10 cycles. Stan Williams provided a keynote address to an MRS workshop last year, in which he explained how his group finally discovered that the conducting channel consists of a 1-2nm thin TiO2 tunnel barrier adjacent to a ~30nm thick “magneli-phase” Ti4O7 layer. Modulating the width of the tunnel barrier through diffusion of oxygen-vacancies controls the electrical resistance of the stack.

This year, HP Labs updated their titania work by reporting on two different electroforming mechanisms seen in the same 50nm × 50nm crossbar memristive device. A “soft” electroforming step uses <140µAmp at ~5V to create a high-resistance mode, while a “hard” electroforming step uses ~250µAmp at ~9V to create a low resistance mode. The two switching modes possessed opposite switching polarities that shared a metastable intermediate resistance state. The two modes can be explained by two switching layers at the top- and bottom-electrode interfaces:

• intermediate state, the bottom layer is ON with conducting channels made of both oxygen-vacancies and charge-traps, while the top layer consists of a tunnel gap;
• OFF state, both layers consist of tunnel gaps; and
• ON state, the top layer is ON with conducting channels made of oxygen-vacancies, while the bottom layer consists of a tunnel gap.

J. Joshua (Jianhua) Yang, provided an update on HP Labs’s RRAM work by surprisingly stating that titanium-oxides have stability issues which may limit device lifetimes, but that tantalum-oxides are free of such issue. The titania family seems to show issues getting beyond 100-1000 cycles, due to excessive heating inside the switch material due to the tendency to apply overvoltage. The two phases of titania will react with each other during heating, so the ON/OFF resistance differences are not so stable. “You need stability, and larger oxygen stability in the materials,” explained Yang. Presumably, the world-record cycling performance using titania was achieved using careful limits on overvoltage.

To improve lifetime with overvoltage margin, HP now uses a tantalum-oxide switching layer, a platinum bottom-electrode, and a tantalum top-electrode. The company claims that this system should be scalable to <5nm, the switching speed is merely 5ns, and the resistance state should be stable for 10 years. TaOx as deposited is amorphous, and even after heating steps it may retain some amorphous character.

RRAM Electroforming Avoidance

The ability to create functional RRAMs without electroforming would provide a significant cost and yield advantage in manufacturing. Though there is still debate as to the exact nature of the solid-state ion-diffusion mechanism(s) responsible for the change in resistance, it is clear that proper stacks of nano-scale oxides and sub-oxides are needed. Consequently, once trial-and-error has identified an ideal materials stack, it is likely that a wafer-scale process flow will be found to create the desired stack without the need for electroforming. For example, annealing in a reducing ambient or solid-phase gettering techniques may be used to adjust the stoichiometry of thin-films.

Using a tungsten-plug from a 90nm node DRAM process flow as one electrode, researchers from Research Center Juelich (with funding from Intel) used TiO2 thickness of 25nm and a Pt/Ti top electrode to make inherently electroforming-free RRAMs (Session Q8.4). Initially the devices were found to be in an intermediate state, and can be SET with positive bias voltage to the low resistance state (LRS). Without bias the intermediate state undergoes a RESET process to a high resistance state (HRS). Under negative voltage bias both processes can be reversed and the device returns into the intermediate state. This flipping of the SET and RESET process from positive to negative bias voltage polarity and vice versa can repeatedly be adjusted in one device. This versatile switching scenario is possible due to the use of the low-workfunction Ti and W electrodes which result in low barriers to the oxide.

The Juelich process flow is as follows:

1. Plasma etch to clean the W plug,
2. Reactive sputter TiO2 (300W, 46sccm AR, 17 sccm O2), and
3. PVD of top-electrode.

The top-electrode was 30nm Pt with an optional 5nm layer of Ti or W below. “As long as there is a Pt/TiO2 interface we need forming,” explained Rainer Bruchhaus of Juelich. However, when using either W or Ti as a barrier between the Pt and TiO2 (while maintaining W as bottom electrode) they see no need for electroforming. In all cases, the voltage range is limited to +- 1V.

RRAM scalability

Much of the global interest in RRAM structures is due to the ability of cross-point memory architectures to be shrunk far more easily than other device structures. The process flow to make cross-point arrays is particularly attractive from an overlay perspective, since the top- and bottom-electrodes are perpendicular to each other and the switching material is patterned along with the top-electrode.

The world record for the smallest resistive memory element is currently held by the National Nano Device Laboratories (NNDL) in Taiwan, which showed a 9nm half-pitch functional RRAM at IEDM last December (Paper #19.1, “9nm Half-Pitch Functional Resistive Memory Cell with <1 µA Programming Current Using Thermally Oxidized Sub-Stochiometric WO_x Film,” C. Ho et al, National Nano Device Laboratories, Taiwan/University of California at Berkeley). It features the lowest reported programming current to date of just <1µA using tungsten-oxide, compared to ~20mA for phase-change memories. The device was built using nano-injection lithography which employs a chemical reaction activated with a finely controlled electron beam to deposit a hard-mask for etching, but could have used Nano-imprint Lithography (NIL) or other patterning to form the array.

For more details on the physics of these devices, Applied Physics A, Vol.A102, No.4 is a special issue on “Memristive and Resistive Devices and Systems,” and is now available for free download as individual PDFs.

by Ed Korczynski

After years of debate and development, air gaps are finally seeing commercial introduction in Flash interconnects. An IEDM 2010 paper presented by Kirk Prall of Micron Technology and Krishna Parat of Intel described the interconnect technology used for the companies’ 25nm multi-level-cell 64 Gbit NAND, which includes air-gaps in low-k dielectric materials (figure).

The disclosure follows details first shown by Intel at the International Interconnect Technology Conference (IITC 2010) on the reliability of air-gaps for electrical insulation in nano-scale devices. While other companies have shown tests of air-gaps, this is the first time that a commercial chip has been designed using air-gaps. Prior Flash chips from many manufacturers have had air-gaps, but seemingly only as anticipated accidents. Philips (now NXP) and IBM have reported on air-gaps for logic chips, but thus far without product commitments.

To reduce the dielectric constant (k) in shrinking integrated circuits (IC), there once was a roadmap for new materials to be deployed with ever lower k at each node. However, integration challenges in practice limited new materials to essentially two moves over the last 15 years: from SiO2 (k~4) to SiOF (k~3.5) and then to SiOCH (k~3). Because solid materials with k<3 have generally not met integration requirements for mechanical stability, much effort was expended to try to add pores (with k~1) to SiOCH to make a porous-low-k (PLK) dielectric with bulk k value proportional to the percent of air incorporated. PLK with porosity up to ~10% allows for k~2.7, and such a film can be integrated with minimal extra work (perhaps just a UV stabilization anneal step) compared to pure SiOCH. However, adding porosity >10% mandates the use of extra barrier/cap layers that almost always combine to produce new failure mechanisms, and the extra layers add capacitance to the whole dielectric stack such that the “effective-k” (keff) tends to end up back at ~2.7 after integration.

At an abstract conceptual level, an air-gap in a dielectric may be considered as a limiting case of PLK, where there is merely one large pore designed into the center of the structure. This is different from “air-bridges” where all solid and liquid dielectric is removed from interconnect structures. Some solid SiOCH dielectric remains around the air-gaps to provide mechanical strength and chemical barrier.

At IEDM 2010, Hynix R&D Division researcher Sungjoo Hong discussed the challenges of continued scaling of NAND Flash technology based on the floating gate (FG) architecture. Scaling has created word-line (WL) to WL spacings such that cross-coupling effects now decrease programming speed. Hong stated that air-gap technology can minimize cross-coupling, but it is necessary to control the integrated process for precise uniformity.

In 2006, researchers from Philips (working with ST, Leti, and IMEC) presented an outstanding paper at the Materials Research Society (MRS) spring meeting on “Benefits and Trade-offs in Multi-Level Air Gap Integration” (Ref: MRS Symp. F Proc. Vol.914). The paper provides a thorough overview of the possible variations on the air-gap theme: generally either additive using CVD or subtractive using a plasma/furnace/vacuum chamber.

One year later, IBM showed subtractive air-gaps integrated into an interconnect stack as proof of concept, using either lithography or self-assembled monolayers to mask off areas around the gaps. At IITC2010, Intel researchers reported that their air gap integration tests have so far resulted in no new failure modes observed. This is highly significant since almost any material change results in new ways for things to fail.

Additive air-gaps: pinching off bread loaves free

For over twenty years, air-gaps have been seen as defects in dielectrics deposited between metal lines. This editor once ran the application lab for Watkins-Johnson (W-J) atmospheric pressure chemical-vapor deposition (APCVD) systems, and learned that any CVD tool can be tuned to produce air-gaps in between lines of equal spacing. As the line sidewalls get coated the cross-section of the coating starts to look like a “bread-loaf” on each side until the top sides “pinch-off” to form an “air-gap” (figure). If you are working with subtractive metal patterning like that for aluminum or tungsten then additive air-gaps can come free with the dielectric deposition.

If you are working with additive metal like copper then additive air-gaps cost an extra etch and deposition step. Of course in either case, the “gap” is really an elongated bubble, and the “air” inside is a combination of the ambient inside the CVD chamber along with trace vapors from the dielectric material.

ChipWorks (the IC reverse-engineering experts in Ottawa) have cross-sectioned commercial memory chips for many years, and often observed dielectric voids in NAND Flash structures. “We have seen voids in between the wordlines of NAND Flash chips, in structures that appear to be not too different from what have been regular in memory,” said ChipWorks’ senior technology advisor Dick James. “We’ve seen voids at ~50nm half-poly-pitch in NAND chips. Even at ~90nm there have been variable voids.”

However, the voids seen so far in commercially available NAND chips appear to be incidental, since they vary in size from gate to gate and sometime disappear entirely (figure). Since ChipWorks has SEM cross-sections of chips from Micron, Samsung, and Toshiba all showing sporadic air-gaps, and since none of these companies had declared air-gaps as intentional design elements, it appears likely they truly were anticipated accidents. Anticipated since the design and manufacturing must allow for air-gaps to be present, yet accidental since the air-gaps may not appear in any one place. Generally speaking, the repeating structures of memory chips makes such anticipated accidental integration possible, while random logic structures don’t allow for such accidents.

Subtractive air-gaps: staying between the lines

To control where air-gaps form outside of periodically structured arrays, another lithography step may be needed to align an etch mask, as shown by Philips and IBM. During their IEDM presentation, Micron and Intel did not detail the air-gap integration processes used for the WL and bitline (BL) dielectrics. However, since the two cross-sections appear differently in the IEDM paper, they probably used different processes. The WL direction looks similar to the WL seen by ChipWorks in previous NAND structures, so was probably formed additively. Presuming the designers are given forbidden pitches to avoid in a layer, the air-gaps could truly come free without even the need for a “non-critical” mask to block out inconvenient areas.

Air-gaps may soon appear in logic structures as well. Since it appears likely that the 22/20nm node of logic will rely upon 1D grid layouts, such severely restricted-design-rules (RDR) will already include forbidden pitches. Consequently, pinch-off additive air-gaps could easily be tuned into CVD processes for dielectrics. If subtractive air-gap flows are needed, then array patterns still allow for relatively easier patterning. Both Intel and IBM are now in top-secret pilot production with this node, but within the year we should learn whether air-gaps are only for memory or whether they will be the mainstream low-k dielectric solution for all future ICs.