Soitec’s Steve Longoria talks with Semiconductor Manufacturing and Design about what’s changing at the leading edge of Moore’s Law and why those changes are necessary.

By Mark LaPedus
Enterprise-based bring your own device (BYOD) programs continue to become more commonplace. In fact, 38% of companies expect to stop providing devices to workers by 2016, according to a global survey of CIOs by Gartner.

What would happen if half of all global DRAM production, two-thirds of NAND flash manufacturing and 70% of the world’s tablet display supply suddenly disappeared from the market? For high-tech companies, this could be the outcome if current tensions escalate to the point of war on the Korean peninsula, resulting in the disruption of South Korea’s technology manufacturing base, says IHS iSuppli.

Intel telegraphed its future directions. The chip giant has named Brian Krzanich as its next chief executive, succeeding Paul Otellini. Krzanich, Intel’s chief operating officer since January 2012, will become the sixth CEO in Intel’s history. As announced, Otellini will step down as CEO. In a research note, Hans Mosesmann, an analyst with Raymond James, said: “We are not entirely shocked by the news but note that some investors preferred an external option on the belief that new blood was needed. Giving Krzanich’s manufacturing background we think the appointment is an indication that Intel will continue Paul Otellini’s strategy of building bigger/better fabs to attack the market. We also believe the move toward better manufacturing processes (like the 450mm transition) will remain front and center.” Added RBC Capital analyst Doug Freedman: “The move to appoint Renee James (as president) is likely in support of the vision of Krzanich’s and the board has laid out for the future of Intel. This appointment validates the increasing importance of on-going software development to Intel’s future, whether it be internally or in collaboration with partners.”

Microsemi has inked a foundry deal with Intel. Microsemi is currently engaged with customers and has started designs utilizing Intel’s 22nm tri-gate technology. Product delivery is anticipated to begin in late 2014 to early 2015.

Infineon and GlobalFoundries announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology. The cooperation will focus on technology development based on Infineon’s eFlash cell design and manufacturing of automotive and security microcontrollers with 40nm process structures.

GlobalFoundries has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20nm and 14nm. GlobalFoundries is using the Cadence Pattern Classification and Pattern Matching Solutions.

SEMI announced that Philip Yeo, chairman of Spring Singapore, and Lee Kok Choy, country manager of Micron Technology Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry. The awards will be presented during festivities held at Semicon Singapore 2013 on May 7.

Soitec has finalized a ZAR 1,000,000,000 (more than $100 million) solar financing bond issued by CPV Power Plant No.1 Bond SPV, an affiliate of Soitec Solar GmbH. The bonds will finance the construction of a 44 MWp utility-scale concentrator photovoltaic (CPV) solar power plant in Touwsrivier, South Africa.

Applied Materials and The Center for Science Teaching and Learning (CSTL) announced the San Francisco Bay Area grand-prize winning team and nine finalist teams in the 2013 Clean Tech Competition.

Rudolph has purchased selected assets related to 3D metrology from Tamar Technology.

Proteus Digital Health has completed a second closing of its Series F financing, raising $62.5 million in total. New corporate investor Oracle joins Otsuka, Novartis, Sino Portfolio and others in this funding round. Proteus is working to create a new category of products. Called Digital Medicines, these new pharmaceuticals will contain a tiny sensor that can communicate, via a digital health feedback system, vital information about an individual’s medication-taking behavior and how their body is responding.

Is Mindspeed Technologies on the block? The supplier of semiconductor solutions for communications has retained Morgan Stanley as a financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Spansion has acquired the microcontroller and analog business of Fujitsu Semiconductor for approximately $110 million, plus approximately $65 million for inventory.

Amkor Technology announced that Stephen Kelley has been appointed to serve as president and CEO. He succeeds Ken Joyce, who previously announced his intention to retire.

ASE remained the world’s largest OSAT in 2012, according to the new rankings from Gartner.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: From your vantage point, what are the challenges for lithography?
Allgair: Among the challenges are resolution and the interaction of the metrology with the resists we are trying to measure. Of course, the resist materials are getting thinner and thinner. And this creates its own set of challenges both from a resolution and an interaction point of view. Also, when moving to new materials, there is the measurement piece. As I mentioned before, we want more 2D and 3D information from the resists. In addition, we want to compare the resists versus what we did with the design. And we are trying to look for the defects. And with overlay, we are seeing challenges there, as well—everything from the sheer volume of the measurements we have to take, to the ability of the overlay targets to really predict what’s going on within the circuit itself. That frequently drives the need for more targets and with in-die targets. And that gets further complicated by the fact that your targets can be impacted by your processing, so you wind up having process interactions that are involved in the overlay target measurements. Somehow you need to take those interactions out to understand where your overlay is.
Heidrich: Litho is driving resolution, overlay and process effects. From each of those, from a CD point of view, we see OCD is the method of choice. Regardless of the techniques used, customers are dealing with measurements on more complex structures in a design. So the question is how many types of structures do you measure in production to track OPC corrections and other complex interactions, as well as additional complexity in the resist patterns themselves? You could end up seeing a double pattern litho resist or other type of litho resist. For overlay, there is a data explosion. The data is going up. At the same time, target size is going down.
Newcomb: Edge inspection is an area of interest. There is a need to combine your wafer inspection and edge inspection and do multi-analysis and multi-channel inspection. Regarding the resists, customers are seeing interactions, for example, in the CD-SEM and e-beam. This is making it difficult to make good and accurate measurements. In the past, it was all about beam alignment, emission and spot size in order to make a measurement for a via hole as one example. Now, in litho, that resist has a charge and creates an electric field that directly impacts the ability to make those critical measurements.
Shetty: As the device sizes are shrinking, the overlay budgets are shrinking. Right now, at 20nm and 16nm, the overlay budget is around 10nm or 8nm. But because of all the issues the customers are having, such as EUV implementation, customers are going with unique schemes like double patterning and triple patterning. What happens is that 10nm budget gets cut by half or one-third. So every part of the overlay budget gets impacted. There are three parts of the overlay budget. There is one that is coming from the overlay tool from the scanner. The second one is coming from the reticle. The third one is coming from the wafer itself. These are wafer-based distortions that the scanner can’t fix. Regarding the overlay tool, traditional tools like Archer and others measure the overlay. As the device sizes are shrinking, the targets are behaving more and more differently than the devices themselves. Customers are left with two choices. Either they can increase the number of targets on the wafer and then take a hit on throughput and have higher costs. Or, they can find a different way to measure these wafers. For example, by using limited targets on the wafer, they will not get all of the information they need for the scanner to fix the wafer.

SMD: What about finFETs?
Newcomb: 3D structures like finFETs not only require more metrology and inspection steps, but they involve a lot more complexity. You are not just looking at the information in the x, y, and z axis, but also at the atomic level of x, y and z. You are asking things like how does that device come together? What is the structure of that device? Does it meet the specs? We are starting to see some interesting interactions with existing process tools types, whether they are across the edge or wet cleaning. When you use existing technologies, and try to build 3D structures, you are getting defect signatures that we’ve never seen before from net Vdd perspective. You also have all of these defectivity models coming forward and you have to deal with them.
Allgair: Going to 3D has created numerous challenges for us. We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. In an x, y and z matrix, you need to ask: ‘The atoms are there, but are they the ones you want? Are they electrically active or not?’ We are trying to use the same tooling that we currently have available. You will see the CD-SEM, OCD, and the overlay tools you are familiar with. With finFETs, we can do some things, such as CD, height, profile, spacer, and thickness. Some of these applications can be done using scatterometry or CD-SEM or a combination of that data set. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.

SMD: What are some of the issues with stacked 2.5D and 3D devices?
Newcomb: As we turn to the 3D packaging world, and we think about stacked memory or memory on logic, we have techniques like traditional optical inspection. Although it will be important for 3D packaging and 3D ICs, you have to be concerned about a whole new class of things like sub-monolayer metallic contamination within the device area. If these wafers need to be thin, and I need to expose the TSVs, I start seeing copper defectivity and sub-monolayer issues. Now, I am trying to stack multiple known-good die. As we package these known-good die in 3D structures, and if you have one mistake like sub-monolayer copper residue, that will make multiple known-good die no longer any good.
Heidrich: Plus, you hand off a known good wafer to someone and then you need to integrate it. In effect, you are doing double metrology and double inspection. And then in the process itself, there is a lot of complexity we address in terms of TSVs. Metrology and inspection for that whole flow must be addressed for cost, performance and reliability.
Allgair: If I look at the 3D TSV side, the idea of stacking structures has created a need for new tools. We have been looking at new techniques, which should work out reasonably well. We are making pretty good progress.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: What are the big challenges in metrology and inspection?
Allgair: As we keep scaling our devices and improved the resolutions, there is a need to not have much interaction with the measurement technique and the sample we are measuring. The information we want to get is also becoming more complex. So in the past, we had one-dimensional CD types of measurements. Now, we really want to understand both 2D and 3D information for the structures that we are measuring. We also have a desire to look at how the structure looks, versus what the design intent was. Of course, the structures are becoming more and more complex to measure. When we look at finFETs, we want to measure everything that we typically would have measured on a normal 2D CMOS device. Except now, we are trying to measure all of these parameters in 3D. That’s becoming very complex now.
Heidrich: Resolution, sample interaction, and complexity drive us, as well as 3D requirements. Top-down measurements, and how wide something is, are important now. How tall is the structure and the undercut are important, as well. The idea of measuring more parameters on a given sample is driving our tool technology and software. But also important, the users of the tools have to deal with even more information, whether how they deal with it for process control or how they collect it from a metrologist point of view. In addition, there are a lot of new architectures coming up in several different areas and all at the same time. One of our challenges is to come up with comprehensive solutions for finFET metrology and 3D ICs for stacking.
Newcomb: The defects continue to get smaller and smaller. But the complexity of those defect issues is being driven by a proliferation of new materials throughout the process at the front-end-of-the-line and the back-end-of-the-line. So when you combine the materials, the device structures and the process technology, we have the continuing challenge of physical defect inspection. But now, we are finding more and more non-visual defects becoming a major part of the yield-critical defects in the fab. Being able to detect those non-visual defects is becoming important, especially at the advanced process nodes.
Shetty: We all agree that resolution is the biggest issue out there. As these device sizes shrink, they are behaving very differently. The information you are getting from these inspection tools is not correlating. Customers are also seeing big yield issues, mainly at the edges of the wafer. And a lot of these inspection and metrology tools are limited on the edge of devices. On the device side, there are two big challenges. The devices are going in vertical dimensions with 3D structures, such as finFETs. On the horizontal direction, customers are going from 300mm to 450mm wafers. This changes the dimensions both in the vertical and horizontal direction, offering more and more challenges in terms of stress, overlay, lithography and CD. We are also bringing in high-stress films like high-k, silicon germanium and thin films. The challenge is can the current inspection and metrology tools keep up with all of these changes taking place.

SMD: Are the existing metrology tools keeping up or do we need new breakthroughs?
Allgair: If you look at the tools available right now, we are primarily controlling the line with the things everyone is used to. We have the CD-SEM, scatterometry, and we have the typical overlay techniques. We use a little AFM. In terms of inspection, we have brightfield inspection and some e-beam inspection. When we look across that tool set, we do see the need for improvements as we move to smaller device dimensions. On the imaging side, we need increased resolution in order to measure some of these features. We are seeing improvements in the CD-SEM. It might be able to get us where we want to go. There may be a need to have a higher resolution-capable tool. We would like that tool not to damage the feature if at all possible. On the scatterometry side, we think that technique is pretty extendable. We start to run into issues with some of the materials interactions. Then, we question the extensibility. There is some work now that says it may extend to the 9nm node before it starts to lose some steam. We have looked at perhaps using another technique like X-ray to extend it.
Heidrich: For the most part, we are doing two things. We are taking tools like our OCD tool and continuously improving the signal to noise for a given configuration. We are also adding more data channels to the tool. We are pretty confident following those approaches we will continue to extend down to many future nodes, and well below normal diffraction limits.

SMD: What about inspection and overlay?
Allgair: On the inspection side, brightfield has some steam left, but it has become very challenged. The idea of having e-beam inspection helps solve some of the resolution problems. But we have a throughput challenge there. So then, we have the concept of multi-column, e-beam inspection. If we could make it work, and have the throughputs that we want, that’s attractive to us. If I talk about overlay, the idea of measuring overlay right off the device structure could be very useful.
Newcomb: We think non-visual defect inspection is the next big thing on the horizon. Most of these leading-edge fabs will say that up to 30% of their yield problems have a ‘no defect found’ category. That basically says I know I have a defect issue at the end of the line and I can see that in my yield maps, but I have no corresponding or matching inspection data from the process line from all of these optical inspection tools or e-beam. Existing tools can address 70% of my defect problems. But I still have 30% of my yields, in which I don’t have a good method to attack from an inspection and yield engineering perspective. That’s where non-visual defect inspection can play a major role.
Shetty: Traditional tools from KLA and ASML do a good job of measuring the targets as a measurement itself. While they do a good job bringing information to the scanners, we are focusing on a tool that gives you non-destructive, high-resolution on the edge of the wafer. And it mainly tells you information on the stress, the shape and distortion. The technology we offer does not replace the traditional overlay tools from KLA and ASML. It’s actually a complementary technology.

SMD: What other breakthroughs are needed?
Heidrich: We see a growing demand for in-line, on-device compositional metrology. That’s an underserved market right now. There are very few tools that have the spot size, resolution and the discrimination that satisfy customers out there.
Allgair: We have been pushing the idea of hybrid metrology, which is the idea of using data from previous process steps. So now, your downstream measurement tool has at least some information coming in about the wafer to make your measurements a little bit more accurate. This is one of the things that could help solve this overall problem of trying to determine what the feature looks like in 3D. From a user perspective, I would like to have a complete picture of what it is I am measuring in the 3D space. I want to know where every avenue is. I want to know where it is located in the matrix, what type it is, and what the electron activity is. That’s ultimately what we want to know. We are still a long way from that. That seems to be kind of the new Holy Grail, so to speak, of metrology.

By Mark LaPedus
Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear.

3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many chipmakers are still developing these technologies and face several process control challenges.

“In our industry, a lot of segments are metrology-limited,” said Christopher Bencher, a member of the technical staff at Applied Materials. “Overlay metrology is the number one area where we are limited. There is also a challenge with 3D devices like finFETs and 3D NAND. You have to be able to characterize them in 3D.”

As with many fab tool markets, there is a disconnect between the rhetoric from chipmakers and equipment vendors. Process control tool vendors insist they are ready for the 3D era. In contrast, chipmakers say many of the existing metrology solutions are running out of steam.

For example, some 50% of the process steps in a fab are devoted to inspection and metrology alone. About 10% of those steps use the workhorse metrology tool in the fab—the critical-dimension scanning electron microscope (CD-SEM). With finFETs, the CD-SEM is being stretched to its limits. “Three quarters of the steps can be handled by a conventional CD-SEM,” said Eric Solecky, senior manufacturing engineer at IBM. “This percentage is growing. It’s that fraction for 3D information that we don’t have a solution today for an image-based tool.”

Near term, there are other challenges in process control. “The main gaps in general are next-generation defect inspection, next-generation charge particle imaging, and next-generation scatterometry profile metrology,” said Benjamin Bunday, senior technical staff member at Sematech. Longer term, the industry also lacks a process control solution for graphene, carbon nanotubes and directed self-assembly (DSA).

Metrology madness
Several tool types—AFM, CD-SEM and OCD—can handle most requirements for today’s planar chips. Atomic force microscopy (AFM) uses a tiny probe to enable measurements. The CD-SEM is used for top-down measurements. And used for CD and overlay, optical scatterometry (OCD) measures the changes in the intensity of light.

But the process control world changed in 2011, when Intel rolled out the industry’s first finFETs. Using a transmission electron microscope (TEM), Chipworks recently discovered that the traditional one-to-one ratio between structures and transistors doesn’t apply with Intel’s tri-gate technology. In fact, one transistor can have multiple fins—six or more—while one fin can have multiple transistors, according to Chipworks.

So for finFETs, a given metrology tool must measure and characterize the separate pieces in the structure, such as the gate, fin height, sidewall angle and others. Each of those parts also requires one or more separate measurements.

The question is which single metrology tool can handle all requirements for structures such as finFETs and 3D NAND? The answer: None of them. There is no silver bullet. “We are already in a deluge of data,” said Jason Osborne, senior systems design engineer at Bruker. “We’ve got many systems making multiple measurements on the same structures and not getting the entire answer off any one system.”

In one possible finFET metrology flow, the fin is measured by the CD-SEM or AFM, and then, the results are feed to the OCD tool. Another possible metrology flow involves the CD-SEM, OCD and a TEM. The TEM, a system that shoots a beam of electrons through a tiny specimen, is used to validate the OCD model. “What you are trying to do is make your scatterometry model more robust,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries.

Intel, meanwhile, uses a combination of undisclosed tool technologies within its finFET process control flow. “We need all solutions,” said Adam Schafer, area manager of metrology and inspection at Intel. “We need to combine them.”

In process control, the biggest challenges for Intel can be summarized in three words—cost, noise and throughput. “Noise is one of our top problems. And it is really distinguishing the signal from the noise in any one of our techniques,” Schafer said.

Each tool type has its own set of issues. “If you are talking about CD-SEM, my CD measurement is traditionally top down. That’s not enough. I cannot control my processes with those CDs,” said Alok Vaid, senior member of the technical staff at GlobalFoundries. “Regarding OCD, it’s a solution, but it’s too complicated. So if you look at 14nm, 10nm and beyond, I don’t think the small dimensions are an issue for OCD. In fact, it can work in your favor. The problem is correlations.”

For AFM, the challenge is to measure finFETs in 10nm to 20nm spaces and characterize the profiles and shapes, he said. “We can’t leave optical tools such as ellipsometry out of the picture. Since everything is going 3D, now you want to measure those thicknesses and compositions on actual 3D structures,” he said.

The solutions
For some time, GlobalFoundries and others have been talking about the solution to the 3D problem—hybrid metrology. In this approach, separate tool technologies are used in a flow. The challenge is to put rival tool vendors in the same flow and tell the competitors to collaborate and share proprietary data with each other. “Let’s take an example. You have a CD-SEM supplier. You have an OCD supplier. And let’s say you want to overlap them and get my results. You can’t do that unless you get those guys to draw an algorithm together and get them to collaborate,” Vaid said.

While hybrid metrology is perhaps the wave of the future, tool vendors are also improving their respective technologies. For example, using Applied Materials’ CD-SEM, IBM conducted measurements in a theoretical gate-all-around finFET with silicon nanowires. In this experiment, “you see nice defined edges, even when you are beyond the resolution image,” said Ofer Adan, managing technology and marketing manager at Applied Materials. “So can we go beyond 14nm? What this work tells me is that a CD-SEM can go down to 6nm on a gate-all-around device.”

This is not to say the CD-SEM can handle all finFET requirements. “It cannot see whether or not there is an undercut. We need to work together with the OCD guys,” Adan said.

Overlay is another challenge and OCD is being stretched to the limits. KLA-Tencor recently unveiled a dimensional metrology system, which includes a new OCD technology based on a laser-driven source. “We think this is an inflection point for scatterometry,” said Andrei Shchegrov, director of advanced development at KLA-Tencor. “Our signal-to-noise gets a huge boost across a very wide range of wavelengths. We found the increased sensitivity due to the light source allows us to see things we couldn’t see before. It allows us to measure deep structures like high-aspect ratio 3D NAND flash.”

Despite the breakthroughs, the industry is still searching for new and better 3D metrology solutions. There are some promising candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging. And X-ray scattering (CD-SAXS) could succeed OCD.

“The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said IBM’s Solecky. “So the question is, ‘Do you need 3D information on the smallest features?’ The answer is yes. Potentially, helium ion is the solution.”

Helium ion enables 3D images, but the technology also can damage a device. The industry is looking for ways to tweak the helium ion microscope, which would make it somewhat comparable to the CD-SEM. “Technically, this involves a lot of challenges to make (helium ion into) a CD-SEM kind of tool. Those are not unsolvable problems, but it requires a lot of investments,” said Bipin Singh, product manager for Zeiss, a supplier of helium ion scopes and other fab tools.

As a replacement for OCD, the industry is looking at CD-SAXS, an X-ray scattering technology based on a synchrotron radiation source. “If you want 3D structures, you can certainly do it with CD-SAXS,” said Joseph Kline, a materials engineer at NIST. “The main limiter for CD-SAXS is throughput. Most of the measurements with CD-SAXS are done with a synchrotron source. Clearly, we are not going to have something like this in the fab. We are trying to figure out how to get a new source and make it work.”

There are other major gaps in metrology. For example, the current buzz in lithography centers on DSA, but it’s unclear if the industry has a metrology solution. “Metrology needed for DSA is really not different than the metrology needed for the rest of the industry,” said Applied’s Bencher. “You need to measure the registration of the holes. Now, when you are defining all of your holes by a mask, things tend to shift systematically, at least within the mobile region of the wafer. So how do you obtain an overlay measurement when things on the local level are shifted randomly? That’s not clear. It requires a different way of thinking.”

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus
The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing.

Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology.

For years, inspection and metrology tool vendors have managed to stay one step ahead of the defect curve. But as chipmakers migrate toward finFETs, 2.5D/3D chips and other complex structures, process control will become even more challenging and costly.

In fact, three key process control tools, CD-SEMs, brightfield defect inspection and optical scatterometry, may soon run out of steam, prompting the need for a new class of 3D metrology gear. “When we get to the 14nm node, we may be able to get by with what we have,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries. “As you get to 10nm, we might need a new technology.”

Next-generation 3D metrology tools exist to some degree, but the industry must make substantial investments to bring these technologies into production. And that’s precisely where the problem, and tension, exists between chipmakers and tool vendors. To develop new tools, equipment vendors want a bigger piece of the R&D pie and want customers to assume more of the risk.

“Different business models are definitely needed,” said Chris Talbot, senior director of strategic licensing at Applied Materials. “As the industry consolidates, with 450mm and EUV on the horizon, the amount of R&D that needs to be done not just in metrology and inspection, but right across the equipment industry, is enormous.”

One idea is to replicate ASML Holding’s recent and blockbuster business deal. Intel, Samsung and TSMC recently invested millions of dollars in ASML to speed up the development of extreme ultraviolet (EUV) lithography and 450mm tools. The three chipmakers also took minor stakes in ASML.

“The investments made by Intel and others in ASML are huge to solve an enormous problem,” Talbot said. “This is maybe one of the things we need to look at for other segments of the industry.”

Wanted: New business models
It’s unlikely that the inspection/metrology industry, or other fab tool sectors, will garner the same level of funding as the ASML deal. Lithography is considered the key manufacturing technology in IC scaling, and it will require a substantial investment to propel the development of EUV and 450mm lithography tools.

In the process control sector, the industry is providing substantial funding to KLA-Tencor, Zeiss and others for the development of EUV mask inspection tools. But beyond EUV, the industry may need to rethink the R&D funding model.

For years, chipmakers, consortia, venture capitalists and even governments have provided various levels of funding to equipment vendors for the development of new fab tools. Generally, the fab tool vendors themselves have assumed a larger percentage of the R&D bill and assumed more of the risk.

Today, however, tool vendors can no longer afford to develop a system on a whim and foot the R&D bill. The development costs, and the risks, are too high. After all, only a handful of chipmakers buy advanced tools today.

As before, there are no guarantees that a proposed tool will move into production. At times, equipment makers also fail to deliver the promised goods. But the real problem surfaces when a chipmaker demands a new system for a future node. An equipment maker complies and develops the system.

Then, in some cases, the IC maker decides not to insert the proposed tool. Instead, the company ends up extending the current technology. For this reason and others, the equipment maker ends up holding the bag. “If you look at the last 10 years, there are very few examples where a technology that we talked about was actually converted into a tool that we could put in our fabs,” acknowledged Alok Vaid, senior member of the technical staff at GlobalFoundries.

So, the time is ripe for a new R&D and risk-sharing model, although don’t look for an immediate change. “The industry has invested in time, resources and materials in process control,” said GlobalFoundries’ Allgair. “You’ve seen some investments through research consortiums. But we’re probably reaching the point where it needs to extend a little bit further than that. We should try to explore some different funding models.”

Given the enormous risks involved in tool development, chipmakers also must open the lines of communication and do a better job in conveying the exact types of technologies needed for a given node, he added.

Wanted: New metrology tools
Chipmakers are finally addressing the problems with the current R&D funding model, as some of today’s process control tools may soon hit the scaling wall. Fortunately, there are some promising next-generation candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging; meanwhile, multi-beam e-beam inspection could displace brightfield inspection. And X-ray scattering (CD-SAXS) could succeed optical scatterometry.

In one area, Applied and KLA-Tencor are among the major suppliers of optical-based brightfield inspection tools. Used to find defects during transistor fabrication, brightfield is a technique that collects light reflected from a defect. In turn, the defect appears dark against a white background. Brightfield is often used in conjunction with single-beam e-beam inspection, which detects even smaller defects.

As chips move to finer feature sizes, brightfield may have trouble seeing smaller defects. “It’s believed that 20nm is a critical particle size in which scattering falls off,” said Benjamin Bunday, senior technical staff member at Sematech. “E-beam inspection can see 5nm particles. But, of course, the throughput is too slow.”

Still, the death of optical and single-beam e-beam inspection is greatly exaggerated, said Mingwei Li, director of product marketing at KLA-Tencor. “Even with today’s wavelengths in optical inspection, we are detecting defects in the range of 10nm,” Li said. “We are not very far off with the ITRS roadmap, which specifies 5nm defects. We also think e-beam has a place.”

One possible successor to brightfield is multi-beam e-beam inspection technology. Multiple beams can boost inspection throughputs, but the technology is difficult to develop and control.

One startup, Multibeam, is developing a 100-column e-beam inspection system. Multibeam’s technology will not replace today’s optical and single-beam e-beam inspection, but rather it is a complementary approach, said David Lam, a venture capitalist and chairman of Multibeam. “We’re focusing on detecting small physical defects that are almost indistinguishable to noise,” Lam said.

Perhaps the biggest challenge for startups like Multibeam is clear—getting funding. “It is indeed very difficult to get funding,” Lam said. “Semiconductor equipment, in particular, is considered passé. It’s something that’s takes too much money. You can’t go IPO. It’s a very unattractive investment for investors.”

Multibeam is not looking for a handout, but the startup needs some backing to advance its tool. “I don’t think it will take $3 billion or $4 billion in funding like EUV. I’d say tens of millions of dollars,” he added.

Besides a new inspection technology, the IC industry is also looking for a next-generation scatterometry tool. Scatterometry analyzes changes in the intensity of light in a device, but the shift towards finFETs presents a challenge for the technology.

As a replacement, the industry is looking at CD-SAXS, a technique that uses a shorter wavelength to measure structures. The downfall with CD-SAXS is that it makes use of a synchrotron radiation source. “CD-SAXs is too slow,” said GlobalFoundries’ Allgair. “We need a new high-brightness source and faster measurement times.”

Another tool under stress is the scanning electron microscope (CD-SEM), which measures critical dimensions in chip structures. “The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said Eric Solecky, senior manufacturing engineer at IBM.

There is one solution on the table. In 2006, Carl Zeiss acquired Alis, a supplier of helium ion microscopy. The technology was supposed to provide better resolutions than CD-SEMs. “We thought we would go to the semiconductor market and solve all of their problems,” said Bipin Singh, product manager for Zeiss. “It turns out the traditional CD-SEM was good enough. The list price for a helium ion microscope was $2.1 million. The industry wasn’t willing to bear the costs.”

Last year, Zeiss decided to focus its helium ion microscopes for nanotechnology fabrication. But as the IC industry moves towards finFETs, some are once again looking at helium ion as a possible replacement for CD-SEMs.

Applied, Hitachi and other CD-SEM suppliers are not throwing in the towel just yet. “The case for helium ion is a bit fuzzy,” said Applied’s Talbot. “Conventional CD-SEMs are getting older, but they are still doing the job and are extendable.”

Probing Lithography
The Imperial College London and Ilmenau University of Technology have made some advances in the development of scanning probe lithography. Claiming resolutions down to 5nm and beyond, the technology combines the best of high-resolution scanning probe and nanoimprint lithography.

Sometimes called dip pen lithography, scanning probe lithography utilizes the same nanoprobe used in an atomic force microscope (AFM). The AFM is used to pattern nanometer-scale features. The AFM also enables the direct write of features into calixarene molecular resist. Then, researchers use a confined, development-less resist removal process via emission of low-energy electrons. An AFM post-imaging process is used for final in-situ inspection.

Researchers demonstrated a tiny pattern written in 10nm 4M1AC6 resists, with 40V bias voltage and 30nC/cm line dose. With the technology, scanning probe lithography could be a candidate for the production of finFETs with silicon nanowires at 10nm resolutions.

Figure 1. (a) Development-less, positive-tone closed-loop scanning probe lithography (SPL) on calixarene-based molecular glass resist, using self-actuating, piezoresistive scanning probes. (b) Scanning electron microscopy image of a corner pattern written in 10nm-thick 4M1AC6 resist, with 40V bias voltage and 30nC/cm line dose.4(c) Atomic force microscopy image of lithographic test features written with 30V bias voltage and a line dose of 32nC/cm (broad lines) and 20nC/cm (small lines), respectively. The image was taken directly after lithography with the same cantilever. Source: SPIE

Researchers also see applications in the development of quantum-effect devices, such as single-electron transistors and quantum-dot structures. Using a combination of lithography and material morphology, researchers have fabricated room-temperature single-electron transistors using e-beams and silicon nanocrystals at about 10nm in size.

DSA Hard Drives
Sputtering has been one of the main techniques to enable magnetic media on today’s hard disk drives. The next round of high-capacity drives could be based on an entirely new technology, including bit-patterned media (BPM) or heat-assisted magnetic recording (HAMR).

HGST, formerly Hitachi Global Storage Technologies, continues to explore the development of BPM. Now owned by Western Digital, HGST has combined directed self-assembly (DSA) and nanoimprint lithography to create large areas of dense patterns of magnetic islands at 10nm widths. In partnership with Molecular Imprints, a nanoimprint lithography vendor, HGST has devised dense patterns of magnetic islands in about 100,000 circular tracks.

Self-assembling molecules, called block copolymers, are composed of segments that repel each other. In self-assembly, a pre-pattern or guide is developed. After polymer patterns are created, a process called line doubling is implemented. This makes the tiny features even smaller, creating two separate lines where one existed before.

The patterns are then converted into templates for nanoimprinting. HGST has combined self-assembling molecules, line doubling and nanoimprinting to make rectangular features as small as 10nm in a circular arrangement. When extended to an entire disk, the nanoimprinting process is expected to create more than 1 trillion discrete magnetic islands.

“We made our ultra-small features without using any conventional photolithography,” said Tom Albrecht, an HGST fellow, on the company’s Web site. “With the proper chemistry and surface preparations, we believe this work is extendible to ever-smaller dimensions.”

Pellicle Island
For years, photomask makers have used a pellicle to protect a mask from particle contamination. Used in the production of today’s photomasks in optical lithography, a pellicle is a thin film material that is stretched on a frame.

One of the problems with extreme ultraviolet (EUV) lithography is that the technology lacks a pellicle. This means that particles could invade an EUV mask, thereby disrupting the photomask flow and threatening the overall viability of EUV. In fact, EUV generally requires a defect-free mask to enable the technology.

To solve the problem, ASML Holding has begun the development of pellicles for EUV masks. There are two possible types of pellicles for EUV masks—grid-supported and free standing. ASML is focusing on the free-standing approach, which itself consists of two materials options—polysilicon and a silicon/molybdenum/niobium multilayer. See slide 26 here.

To make the technology viable, an EUV pellicle must have a transmission rate at 90%. At present, ASML has achieved a transmission rate at 87%. In a simulated test, the pellicle was subjected to a 250 Watt source. “The results are promising,” said Luigi Scaccabarozzi, a research scientist at ASML “There was no damage to the (EUV scanner).”

—Mark LaPedus