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Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016


By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.

Synopsys Debuts Tools at Users Group Meeting

Wednesday, March 30th, 2016

By Jeff Dorsch, Contributing Editor

Aart de Geus, the chairman and co-chief executive officer of Synopsys, speaking at the keynote address Synopsys Users Group Meeting

Aart de Geus, the chairman and co-chief executive officer of Synopsys, used his keynote address at the 2016 Synopsys Users Group conference in Silicon Valley to tout a pair of new products.

Custom Compiler is one new tool. It promises to provide what the company calls “visually-assisted automation” in designing custom ICs.

Custom chip designers have asked, ‘Where are the productivity improvements?” for their line of work, de Geus said Wednesday morning (March 30) at the Santa Clara Convention Center.

Designing advanced chips with 3D transistors, FinFETs, adds complexity to the design process, he noted, with “many more rules” and transistors that have “many fins.”

Custom Compiler offers visually-assisted layout with interactive placement and routing, the Synopsys chairman said. The tool’s capabilities “can bring significant productivity,” he added.

To go with Custom Compiler, Synopsys last week introduced the VCS Cheetah simulation tool for system-on-a-chip designs. As part of the VCS verification suite, Cheetah adds the “fastest engines,” unified compile, and unified debug for complex IC designs, de Geus said.

Cheetah employs fine-grained parallelism and advances in CPU/graphics processing unit architectures to speed up simulation for register-transfer level and gate-level designs, according to Synopsys.

De Geus began his keynote saying, “We are going to change the world again.” By “we,” he meant Synopsys, its customers, and its partners in addressing chip design for the Internet of Things, automotive electronics, and other areas.

IoT, he said, can also stand for “immensely optimistic thinking,” to the general amusement of the large audience for the opening keynote. “Deep down, I’m a great optimist,” de Geus added.

Taking “Smart Everything” as his theme, de Geus moved on to the topic of digital intelligence, which is less ambitious than artificial intelligence. “Digital can do things humans cannot,” he said.

While some people will debate whether applications, the computing cloud, the networking edge, or “the fog” is the true center of attention for the IoT, de Geus broke it down to sensors with data storage and some data processing capability, “generating massive amounts of data” – Big Data, as it is commonly known.

Developing the Internet of Things calls for consideration of “technomics,” de Geus said. The impact of IoT technology will be “very long and very broad,” he said.

All of the hardware and software going into the IoT must be secure, according to de Geus, making sure that “the Internet of Threats” doesn’t take over the technology.

Synopsys has made a substantial investment in code security through its acquisition of Coverity and other moves, the Synopsys chairman said. He also addressed automotive-grade intellectual property for chip design and the introduction of data fusion in the IC design process.

“What we need is smart everybody,” de Geus concluded.

SNUG Silicon Valley 2016 continues through Thursday with 10 topic tracks and 52 presentations for Synopsys users. Almost 2,500 users are attending the two-day conference, it was said.

Chenming Hu, a University of California at Berkeley professor, is scheduled to give Thursday’s keynote address on “What Else Besides FinFET?”

Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

Thursday, March 17th, 2016

Mentor Graphics Corporation (NASDAQ: MENT) today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification. In addition, the Calibre and Analog FastSPICE platforms are ready for early design starts and IP design on TSMC’s 7nm FinFET process based on the most current Design Rule Manual (DRM) and SPICE model.

To help mutual customers prepare their designs for advanced manufacturing processes, Mentor has made improvements for 10nm physical verification, accelerating the runtime of the Calibre nmDRC™ sign-off tool compared to the tool’s runtime when it was initially certified for required 10nm accuracy last year. New device parameters of the 10nm process are supported in the Calibre nmLVS™ tool for more accurate SPICE models and self-heating simulation. Mentor has also enhanced the parasitic accuracy in the Calibre xACT™ solution, and is actively improving layout parasitic extraction flow to meet 10nm requirements.

The Calibre platform also helps designers improve design reliability and manufacturability. The TSMC reliability offering leverages the Calibre PERC™ reliability verification solution, now with enhanced techniques for 10nm resistance and current density checking. For design for manufacturing (DFM), Mentor added color-aware fill and more sophisticated alignment and spacing rules to the SmartFill feature of the Calibre YieldEnhancer tool. Mentor also optimized the Calibre DesignREV™ chip finishing tool, the Calibre RVE™ results viewer, and the Calibre RealTime interface to give designers easier integration and debugging capabilities for multi-patterning, layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) and reliability verification.

Mentor and TSMC are now collaborating on bringing the Calibre platform’s broad capabilities to the 7nm FinFET process. The Calibre nmDRC and Calibre nmLVS tools are already certified for customers’ early design starts. TSMC and Mentor are expanding use of the SmartFill functionality and Calibre multi-patterning capabilities to support the technology requirements of 7nm.

For fast, accurate circuit simulation, TSMC certified the AFS platform, including the AFS Mega circuit simulator, for 10nm V1.0. The AFS platform is also certified for the latest version of the 7nm DRM and SPICE for early design starts.

The Mentor place-and-route platform—including the Olympus-SoC™ system—has been enhanced to support advanced design rules at 10nm, and Mentor is optimizing its correlation with sign-off extraction and static timing analysis tools. This collaboration has also been extended to 7nm.

“We continue to collaborate with Mentor Graphics to provide design solutions and services that will help our mutual customers become successful with their 7nm designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Working together, we are also enabling the full production release of our 10nm technology design support.”

“To get the world’s most advanced processes into the hands of today’s leading SoC designers requires intense collaboration between the foundry and the EDA supplier,” said Joe Sawicki, vice president and general manager of Mentor Graphics Design-to-Silicon Division. “We’re honored that TSMC continues to leverage the proven quality, performance and breadth of Mentor platforms in its ecosystem strategy for the future.”

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016


By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

Applied Materials Prospers in CMP, Deposition, Etch

Tuesday, October 6th, 2015


By Jeff Dorsch, Contributing Editor

Applied Materials covers the waterfront when it comes to wafer fabrication equipment, especially when it comes to chemical mechanical planarization, deposition, and etching systems.

The company, founded in 1967, has a Silicon Systems Group which last year accounted for 66 percent of Applied’s revenue. The SSG includes a number of other wafer fab equipment categories, such as epitaxy, ion implantation, metrology and wafer inspection, rapid thermal processing, and wet cleaning.

Applied refreshes its product lines on a regular basis. New deposition and etch systems were introduced in July at the SEMICON West conference and exhibition, while the company’s latest CMP system was rolled out a year earlier, also at “West.”

Steve Lassig, global product manager for Etch Products at Applied, notes that the first 300-millimeter etchers emerged on the market 15 to 20 years ago. “The geometries have shrunk” since then, from 180 nanometers to 10nm, he says.

Applied Centris Sym3 Etch system

The Applied Centris Sym3 Etch system, debuted in the summer, features a “brand-new etch chamber for 10 nanometer and beyond,” Lassig says. “It’s the first new etch chamber for 300-millimeter etching.”

The Sym3 offers the high aspect ratio needed for manufacturing the 3D features of current chips — FinFETs on logic devices, 3D NAND flash memory devices, and advanced DRAMs, according to Lassig. It can deal with aspect ratio-dependent etching and handle dimensional loading effects and pattern loading effects, he adds.

Applied has shipped about 300 Sym3 chambers, with the etch chambers incorporating the company’s True Symmetry technology for extreme symmetry issues, Lassig says.

Applied has paid special attention to chamber materials, process gases, and wafer materials in designing the Sym3, according to Lassig. “This is one area where we’ve excelled,” he asserts.

Customers are typically using silicon and silicon germanium substrates at present, and Applied will be ready for gallium arsenide and carbon nanotubes when those materials become more commonplace in semiconductor manufacturing, Lassig says. “We’ve already been etching amorphous carbon, carbides,” he adds. “Etching carbon is pretty easy.”


Applied Olympia ALD system

David Chu, senior director of strategic marketing for Deposition Products, touts the capabilities of the new Applied Olympia ALD system for atomic-level deposition. “ALD has been around for quite a while, the past 20 years or so,” he says. The system offers excellent thickness control and the capability to alternatively handle two different chemistries, Chu adds.

While ALD is typically slower than chemical vapor deposition and physical vapor deposition systems, it is well-suited to 3DIC features like FinFETs, he says.

“Our product offering is a new, novel way to do the ALD process,” Chu says of the Olympia tool. It is a spatial ALD system, separating deposition steps by space, rather than time.

The Applied executive offers a colorful analogy for this ALD system, compared with its predecessors. To paint a board purple in a garage, the old way would be to paint the entire garage red, open the door to let out the fumes, and then paint the entire garage blue.

With spatial ALD, the board is painted with spray can of blue paint, then a spray can of red paint, and the colors are alternated for several steps, without having to open the garage door — or to paint the entire garage, Chu points out. The board continuously moves underneath the spray cans.

With the Olympia, the wafers rotate under modules in a carousel or merry-go-round, according to Chu. The system has the capability to use multiple modules.

“More and more applications require ALD,” Chu notes. Spatial ALD “helps to reduce cost,” he adds.

“The need for new materials is growing tremendously,” Chu says. “We’re going beyond carbide, silicon dioxide.”

Applied Reflexion LK Prime CMP system

The Applied Reflexion LK Prime CMP system was introduced in July of 2014. Customer adoption of the new gear has gone “exceptionally well,” says Sidney Huey, global product manager for CMP Products. “It was a combination of productivity and performance. Customers gravitated to it.”

When it comes to CMP technology, there has been “tremendous activity in the logic area,” Huey notes. “Customers are moving from planar structures,” at the 28nm process node, to the 3D FinFETs of logic devices, he adds.

“We’re carrying over all the challenges of planar, such as metal gates, plus 3D structures,” Huey says. Three-dimensional features involve “additional steps for FinFETs,” and “added steps mean added costs,” he notes.

In designing the Prime CMP system, “cost control was even more of a challenge,” Huey says. “Other integration steps have to happen. Many more deposition layers have to be polished. The number of CMP steps is growing.”

Interconnects are transitioning from copper to cobalt to ruthenium, according to Huey, while contacts are moving from tungsten to cobalt.

With chip interfaces, “more attention is being paid to materials,” Huey says. “Interfaces are so thin.”

Wafer surface topography is also becoming more of a concern. “Customers are looking at the atomic level,” Huey says. “They don’t want scratches, opens, shorts. They want a surface to be at a certain roughness.”

Risto Puhakka, president of VLSI Research, says Applied Materials is “doing good.” Among devices, “3D NAND (flash memory) is driving CVD and etch,” he adds. “Applied is doing very well with those products.”

The company’s financial results have been “very strong in the last four or five quarters,” Puhakka says. “There are so many moving parts” to Applied, he notes.

Calling off the proposed merger with Tokyo Electron Ltd. (TEL) last spring was a beneficial event for Applied, according to Puhakka. “It enables the company to refocus,” he says. “Management focus is back to the products.”

With the two-year effort to combine with TEL now over, “product people are reporting directly to Gary Dickerson,” Applied’s president and CEO, Puhakka observes.

At the same time, “competition is tough” for Applied, Puhakka says. “Lam (Research] is a great company, as well. TEL is, too.”

While Applied is enjoying “a balanced, strong marketplace,” there are signs that some areas of the wafer fab equipment field are “slowing dramatically,” Puhakka notes. “DRAM seems to be slowing; 3D NAND is still strong.”

Whatever happens in the near future, Applied Materials seems poised to weather any storms, as it has for the past 48 years.

GlobalFoundries CTO Calls for Innovation in Chip Materials

Thursday, September 24th, 2015

GlobalFoundries CTO Gary Patton

By Jeff Dorsch, Contributing Editor

“It’s really all about materials innovation,” said Gary Patton, chief technology officer of GlobalFoundries and head of the company’s worldwide research and development, in his keynote address on Tuesday at SEMI’s Strategic Materials Conference in Mountain View, Calif.

The semiconductor technology landscape looks challenging and even daunting at the moment. “We always figure out how to keep going,” Patton told the overflow audience.

The industry has reached “the end of the planar device era,” he added, and entered into “the 3D era,” with 3D chips and 3D stacking of chips in packaging.

Ahead in the not-too-distant future lies “the atomic era” of carbon nanotubes and other materials to replace silicon, Patton said, a theme that was reinforced over the conference’s two days, surrounded by information technology artifacts in the Computer History Museum.

Extreme-ultraviolet lithography is “a key challenging technology,” Patton observed. “We need to make it happen. EUV will take us into the 2020s.”

Double-patterning with immersion lithography will usher the industry into the 10-nanometer process node, according to the GlobalFoundries technologist. Implementing EUV will simplify a number of aspects of lithography, such as the multiple photomasks involved. “EUV will take us back to the 45-nanometer era,” Patton said.

He reviewed several areas of semiconductor manufacturing that will be changing in the near future, from the front end to the back end.

It was nearly three months ago that GlobalFoundries completed its acquisition of IBM Microelectronics. Patton served as vice president of IBM’s Semiconductor Research and Development Center for eight years prior to joining GlobalFoundries in July.

In his keynote, he touted the network of New York’s “Tech Valley,” taking in GlobalFoundries’ facilities in Malta, N.Y.; the Albany NanoTech Complex; and the former IBM chip facilities in East Fishkill, N.Y., and Burlington, Vt. “What we develop in Albany, we run in Malta,” Patton said.

GlobalFoundries, with its academic and industry partners, has 23 joint development projects in Albany, Patton noted, and is open to even more.

In an interview on Wednesday, Patton emphasized the development of “differentiated technologies” with the integration of IBM’s chip manufacturing operations. In addition to supplying processors for IBM’s server business over the next decade, GlobalFoundries also has IBM’s radio-frequency chip business, silicon germanium-based devices, power amplifiers, RF silicon-on-insulator technology, ASICs, and chips for wired communications, Patton noted.

The foundry is “ramping 14-nanometer technology” and working with Samsung Electronics on FinFET processes, Patton said. While the 14nm FinFET process covers advanced semiconductors, GlobalFoundries can also make lower-power parts with its 22nm fully-depleted SOI process, using the 22FDX platform.

GlobalFoundries was able to maintain the Trusted Foundry relationship with the U.S. Department of Defense with the IBM Microelectronics acquisition, according to Patton, and one business unit is devoted to aerospace and defense customers.

Asked about the delayed Fab 8.2 expansion in Malta, Patton said resumption of the project would depend on business conditions in the industry. “We’ll invest at a better time,” he said.

And what about the report concerning a Chinese financial entity approaching GlobalFoundries about a possible acquisition? “I have no knowledge of that,” Patton said.

Samsung to put 10nm chips into mass production by end of 2016

Friday, May 22nd, 2015


By Jeff Dorsch, Contributing Editor

Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.

At an event in San Francisco, the Samsung Electronics subsidiary exhibited a 12-inch wafer with what it said were 10nm FinFET semiconductors. Over the next 18 months, Samsung will provide process design kits and multi-die wafers for the 10nm FinFET chips.

Samsung Semiconductor is also ramping up volume production of 14nm FinFET chips at its S1 wafer fabrication facility in South Korea and its S2 fab in Austin, Texas, while preparing the S3 fab in South Korea for 14nm FinFET volume production. In addition, GlobalFoundries will implement the Samsung 14nm FinFET process at its chip-making facilities in New York State.

“We are in business for 14-nanometer FinFET,” said Hong Hao, senior vice president for Samsung’s foundry business. “We have brought broad competition back into the foundry business.”

Samsung Foundry has closely matched Taiwan Semiconductor Manufacturing in providing 14nm and now 10nm chips.

Hao said Samsung will support “a broad range of applications” with chips coming out of its foundry fablines – consumer electronics, mobile devices, computing, networking, and data center infrastructure.

He also noted that Samsung is offering a 28nm fully-depleted silicon-on-insulator process, licensed from STMicroelectronics.

Samsung Semiconductor executives made brief presentations on other product areas for the chipmaker, and also reported on progress in constructing the company’s new facility in northern San Jose, Calif., which will be occupied this summer.

Solid State Watch: April 3-9, 2015

Friday, April 10th, 2015
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Synopsys founder has plenty of work to do, isn’t interested in politics

Thursday, March 26th, 2015


By Jeff Dorsch, Contributing Editor

Aart de Geus is not running for governor of California.

The Synopsys chairman and co-CEO denied that speculation in meeting with journalists Monday morning at the 25th annual Synopsys Users Group Conference in Santa Clara, Calif. In any case, Governor Jerry Brown just began his last four-year term, and there’s not another gubernatorial election in the Golden State until 2018.

“I have a life so interesting,” de Geus said during an hour-long, freewheeling discussion of mostly technical topics. In addition to leading the electronic design automation, intellectual property, and software firm he founded in 1986, which had fiscal 2014 revenue of $2.057 billion, de Geus serves as the guitarist of Legally Blue, a blues band that regularly performs in Silicon Valley.

The political process in Sacramento and Washington, D.C., is plagued by “diffraction,” de Geus observed, leaving little or no public consensus on important issues, such as climate change and water supplies. Synopsys has provided corporate philanthropy for public education in the valley and the Second Harvest Food Bank, among other causes and charities. De Geus said he personally supports the Environmental Defense Fund and Human Rights Watch.

As he noted earlier in the morning during his SNUG keynote address, de Geus spoke about the hardiness of Moore’s Law, which is often proclaimed to be dead.

“For 15 years, analysts have predicted the next chip is impossible,” he said. He recalled that while he was a student 37 years ago, semiconductor experts generally agreed that the industry would never produce chips with dimensions smaller than 1 micron.

“Everything is a constraint problem,” he commented. “It’s always been like that.”

De Geus added, “I have been surprised by how quickly FinFET has caught on.” Later on Monday, Synopsys customers testified about how they have designed chips with FinFETs using Synopsys tools.

Asked about the implementation of fully-depleted silicon-on-insulator technology, de Geus said, “The jury is still out.” He added, “We are seeing design starts.”

The complexity of semiconductor design and manufacturing is increasing, de Geus acknowledged. “Of course it’s getting hard,” he said. The industry will go through the usual period of hand-wringing about technical challenges, according to de Geus. “Then, we nail it!”

Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

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