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Posts Tagged ‘FET;’

5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

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At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Research Alert: May 6, 2014

Tuesday, May 6th, 2014

Probing dopant distribution

One method of altering the electrical properties of a semiconductor is by introducing impurities called dopants. A team led by Delia Milliron, a chemist at Berkeley Lab’s Molecular Foundry, a U.S Department of Energy (DOE) national nanoscience center, has demonstrated that equally important as the amount of dopant is how the dopant is distributed on the surface and throughout the material. This opens the door for engineering the distribution of the dopant in order to control what wavelength the material will absorb and more generally how light interacts with the nanocrystals.

“Doping in semiconductor nanocrystals is still an evolving art,” says Milliron. “Only in the last few years have people begun to observe interesting optical properties as a result of introducing dopants to these materials, but how the dopants are distributed within the nanocrystals remains largely unknown. What sites they occupy and where they are situated throughout the material greatly influences optical properties.”

Milliron’s most recent claim to fame, a “smart window” technology that not only blocks natural infrared (IR) radiation while allowing the passage of visible light through transparent coated glass, but also allows for independent control over both kinds of radiation, relies on a doped semiconductor called indium tin oxide (ITO).

ITO, in which tin (the dopant) has replaced some of the indium ions in indium oxide (the semiconductor), has become the prototypical doped semiconductor nanocrystal material.  It is used in all kinds of electronic devices, including touchscreens displays, smart windows and solar cells.

“The exciting thing about this class of materials is that the dopants are able to introduce free electrons that form at high density within the material, which makes them conducting and thus useful as transparent conductors,” says Milliron

But the same electrons cause the materials to be plasmonic in the IR part of the spectrum. This means that light of IR wavelength can be resonant with free electrons in the material: the oscillating electric fields in the light resonate and can cause absorption.

“[These materials] can absorb IR light in a way that’s tunable by adjusting the doping, while still being transparent to natural visible light. A tunable amount of absorption of IR light allows you to control heating.  For us, that’s the driving application,” explains Milliron.

Until now, adjustments have been made by changing the amount of dopant in the semiconductor. Puzzled by studies in which optical properties did not behave as expected, Milliron and University of California (UC) Berkeley PhD candidate Sebastien Lounis looked to x-ray photoelectron spectroscopy to probe electrons near the surface of the ITO samples and investigate the distribution of elements within the samples at the Stanford Synchrotron Radiation Lightsource (SSRL).

The SSRL uses a tuneable beam of photons to excite electrons inside the material. If the electrons are close enough to the surface, they can sometimes be emitted and collected by a detector. These electrons provide information about the properties of the material, including the ratio of the amounts of different elements like indium and tin in ITO. Increasing the energy of the x-ray beam shows how the composition of tin and indium changes as one moves deeper into the sample. Ultimately, the spectroscopy technique allowed Milliron and her team to probe the doping distribution as a function of distance from the nanocrystals’ surface.

An edgy look at molybdenum disulfide

Researchers with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) have recorded the first observations of a strong nonlinear optical resonance along the edges of a single layer of molybdenum disulfide. The existence of these edge states is key to the use of molybdenum disulfide in nanoelectronics, as well as a catalyst for the hydrogen evolution reaction in fuel cells, desulfurization and other chemical reactions.

“We observed strong nonlinear optical resonances at the edges of a two-dimensional crystal of molybdenum disulfide” says Xiang Zhang, a faculty scientist with Berkeley Lab’s Materials Sciences Division who led this study. “These one-dimensional edge states are the result of electronic structure changes and may enable novel nanoelectronics and photonic devices. These edges have also long been suspected to be the active sites for the electrocatalytic hydrogen evolution reaction in energy applications. We also discovered extraordinary second harmonic light generation properties that may be used for the in situ monitoring of electronic changes and chemical reactions that occur at the one-dimensional atomic edges.”

For the SHG imaging of molybdenum disulfide, Zhang and his collaborators illuminated sample membranes that are only three atoms thick with ultrafast pulses of infrared light. The nonlinear optical properties of the samples yielded a strong SHG response in the form of visible light that is both tunable and coherent. The resulting SHG-generated images enabled the researchers to detect “structural discontinuities” or edges along the 2D crystals only a few atoms wide where the translational symmetry of the crystal was broken.

“By analyzing the polarized components of the SHG signals, we were able to map the crystal orientation of the molybdenum disulfide atomic membrane,” says Ziliang Ye, the co-lead author of the paper and current member of Zhang’s research group. “This allowed us to capture a complete map of the crystal grain structures, color-coded according to crystal orientation. We now have a real-time, non-invasive tool that allows us explore the structural, optical, and electronic properties of 2D atomic layers of transition metal dichalcogenides over a large area.”

This research was supported by the DOE Office of Science through the Energy Frontier Research Center program, and by the U.S. Air Force Office of Scientific Research Multidisciplinary University Research Initiative.

New rapid synthesis developed for bilayer graphene and high-performance transistors

Researchers at University of California, Santa Barbara, in collaboration with Rice University, have recently demonstrated a rapid synthesis technique for large-area Bernal (or AB) stacked bilayer graphene films that can open up new pathways for digital electronics and transparent conductor applications.

The invention also includes the first demonstration of a bilayer graphene double-gate field-effect transistor (FET), showing record ON/OFF transistor switching ratio and carrier mobility that could drive future ultra-low power and low-cost electronics.

Graphene is the thinnest known (~0.5 nanometer per layer) 2-dimensional atomic crystal. It has attracted wide interest due to its promising electrical and thermal properties and potential applications in electronics and photonics. However, many of those applications are significantly restricted by the zero band gap of graphene that results in leaky transistors not suitable for digital electronics.

“In addition to its atomically smooth surfaces, a considerable band gap of up to ~0.25 eV can be opened up in bilayer graphene by creating a potential difference between the two layers, and thereby breaking the inherent symmetry, if the two layers can be aligned along a certain (Bernal or AB) orientation” explained Kaustav Banerjee, professor of electrical and computer engineering and Director of the Nanoelectronics Research Lab at UCSB. “The dual-gated transistors were specifically designed to allow such potential difference to be established between the layers through one of the gates, while the second gate modulated the carriers in the channel,” he added. Banerjee’s research team also includes UCSB researchers Wei Liu, Stephan Kraemer, Deblina Sarkar, Hong Li and Professor Pulickel Ajayan of Rice University. Their study was recently published in Chemistry of Materials.

The graphene films were grown in a deterministic manner using an engineered bifunctional (Cu:Ni) alloy surface at a relatively low temperature of 920 °C. Large-area (> 3 inch × 3 inch) Bernal (or AB) stacked bilayer graphene growth was demonstrated within few minutes and with nearly 100% area coverage. The bilayer graphene films exhibited electron mobility as high as 3450 cm2/(V•s), which is comparable to that of exfoliated bilayer graphene, thereby confirming very high-quality. The quality of grown graphene was further corroborated by demonstration of high-performance FETs with record ON/OFF ratio that is a key requirement in low-power digital electronics.

“Achieving surface catalytic graphene growth mode and precise control of the surface carbon concentration were key factors for the favorable growth kinetics for AB stacked bilayer graphene,” explained Wei Liu, a post-doctoral researcher in Banerjee’s group and a co-author of the article. In 2011, Banerjee’s group demonstrated a large-area monolayer graphene synthesis method using a copper substrate as catalyst.

Bilayer graphene is close to monolayer graphene in terms of the film thickness with a hexagonal atomic structure and can be derived from its layered bulk form (graphite) in which adjacent layers are held together by relatively weak van der Waals forces. “However, apart from its band gap tunability, bilayer graphene has some key advantages over monolayer graphene. It has higher density of states and suffers much less from interface effects, which are beneficial for improving the current carrying capability,” Liu continued.

“This demonstration is very impressive and should have far-reaching implications for the entire 2D materials community,” commented Professor Ali Javey, of University of California, Berkeley and a Co-Director of the Bay Area Photovoltaic Consortium (BAPVC).


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