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Posts Tagged ‘FDX’

GlobalFoundries Turns the Corner

Friday, September 29th, 2017

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By David Lammers

Claiming that GlobalFoundries “is a different company than two years ago,” executives said the foundry’s strategies are starting to pay off in emerging markets such as 5G wireless, automotive, and high-performance processors.

CEO Sanjay Jha, speaking at the GlobalFoundries Technology Conference, held in Santa Clara, Calif. recently, said that to succeed in the foundry segment requires that customers “have confidence that they are going to get their wafers at the right time and with the right quality. That has taken time, but we are there.”

CEO Sanjay Jha: “differentiated” processes are key.

Innovation is another essential requirement for success, Jha said, arguing that R&D dollars must include spending on “differentiated” approaches. Alain Mutricy, senior vice president of product development, acknowledged that only recently have customers turned to GlobalFoundries as more than just a second-source to TSMC. For the first few years, “most companies used us to keep (wafer) prices down,” he said, while noting GlobalFoundries bears some responsibility for that by not investing nearly enough, early on, in IP libraries and EDA tool development.

Founded in March 2009 as a spinout of the manufacturing arm of Advanced Micro Devices, Global Foundries’ Abu Dhabi-based owner soon acquired Singapore’s Chartered Semiconductor in January 2010, and further expanded through the July 2015 acquisition of IBM Microelectronics. It is now engaged in building what Jha said will be the largest wafer fab in China, in Chengdu, capable of processing a million wafers a year. The Chengdu fab, operated by GlobalFoundries but with investments from the local government, will begin with 180nm and 130nm products now fabbed in Singapore, and then add 22FDX IC production to meet demand from Chinese customers.

While the road to profitability has been a hard one, Len Jelinek, chief technology analyst at HIS Markit, said GlobalFoundries is now “cash flow positive,” with the flagship Malta, N.Y. fab “essentially full” at an estimated 40,000 wafer starts per month. That is a big turnaround from four years ago, he said.

Malta fab’s capacity doubling

Nathan Brookwood, longtime microprocessor watcher at Insight64, said while AMD no longer has an ownership stake in GlobalFoundries, it does have wafer supply agreements with the foundry. The fact that AMD’s Zen-based microprocessors and newest graphics chips are all made on the 14nm Finfet process at Fab 8 “means that AMD is now actually using the wafer supply it is committed to taking. That helps both companies.”

Andrea Lati, director of market research at VLSI Research, said while TSMC “is clearly a very well-run company that is marching ahead,” GlobalFoundries also is making progress. Again, AMD’s success is a large part of that, Lati said, noting that “AMD is definitely doing very well for the last couple of years, and has good prospects, along with Nvidia, in the graphics side.”

In a telephone interview, Tom Caulfield, senior vice president and general manager of the GlobalFoundries’ Malta fab, said “we are continually adding capacity in 14nm as we get a window on to the demand from our customers. In 2016 and 2017 we made additional investments.”

While not putting a specific number on Malta’s capacity, Caulfield said that if the beginning of 2016 is taken as a baseline, by the end of 2018 the wafer capacity at Malta’s Fab 8 will have more than doubled.

“AMD refreshed its entire portfolio with 14nm, exclusively made here at Malta, and we are chasing more demand than we planned on. AMD’s success is a proxy for our success. We are in this hand in hand,” Caulfield said.

Asked if a new fab was being considered at Malta, Caulfield said “At some point we will need more brick and mortar. Eventually we will run out of space, but we still have some time in front of us.

FDX in the wings

Scotten Jones, who runs a semiconductor cost modeling consultancy, IC Knowledge LLC, said competition is also heating up at the 28nm node, once controlled almost exclusively by TSMC. As GlobalFoundries, Samsung — and more recently, SMIC and UMC — have ironed out their own 28nm processes, the profitability of TSMC’s 28nm business has tightened, Jones said.

The competitive spotlight is now on the 22FDX SOI-based process developed by GlobalFoundries, buttressed by an embedded 22nm eMRAM capability developed along with MRAM pioneer Everspin Technologies.

Gary Patton, chief technology officer at GlobalFoundries, said the SOI-based 22nm node supports forward biasing, while the 12nm FDX technology will support both forward and back-biasing, to either boost performance or conserve power. Patton said the 12FDX process will provide 26 percent more performance and 47 percent less power consumption than the 22FDX process, with prototypes expected in the second half of 2018 and volume production beginning in 2019.

CTO Gary Patton: Technology development boosted by IBM engineers.

Patton said “maybe we haven’t done enough” to explain the differences between the 14nm FinFet technology and the SOI-based FDX technologies. The FinFET transistors have enough drive current to drive signals across fairly large die sizes, while the FDX technology is best suited to die sizes of 150 sq. mm and smaller, he said.

Jones said his cost analysis shows that the design costs for the planar FDX chips are much less expensive than for FinFETs, which require “some fairly expensive EDA tools.” That combines with a much smaller mask count, due to multi-patterning.

Patton said the 22FDX designs require 40 percent fewer masks that comparable 14nm FinFET-based designs. “With the SOI technology customers have the option of using body biasing, which has been used in the industry for the past three or four years. We can operate at .4 Volts, and customers are putting RF on the same chip as digital.”

Asked if he thought the FDX processes would gain traction in the marketplace, Jones answered in the affirmative. “I think it will find its place. It is still early. These kinds of new technologies take time to get established,” Jones said.

Jha said two companies have developed products based on 22FDX, Dream Chip Technologies, an advanced driver assistance system (ADAS) supplier, which last February said it has completed a computer vision SoC based on the 22FDX process, and Ineda Systems, which seeks to integrate RF and digital capabilities on its 22FDX-based processors, targeted at the Internet of Things market.

Mutricy said 70 companies purchased the 22FDX foundation IP provided by Invecas for the 22FDX process, with 18 tapeouts on track for production next year.

Patton said the addition of 500 technologists from IBM’s microelectronics division has aided the technology development operation. “GlobalFoundries is absolutely a different company than it was just two years ago,” Patton said at the GTC event.

Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016

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By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.