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Posts Tagged ‘FD-SOI’

Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

Blog review October 27, 2014

Monday, October 27th, 2014

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

Phil Garrou blogs that most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers. NANIUM also has extensive volume manufacturing experience in WB multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

Gabe Moretti says it is always a pleasure to talk to Dr. Lucio Lanza and I took the opportunity of being in Silicon Valley to interview Lucio since he has just been awarded the 2014 Phil Kaufman award. Dr. Lanza poses this challenge: “The capability of EDA tools will grow in relation to design complexity so that cost of design will remain constant relative to the number of transistors on a die.”

Are we at an inflection point with silicon scaling and homogeneous ICs? Bill Martin, President and VP of Engineering, E-System Design thinks so. I lays out the case for considering Moore’s Law 2.0 where 3D integration becomes the key to continued scaling.

Congratulations to Applied Materials Executive Chairman Mike Splinter on receiving the Silicon Valley Education Foundation’s (SVEF) Pioneer Business Leader Award for driving change in business and education philanthropy by using his passion and influence to make a positive impact on people’s lives.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. As Adele Hars reports, speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM.

Blog review October 20, 2014

Monday, October 20th, 2014

Matthew Hogan of Mentor Graphics blogs about how automotive opportunities are presenting new challenges for IC verification. A common theme for safety systems involves increasingly complex ICs and the need for exceptional reliability.

Anish Tolia of Linde blogs that technology changes in semiconductor processing and demands for higher-purity and better-characterized electronic materials have driven the need for advanced analytical metrology. Apart from focusing on major assay components, which are the impurities detailed in a Certificate of Analysis (CoA), some customers are also asking that minor assay components or other trace impurities must be controlled for critical materials used in advanced device manufacturing.

Karey Holland of Techcet provides an excellent review of SEMI’s Strategic Materials Conference. The keynote presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm. He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices.

The age of the Internet of Things is upon us, blogs Pete Singer. There are, of course, two aspects of IoT. One is at what you might call the sensor level, where small, low power devices are gathering data and communicating with one another and the “cloud.” The other is the cloud itself. One key aspect will be security, even for low-level devices such as the web-connected light bulb. Don’t hack my light bulb, bro!

Linde Electronics has developed the TLIMS/SQC System. Anish Tolia writes that this system includes an information management database plus SQC/SPC software and delivers connectivity with SAP, electronically pulling order information from SAP to TLIMS and pushing CoA data from TLIMS to SAP.

Ed Korczynski blogs about how IBM researchers showed the ability to grow sheets of graphene on the surface of 100mm-diameter SiC wafers, the further abilitity to grow epitaxial single-crystalline films such as 2.5-μm-thick GaN on the graphene, the even greater ability to then transfer the grown GaN film to any arbitrary substrate, and the complete proof-of-manufacturing-concept of using this to make blue LEDs.

Phil Garrou says it’s been awhile since we looked at what is new in the polymer dielectric market so he checked with a number of dielectric suppliers – specifically Dow Corning, HD Micro and Zeon — and asked what was new in their product lines.

Karen Lightman, Executive Director, MEMS Industry Group, had the pleasure to learn more about the challenges and opportunities affecting MEMS packaging at a recent International Microelectronics Assembly and Packaging Society (IMAPS) workshop held in her hometown of Pittsburgh and at her alma mater, Carnegie Mellon University (CMU).

Ed Korczynski blogs that The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources.”

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014) blogs Adele Hars.

Blog review September 8, 2014

Monday, September 8th, 2014

Jeff Wilson of Mentor Graphics writes that, in IC design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Is 3D NAND a Disruptive Technology for Flash Storage? Absolutely! That’s the view of Dr. Er-Xuan Ping of Applied Materials. He said a panel at the 2014 Flash Memory Summit agreed that 3D NAND will be the most viable storage technology in the years to come, although our opinions were mixed on when that disruption would be evident.

Phil Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out packaging (P-FO), Nanium’s eWLB Dielectric Selection, and an electronics contact lens for diabetics from Google/Novartis.

Ed Koczynski says he now knows how wafers feel when moving through a fab. Leti in Grenoble, France does so much technology integration that in 2010 it opened a custom-developed people-mover to integrate cleanrooms (“Salles Blanches” in French) it calls a Liaison Blanc-Blanc (LBB) so workers can remain in bunny-suits while moving batches of wafers between buildings.

Handel Jones of IBS provides a study titled “How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales” that concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics.

Gabe Moretti of Chip Design blogs that a grown industry looks at the future, not just to short term income.  EDA is demonstrating to be such an industry with significant participation by its members to foster and support the education of its future developers and users through educational licenses and other projects that foster education.

Blog review June 30, 2014

Monday, June 30th, 2014

Pete Singer blogs that at The ConFab last week, IBM’s Gary Patton gave us three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

Tony Chao of Applied Materials writes that Applied Ventures will be participating in the second-annual Silicon Innovation Forum (SIF) held in conjunction with SEMICON West 2014 in San Francisco on Tuesday, July 8. The forum is designed to bring new and emerging innovators together with the semiconductor industry’s top strategic investors and venture capitalists (VCs), in order to enable closer collaboration and showcase the next generation of entrepreneurs in microelectronics.

Adele Hars of ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. Malier said that CEA-Let has been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development.

Phil Garrou blogs that last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core.

Solid State Watch: May 9-15, 2014

Friday, May 16th, 2014
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ST licenses 28nm FD-SOI to Samsung

Friday, May 16th, 2014

By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

On May 14, 2014 it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

“Building upon the existing solid relationship between ST and Samsung within the framework of the International Semiconductor Development Alliance, this 28nm FD-SOI agreement expands the ecosystem and augments fab capacity for ST and the entire electronics industry,” said Jean-Marc Chery, COO, STMicroelectronics. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”

According to Handel Jones, founder and CEO of International Business Strategies Inc. (IBS), “The 28nm node will be long-lived; we expect it to represent approximately 4.3 million wafers in the 2017 timeframe, and FD-SOI could capture at least 25 percent of this market.”

Table 1 shows IBS data estimating costs for different 28nm fab process technologies.

“We are pleased to announce this 28nm FD-SOI collaboration with ST. This is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Seh-Woong Jeong, executive vice president of System LSI Business, Samsung Electronics. “28nm process technology is a highly productive process technology and expected to have a long life span based on well-established manufacturing capabilities.”

In June 2012, ST announced that GLOBALFOUNDRIES had joined the FD-SOI party for the 28nm and 20nm nodes. However, though the name has since changed from “20nm” to “14nm” (Table 2), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.

“Leti continues its development of further generations and our technology and design results show great promise for the 14nm and 10nm nodes,” said Laurent Malier, CEO of CEA-Leti (Laboratory for Electronics and Information Technology). Leti and ST are not against finFET technology, but sees it as complementary to SOI. In fact the ecosystem plans to add finFETs to the FD-SOI platform for the 10nm node, at which point Taiwanese foundry UMC plans to join.

FD-SOI Substrate Technology

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, supplies most of the world’s SOI wafers. Paul Boudre, COO of Soitec, commented, “Our FD-SOI wafers represent an incredible technology achievement, resulting from over 10 years of continuous research and high-volume manufacturing expertise. With our two fabs and our licensing strategy, the supply chain is in place and we are very excited by this opportunity to provide the semiconductor industry with our smart substrates in high volume to enable widespread deployment of FD-SOI technology.”

Soitec’s R&D of ultra-thin SOI was partly funded and facilitated by the major French program called “Investments for the Future.” Soitec has collaborated with CEA-Leti on process evolution and characterization, with IBM Microelectronics for device validation and collaboration, and with STMicroelectronics to industrialize and demonstrate the first products.

Boudre, in an exclusive interview with SST/SemiMD, explained, “For 28nm node processing we use a 25+-1nm buried oxide layer, which is reduced in thickness to 20+-1nm when going to the 14nm node and we don’t see any differences in the substrate production. However, for the 10nm node the buried oxide layer needs to be 15nm thin, and we will need some new process steps to be able to embed nMOS strain into substrates.”


The Week in Review: Nov. 29, 2013

Friday, November 29th, 2013
Soitec and SunEdison, Inc. announced today that they have entered into a patent cross-license agreement relating to silicon-on-insulator (SOI) wafer products.  The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all outstanding legal disputes between the companies. This agreement provides access to a portfolio of patents from both companies and covers the manufacturing of existing engineered unpatterned handle-substrates such as partially depleted SOI (PD-SOI), fully depleted SOI (FD-SOI) and radio-frequency SOI (RF-SOI) as well as advanced FinFETs.
The Semiconductor Industry Association announced that Assistant U.S. Attorney Sherri Schornstein is the recipient of the Anti-counterfeiting Task Force (ACTF) 2013 Distinguished Service Award in appreciation for her many years of service with the U.S. Department of Justice (DOJ) and her successful efforts to combat semiconductor fraud and counterfeiting.
Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, announced that IO Semiconductor Inc., a fabless semiconductor company, has selected the company’s Analog FastSPICE AMS for RF front-end mixed-signal design verification. The Analog FastSPICE Platform provides circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits.
CEA-Leti announced a development agreement that will utilize Leti’s MEMS expertise and leading-edge infrastructure with OMRON, a global leader in factory automation and control solutions for the transportation, healthcare and consumer-goods industries. While Leti has a Tokyo office and has partnered with Japanese companies and research organizations for many years, the agreement is Leti’s first collaboration with a Japanese MEMS producer.
PPG Industries and Universal Display Corporation marked the opening of a world-class organic light-emitting diode (OLED) materials production facility at PPG’s Barberton, Ohio plant. This new site, which PPG owns and operates, commenced manufacturing earlier this month and will foster the expanded development and production of Universal Display’s phosphorescent OLED (UniversalPHOLED) materials.

The Week In Review: Nov. 7, 2013

Friday, November 8th, 2013

Peregrine Semiconductor Corp. and GLOBALFOUNDRIES are sampling the first RF Switches built on Peregrine’s new UltraCMOS 10 RF SOI technologies. This partnership unites Peregrine’s 25 years of RF SOI experience with a tier-one foundry. In a joint development effort, GLOBALFOUNDRIES and Peregrine created a unique fabrication flow for the versatile, new, 130 nm UltraCMOS 10 technology platform. This new technology delivers a more than 50-percent performance improvement over comparable solutions. UltraCMOS 10 technology gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.

Peregrine Semiconductor this week celebrated two significant milestones – its 25th anniversary of pioneering RF SOI solutions and the shipment of the two-billionth chip. Peregrine reaches the two-billionth-chip milestone in an order to Murata Manufacturing Company, the supplier of RF front-end modules for the global mobile wireless marketplace.

Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters.  This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.

Semiconductor Research Corporation and Northeastern University researchers announced advancements in radio-frequency (RF) circuit technology that promise to improve and widen the applications of mobile devices.

Imec announced that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon.

STMicroelectronics announced this week its close collaboration with Memoir Systems has made the revolutionary Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully-depleted silicon-on-insulator (FD-SOI) process technology.

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FD-SOI Targets Mobile Applications

Monday, September 30th, 2013

GIORGIO CESANA, STMicroelectronics, Crolles, France and CARLOS MAZURE, Soitec, Bernin, France

The FD-SOI technology platform is perfectly suited for mobile IC applications where power consumption has to be very low to maximize battery lifetime.

The IC industry has been innovative with the introduction of new materials and process modules like stressors, high-k and metal gates (HKMG). It has been very conservative in keeping the bulk planar transistor structure. As a result, the planar transistor has become a highly doped device with decreasing dimensions. Moreover, at these smaller dimensions, transistor characteristics suffer from statistical fluctuations like random dopant fluctuations (RDF) in the channel, which impair device matching in sub-100nm circuits. This has become an important problem beyond node 28/32nm limiting VDD reduction, thus limiting the reduction of both dynamic and standby power consumption.

There is strong consensus in the IC community that fully depleted (FD) transistors, also known as Ultra Thin Body (UTB) devices, are an effective solution for reducing the VT variability caused by random dopant fluctuation (RDF). FD devices can be vertical, (FinFETs, 3D MOSFET) [1], or planar (FD-SOI) [2, 3]. Their key characteristic is that the silicon channel is undoped.

FD-SOI is an evolutionary innovation because it has the advantage of being a planar transistor structure that extends the applicability of bulk design flows with existing design and EDA tools. It is a non-disruptive MOSFET architecture change for SOC design and processing. FD-SOI requires ultra-thin Si (<20nm) over an ultra-thin buried oxide (BOX<25nm) for improved electrostatics [3]. FD technology brings numerous benefits for power reduction, area scaling and performance improvement while enabling a lower VDD [3]. The IC SOC community has accepted that technology nodes beyond 20nm will have to use fully depleted (FD) MOSFETs.

Pushing performance, Intel introduced the 3D transistors, FinFET, first in 2011 for CPU applications [1]. The foundry world, in contrast, was able to scale conventional bulk CMOS technology from to 28nm to 20nm. The gain in density came with a higher price per unit area and little performance gain, however. Indeed, beyond the 28nm node, CMOS technology has become more complex with double patterning (node 20nm) and with 3D FinFET devices (node 14/16nm). The performance gain from node to node is well below the 30% boost we have seen historically with scaling from a nodes n to the following n+1.

In this landscape, 28nm FD-SOI [4, 5] offers a very attractive value proposition: best low power at HKMG performance. In fact, 28nm FD-SOI gives the performance boost of scaling without changing the node. This is very interesting option for low-power ICs where area is not the driving factor and which could profit from a performance boost at constant or lower power consumption. Thus for many IC products moving to FD-SOI without changing the node can be very attractive from a power, performance and cost point of view. Only density-driven ICs need to rush to the next node. The offering of 28nm FD-SOI by foundries [6] will, without doubt, be interesting for numerous fabless companies having products in 28nm that could take advantage of a higher performance second generation 28nm technology without sacrificing low-power operation. Furthermore, low-power HKMG 28nm FD-SOI will also be very attractive 40nm IC products moving to 28nm.
FD-SOI technology

For bulk MOSFETs, the channel VT is tuned through channel and Halo doping, which is where RDF originates. In contrast, the FD-SOI channel is undoped, significantly decreasing or eliminating RDF. The FD transistor VT is tuned through the gate work function and the back-bias voltage. Because of better electrostatics, FD-SOI transistors exhibit lower parasitics, which improves the transistor driving behavior. This is particularly advantageous at low VDD supplies. The better electrostatics also improve the short-channel effect as compared to the bulk 28nm version. This in turn enables a CMOS technology with shorter gate lengths (Lg=24nm), relaxing the integration constraints on the source and drain contact module.

FD-SOI in the ultra-thin body and buried oxide (UTBB) configuration [2, 3] offers the additional benefit of modulating the FD transistor characteristics by applying a back bias (FIGURE 3a). The FD-SOI transistor is, in principle, controlled by two gates: the actual transistor gate and the back plane, which acts as a second independent gate. Forward (FBB) and reverse back bias (RBB) circuit techniques have been used by many designers in earlier technology nodes but the range of biases were limited, on the one hand, by the source/drain to well diode forward-biasing, and, on the other hand, by the diminishing back biasing modulation of the bulk-transistor threshold voltages (VT) due to increasing channel doping levels. UTBB enables an extended back-biasing range of several VDD (-3V<VBB<+3V) and is a very powerful design tool for power management as well as for performance boosting, as illustrated in FIGURE 3b. Moreover, FD-SOI technology allows for dynamically adjusted threshold voltages.

Body bias requires a limited area overhead (2-3%), and can be restricted only to the IPs (i.e. CPU/GPU cores) that would benefit most from it to reduce the implementation effort and area overhead.

The 28nm FD-SOI process flow is a modified bulk 28nm HKMG LP process. It uses the same back end of the line andsame gate module. It is a simple incremental porting from bulk 28nm. Manufacturing even uses the same tool set. Several process steps, specifically channel implants, halo implants and masking levels, are removed compared to the traditional 28nm bulk technology because of the undoped FD-SOI channel. There is less than a 20% change to the typical CMOS bulk flow [4, 6].

The extremely thin body and buried oxide layers makes it possible to etch them and to co-integrate SOI and bulk devices on the same SoC. The ESD and I/O structures are kept in bulk for simplicity (FIGURE 4b). This is the hybrid integration with diodes and bipolars in bulk [2, 3, 4].

FD-SOI Substrates

FD-SOI technology builds on an SOI substrate with ultra-thin top Si (<12nm) and ultra-thin buried oxide (25nm) and with the utmost thin-layer uniformity of 6 = 0.5nm, all sites and all wafers [8].

Ultra-thin Silicon: The starting ultra-thin Si thickness has to be matched to the subsequent FD CMOS processing. Cleaning and sacrificial oxidations remove a few Si monolayers and this has to be considered when specifying the initial SOI thickness. The targeted Si channel thickness is typically between 5nm ??? 7nm [3, 7]. The SOI thickness (TSi) has a direct effect on the MOSFET characteristics [5]. To take advantage of the improved electrostatic behavior of FD-SOI, the rule of thumb is LG=1/3 TSi (5) in the channel region.

Thickness uniformity is the key parameter to control the VT variation and short-channel effects (SCE) of the planar FD-SOI device. Typical uniformity requirements include on-wafer uniformity and wafer-to-wafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the nanometer or sub-nanometer range for the SOI layer for all wafers and all sites in order to meet the FD specifications.

From circuit and device considerations, the maximum TSI fluctuation that can be tolerated is ??5?? within-wafer (WiW), total wafer range of the TSi non uniformity, and wafer-to-wafer (WtW) TSi reproducibility.

Ultra-thin BOX: The thin BOX (Buried Oxide) suppresses the lateral electrostatic coupling between source, drain and channel of the transistor through the thick BOX. Furthermore, the BOX thickness reduction improves the scalability of the FD-SOI device at almost constant channel silicon thickness down to LG=10nm, which corresponds to the targeted gate length for the 10nm node. An ultra-thin BOX (UTBOX) enables the use of a back bias and a forward bias to adjust the transistor characteristics like current drive (Ion), off leakage (Ioff) and VT within an extended VBB voltage range [9].
The BOX thickness TBOX and silicon thickness TSi are independent parameters for the SOI fabrication and can therefore be adjusted without degrading the properties of the top silicon layer. The oxide quality of ultra-thin BOX is very similar to the quality of equivalent gate oxides.

FD-SOI Design

We use standard commercial EDA flow to design both bulk and FD-SOI. Design migration from Bulk to FD-SOI EDA flow is straightforward. The interconnects and routing are identical. FD-SOI devices behave very much like bulk transistors because there is no history effect and no floating-body effect, if TSi is sufficiently thin (<10nm). Logic and memory design and architecture are also similar to bulk.

The differences between FD-SOI and bulk are related to process and devices, and include, SPICE models, integration of ESD and analog devices, and application of back-bias schemes.

FD-SOI standard and custom cells can be duplicated or ported from existing bulk cells. Re-characterization is required due to a different SPICE model: Input capacitance, timing, leakage and dynamic power data in library files will change. Timing analysis needs to be rerun to check that there are no setup/hold violations in case of direct porting. Porting bulk designs to FD-SOI is as simple as porting to an updated bulk design [10, 11, 13, 14].

The device models are validated on FD-SOI hardware and available with EDA tools. Compact device models [11, 12] are production ready.

Circuit Results

SRAM Robustness: The lowest AVT values are achieved with FD-SOI [3, 9] due to the undoped channel and consequently the strong RDF reduction. Thus, lower VDD operation is enabled for minimum SRAM cell size as compared to its bulk equivalent. The FD-SOI cell has a better read stability and write ability with respect to the bulk cell. The typical bulk countermeasures of increasing VDD, or increasing the channel length and width to compensate for the VT variability are no longer necessary. At the same cell size, FD-SOI makes it possible to gain 100mV to 200mV in Vmin compared to the bulk cell [4]. The operation regime at VDD<0.8V is very attractive for mobile hand-held applications.

Circuit Performance: FD-SOI technology is particularly suited for high speed at low-voltage operation, reducing signifantly the power consumption (~VDD).

At 0.6V, FD-SOI is already capable of delivering 550MHz, >3x the performance of an equivalent 28LP technology implementation, without requiring any Forward Body Bias (FBB). Using Forward Body Bias, it is possible to reach 1GHz operation with a 0.6V source.

FD-SOI can also deliver the same performance as bulk while running at a lower operating voltage. As highlighted in Fig. 7, we have achieved the same performance in 28nm FD-SOI as 28LP while running with 200mV lower supply, and an even further saving of 200mV is possible when applying Forward Body Bias. This impressive reduction of 400mV on the supply voltage immediately translates into huge dynamic power savings.
In overdrive conditions, by boosting performance with FBB, we have demonstrated 3GHz operation [13], overtaking what has been obtained to date with the A9 architecture.


The FD-SOI technology targets fast performance at low voltage VDD and is an ideal technology to reduce the energy gap between battery energy supply and smart handheld system energy needs, so it runs cool. The industrial ecosystem is in place for the substrate supply, technology platform and design infrastructure. The FD-SOI technology platform is perfectly suited for mobile IC applications where the power consumption has to be very low to maximize battery lifetime. Furthermore, with its simplicity, FD-SOI is an evolutionary step from bulk towards fully depleted design because it maintains the planar device structure.


1. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarme, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L.Pipes, I. Post, S. Pradhan, M.Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sanford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry, “A 22nm High Performance and Low Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, self-Aligned Contacts and High Density MIM Capacitors”, VLSI Symp. Tech. (2012).
2. N. Planes, O. Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, PO Sassoulas, X. Federspiel, A. Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, D. Petit, D. Golansli, C. Fenouillet-Beranger, N. Guillot, M. Rafik, V. Huard, S. Puget, X. Montagner, MA Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud and M. Haond, “28nm FD-SOI Technology Platform for High-Speed Low-Voltage Digital Applications”, VLSI Symp. Tech. (2012).
3. T. Skotnicki; IEDM Short Course “Low Power Logic and Mixed Signal Technology”, IEDM 2009.
4. J. Hartmann, STMicroelectronics, “Planar FD-SOI technology at 28nm and below for extremely power efficient SOCs”, 13 Dec 2012, San Francisco, California, USA.
5. T. Skotnicki, Proc. of ESSDERC 2000, pp. 19-33.
6. S. Kengari, GlobalFoundries, ” SoC Differentiation using FD-SOI ??? A Manufacturing Partner’s Perspective FD-SOI Workshop”, 22 April 2013, Hsinchu, Taiwan.
7. K. Cheng, et al; “ETSOI CMOS with Record Low Variability for Low Power System-on-Chip Applications”, IEDM 2009, session 3.2.
8. FD-SOI substrate Soitec data sheet.
9. F. Andrieu, et al; “Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond”, VLSI 2010, session 6.1.
10. J.L. Pelloie and B. Hold, “FD-SOI Design Portability from BULK at 20nm Node”, Fully Depleted Workshop, San Francisco, Feb. 24, 2012.
11. G. Cesana, “20nm and 28nm FD-SOI Technology Platforms”, Fully Depleted Workshop, San Francisco, Feb. 24, 2012.
12. C. Hu, A. Niknejad, Sriramkumar V., Darsen Lu, Yogesh Chauhan, Muhammed Karim, Angada Sachid, “BSIM-IMG: A Turnkey Compact Model for Back-gated FD-SOI MOSFETs”, Fully Depleted Workshop, Hsinchu, Taiwan, April 28, 2011.
13. L. Le Pailleur, Proc. of VLSI-TSA 2013.
14. L. Le Pailleur, “Seamless design migration to 28nm FD-SOI”, 22 April 2013, Hsinchu, Taiwan.
GIORGIO CESANA is director of technology marketing at STMicroelectronics, Crolles, France and CARLOS MAZURE is chief technology officer at Soitec, 38190 Bernin, France.