By Mark LaPedus

A group of 19 European companies and academic institutions have launched a three-year, 360 million euro ($464.5 million) pilot-line project to support the industrialization of fully-depleted silicon-on-insulator (FD-SOI) technology.

The project, dubbed Places2Be, is led by one of the biggest proponents of FD-SOI–STMicroelectronics. In addition, STMicroelectronics and GlobalFoundries will provide the manufacturing capabilities for the program. Separately, GlobalFoundries is also joining Imec’s advanced MRAM project.

Meanwhile, Places2Be, which stands for “Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe,” is aimed to support the deployment of FD-SOI pilot lines at 28nm and beyond.  It will also drive the creation of a European microelectronics design ecosystem using this FD-SOI platform and explore the path towards the next step for this technology at 14nm and 10nm.

The FD-SOI manufacturing sources for the project are located in two fabs. The first is the pilot line in STMicroelectronics’ Crolles fab, near Grenoble, France. The dual-source is in GlobalFoundries’ fab 1 in Dresden, Germany. STMicroelectronics and IBM are the biggest proponents for FD-SOI. Not long ago, STMicroelectronics signed an FD-SOI foundry deal with GlobalFoundries.

FD-SOI is a low-power, high-performance alternative to conventional bulk silicon and finFET technologies. The first FD-SOI systems-on-chips are expected to be used in consumer electronics, high-performance computing and networking.

The project includes participation of 19 partners from 7 countries, and the planned involvement of about 500 engineers over three years across Europe. Places2Be is the largest ENIAC Joint Undertaking project to date and is supported as well by the National Public Authorities in the participating countries. The ENIAC JU was set up in 2008 and will allocate grants throughout 2013. The projects selected for funding shall be executed till December of 2017. The total value of the R&D activities generated through ENIAC JU is estimated at 3 billion euros ($3.8 billion).

“The Places2Be project will reinforce the ecosystems of both Grenoble and Dresden clusters, while also positively impacting the whole value chain of microelectronics in Europe–large companies, SMEs, start-ups and research organizations–beyond the direct impact induced by the material and IP investments,” said François Finck, director of ST’s R&D cooperative programs and project coordinator, in a statement.

The Places2Be members include ACREO Swedish ICT AB,  Adixen Vacuum Products,  Axiom IC, Bruco Integrated Circuits, Commissariat à l’énergie atomique et aux énergies alternatives, Dolphin Integration,  Ericsson AB, eSilicon Romania S.r.l., Forschungzentrum Jülich Gmbh, GlobalFoundries Dresden, Grenoble INP, IMEC,  Ion Beam Services, Mentor Graphics France Sarl, Soitec, ST-Ericsson, STMicroelectronics, Université Catholique de Louvain, and the University of Twente.

In a separate move, GlobalFoundries is joining Imec and others to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology. The first IC manufacturer to join Imec’s R&D program on emerging memory technologies, GlobalFoundries completes the value chain of Imec’s research platform.

GlobalFoundries is joining a team with Qualcomm and several worldwide equipment suppliers providing the complete infrastructure necessary for R&D on STT-MRAM. In January, Qualcomm joined Imec’s STT-MRAM program.

STT-MRAM technology is a promising high-density alternative to existing memory technologies, like SRAM and DRAM. Together, imec and the program members aim to explore the potential of STT-MRAM, including performance below 1ns and scalability beyond 10nm for embedded and standalone applications.

Soitec’s Steve Longoria talks with Semiconductor Manufacturing and Design about what’s changing at the leading edge of Moore’s Law and why those changes are necessary.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Mark LaPedus

The complexity of today’s chips is forcing silicon foundries to expand on both the leading-edge and specialty-process fronts.

For example, GlobalFoundries is expanding in both areas. On the specialty process front, GlobalFoundries confirmed that it recently bought 300mm fab tools from Taiwan’s ProMos Technologies. Many of the tools will be used within GlobalFoundries’ 300mm fab in Singapore, which makes wafers based on various analog and mixed-signal processes. The idea behind this move is to offer “mixed-signal technologies with 300mm economies of scale,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries.

On the leading-edge, the silicon foundry vendor recently expanded its technology platform offerings to five, including bulk planar, super-steep retrograde well (SSRW), fully-depleted silicon-on-insulator (minimum), fully-depleted silicon-on-insulator (maximum) and finFET.

Despite a recent setback with FD-SOI, GlobalFoundries will continue to offer the technology and also gave a ringing endorsement about FD-SOI. In March, Ericsson and STMicroelectronics announced plans to disband ST-Ericsson, a supplier of cell-phone chipsets, including an integrated applications processor based on FD-SOI. Ericsson will take on the design, development and sales of the LTE multimode modem products from ST-Ericsson. STMicroelectronics assumed the ownership of the integrated applications processor based on FD-SOI.

Meanwhile, for some time, GlobalFoundries and STMicroelectronics have had a foundry arrangement under which GlobalFoundries will make FD-SOI products on a foundry basis for STMicroelectronics. GlobalFoundries has not wavered in its support for FD-SOI, saying it will continue to provide the technology on a foundry basis for customers.

FD-SOI provides a viable option for customers, enabling them to differentiate their products, Noonen said. “We want to supply options to customers,” he said. “There is a tremendous amount of interest (for FD-SOI).”

Noonen is also seeing strong interest for its finFET process. GlobalFoundries, Samsung and TSMC have all accelerated their finFET process roadmaps. “We’ve accelerated it,” said Morris Chang, chairman and chief executive of Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), at a recent event. At the event, TSMC reiterated its finFET roadmap, saying it would move into “risk production” by the fourth quarter of 2013.

Like TSMC and Samsung, GlobalFoundries is in mass production for its 28nm processes and is ramping up its 20nm technology. “20nm will be a fast ramp,”  Noonen said. “In general, 28nm is going to be a long-lived node.”

On the specialty process front, meanwhile, GlobalFoundries recently disclosed an initiative called “Vision 2015.”  The initial phase of the plan will include a capacity expansion of its current Fab 7 300mm facility to be on a trajectory of nearly 1 million wafers per year, up from 600,000 wafers a year right now. The expansion is expected to be completed by the middle of 2014.

As part of that effort, GlobalFoundries wants to give analog- and mixed-signal customers a viable 300mm option to compete against the analog leader—Texas Instruments. For some time, TI has been in production within the world’s first 300mm analog fab, dubbed RFAB, based in Texas.

“We want to be the answer to that,” Noonen said.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
Is China set to bail out a U.S. government technology darling? Two Chinese automotive companies, Geely and Dongfeng Motor, are reported to have bid between $200 million and $350 million for a majority stake in Fisker, the maker of plug-in hybrid cars. If that happens Fisker—which has $192 million in U.S. federal government loan guarantees—could be headed to China, according to Lux Research.

Over the years, Apple has moved deeper into IC design. In an e-mail newsletter, Will Strauss, president of Forward Concepts, indicated that Apple could be expanding its efforts in wireless ICs, a move that might impact Broadcom, Qualcomm and others. “There is a rumor published in Israel that Apple will be designing its own baseband and Wi-Fi chips,” Strauss said. “When Texas Instruments dropped out of the cell-phone business, within a week about 100 of the former TI engineers in Israel were hired by Apple. Of course, Apple once hired a bunch of former VLSI Technology wireless engineers, but I understand that that operation came to naught. So, maybe Apple just wanted more engineering talent.”

In a separate research note, Doug Freedman, an analyst with RBC Capital Markets, said: “After talks with management dating back from CES to today (Feb. 25), we believe that Intel is becoming increasingly closer to inking a material foundry design win(s).” Intel is in consideration to be a potential foundry partner for Apple. “Intel’s foundry aspirations may come to light soon,” he said. Apple is also supposedly doing a 20nm foundry deal with TSMC.

Taking the process technology lead in the FPGA market, Achronix Semiconductor is shipping the first in a family of devices based on Intel’s 22nm finFET technology. Achronix’ FPGAs are built using Intel’s foundry services. Achronix says that it has a two- to three-year lead over Altera and Xilinx, which are still shipping 28nm planar devices. The event has prompted two questions. First, will Altera and Xilinx turn up the heat on their FPGA foundry partner, TSMC, to accelerate its finFET efforts? Or second, will Altera and Xilinx turn to Intel over time?

CEA-Leti will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding up the industrialization of the technology. Mentor Graphics, PhoeniX BV and Si2 will work together to develop a common reference platform. STMicroelectronics, Tyndall-UCC, Aifotec and others are also part of the group.

Mentor Graphics has expanded its automotive business unit by purchasing certain assets from MontaVista. This establishes Mentor as a bigger commercial provider of Linux-based automotive in-vehicle infotainment (IVI) solutions.

Mentor announced the 10.2 release of the Questa functional verification platform. In addition, Tesla Motors has standardized on Mentor’s Capital toolset for 12-volt electrical systems design.

With FD-SOI, STMicroelectronics said that application processors manufactured at its fab are capable of operating at 3 GHz.

Soitec and Sumitomo Electric have signed a licensing and technology-transfer agreement. Sumitomo will use Soitec’s Smart Cut technology to manufacture engineered gallium nitride (GaN) substrates. GaN substrates are used in high-performance light-emitting diode (LED) lighting applications.

GlobalFoundries announced enhancements to its 55nm Low-Power Enhanced (LPe) process technology platform. The so-called 55nm LPe 1V has been qualified with next-generation memory and logic IP solutions from ARM.

Are happy days here again for fab tool vendors? The book-to-bill ratio is above parity for the first time in recent memory. North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.14 in January, according to SEMI. This compares to a ratio of 0.92 in December.

Intersil cut its global work force by approximately 18%. This comes on the heels of the resignation of the company’s CEO.

Sony introduced the PlayStation 4, which is based on AMD’s single-chip, eight-core custom processor. The x86 processor, dubbed Jaguar, is a 28nm device built by TSMC.

Five IC suppliers are expected to hold one-third of 300mm wafer capacity in 2013, according to IC Insights. Samsung was by far the leader in 2012, having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.

Qualcomm dominated the LTE cell-phone modem market with a staggering 86% share in 2012, according to Forward Concepts. In total, Qualcomm shipped 47 million FDD-LTE cell-phone modems last year. Samsung followed with 9% of the shipments in 2012, while GCT Semiconductor managed to grab 3% of the market, primarily through LG handsets, according to the firm. Renesas Mobile and Nvidia-Icera each garnered 1% market shares.

The number of China Mobile 4G subscribers is forecast to reach 228.8 million in 2017, representing 52 percent of China’s 439.9 million total 4G users, according to IHS. In comparison, 4G users from China Unicom and China Telecom, the country’s two other major telecommunications operators, will number 114.4 million and 96.8 million, respectively.

By Mark LaPedus
Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories.

In the cell-phone chipset area alone, there are a multitude of options and design considerations. Some devices combine the application processor and modem on the same chip. Some are separate devices. In addition, the architectures range from single- to eight-core devices.

On top of that, devices eventually will migrate from planar to finFET transistors. And not to be outdone, there are a couple of major technology platforms to choose from: bulk CMOS and fully-depleted silicon-on-insulator (FD-SOI). Startup SuVolta also has garnered some attention with its dual-gate 2D transistor, but so far it remains an underdog in a highly competitive market.

Needless to say, OEMs face some tough choices and challenges. The prevailing wisdom is that next-generation smartphones and tablets will require more cores and new transistor architectures. After all, consumers want more performance, bandwidth and battery life.

In reality, however, there is no one-size-fits-all technology. As the market continues to splinter into various sub-segments, such as entry-level phones, smartphones, superphones and tablets, there is room for several different architectures and technologies.

Still, OEMs must rethink their design and product choices before jumping on a device with the most cores and the usual processes. In fact, there is a common and oversimplified message that more processor cores translate into a better performance in mobile systems, said Marco Cornero, a fellow and head of advanced computing at ST-Ericsson, a cell-phone chipmaker.

The reality is that mobile designs are much more complex. There are several factors at play in determining the efficiency of multicore systems, such as software, chip frequency, area and power, Cornero said. And generally, quad-core and beyond may be overkill for today’s systems, thereby creating unnecessary costs for OEMs and consumers. “It makes sense to add more cores if the software can utilize them,” he said. “The problem is the software can’t utilize them.”

Going against the grain, he contends that the optimum solution for mobile platforms involves two main technologies: dual-core and FD-SOI. Dual-core architectures provide enough horsepower, and are more efficient, than today’s slower quad-core devices for mobiles. And bulk CMOS is rapidly running out of gas, propelling the need for a new technology like FD-SOI, he added.

Still, there are various tradeoffs between bulk and SOI, not to mention the implications in moving from planar devices to finFETs. “FinFETs move the line quite nicely in terms of power efficiency,” said John Goodacre, director of program management within ARM’s CPU group. “With finFETs, unfortunately, we lose the dynamic range.”

Multicore: Fact vs. fiction
In any case, there are some parallels between the development of processors for PCs and mobile systems. The prevailing wisdom changed almost overnight in 2001, when Pat Gelsinger, then Intel’s chief technology officer, proclaimed that if chip scaling continued on its current pace, then processors could reach the power density of the sun’s surface by 2015.

At the time, IBM, Intel, AMD and others were racing each other to develop faster microprocessors by boosting the clock frequencies. In those days, Intel claimed that its Pentium 4 processor would scale up to 10 GHz, but in reality, heat dissipation issues limited the clock speeds to only 3.8 GHz.

Then, a decade or so ago, Intel and others moved away from the “megahertz race,” focusing instead on multicore designs. That put far greater emphasis on core efficiency and power consumption, but multicore also caused a fundamental disruption in software on the PC. Applications had to be written in a concurrent and parallelized fashion to map the programs efficiently on multiple processors. Even today, parallelism remains a challenge in system environments.

To some degree, history is repeating itself on the mobile processor front, at least according to ST-Ericsson. To prove its case, the cell-phone chipmaker examined the performance of Apple’s iPhone 4S and 5. The 4S is based on Apple’s A5 application processor, which includes dual-core, 800-MHz Cortex A9 chips from ARM. The iPhone 5 is based on Apple’s A6, which has two custom 1.3-GHz cores based on ARM’s technology.

The software performance of the iPhone 4S and 5 were benchmarked using Browsermark, Geekbench and Sunspider. The benchmarks were conducted by AnandTech, a hardware review Web site.

Deriving the data from AnandTech’s benchmarks, ST-Ericsson drew two conclusions. First, the dual-core processors in the iPhones ran below their theoretical peak performances. Not one of the processors in the iPhone showed signs of being “saturated” in terms of CPU efficiency and frequency, according to ST-Ericsson.

Second, the iPhone 5 ran faster than the 4S. This has little to do with dual-core chips, but rather the faster speeds are attributed to “other hardware optimizations, such as an improved memory sub-system,” according to ST-Ericsson.

Like the PC, the problem is that software scales less proportionally in multicore mobile designs, according to the firm. The dual-core design in the iPhone also impacts clock frequency, due to conflicts on the shared resources in the system.

Now, the market is turning up the volume about quad-core. “There has been a lot of marketing about quad-core,” said ST-Ericsson’s Cornero, “but quad-core doesn’t bring a lot of benefits.”

In Web browsing, for example, a system can run 30% faster when moving from single- to dual-processor designs. But a system only shows a 0 to 11% improvement when moving from the dual- to quad-processor designs, according to the company.

Second opinion
Regarding the multicore debate, ARM has a different viewpoint. “With multicore, I spread the work over two cores,” ARM’s Goodacre said. “In aggregate, the number of instructions are about the same or potentially even less. Then, I can start playing a power game with the voltage. You can lower the frequency with the associated cores for that given workload.”

The real question is whether the software can take advantage of multicore devices execute in parallel. “We’ve got applications that are single-threaded. They run perfectly well on a single thread,” he said. “The question is why do I need multiple cores if the existing workloads can work on one? What we’re really seeing today is a lot of individual sub-systems. This is where we can leverage dual- and quad-core. What that means is that everything runs faster and smoother.”

ARM refers to this as explicit concurrency. Multicore designs are likely required in two booming segments—gaming and social media. “In the user interface, scrolling up and down on Facebook can resource four CPUs flat out. Going back and forth on applications in Android is another one,” he said. “When we look at LTE bandwidths, those management threads are fairly significant in terms of IP traffic. So, you might have three dominant threads, plus management. So, four for the design phase is reasonable. One keeps the management in place. Another puts the network tasks in place. The user interface and the applications each require one.”

There are also tradeoffs on the process and transistor fronts. “Bulk, through voltage and frequency scaling, can get your power/performance ratio down plus or minus 50%,” Goodacre said. “FD-SOI has a specific body-bias technique, which allows it to stretch the voltage down even further while still delivering performance.”

When asked about the shift towards finFETs, he said: “The interesting thing with finFETs is that the steepness of the curve is greatly reduced. It’s much flatter. I don’t have much dynamic range in terms of power efficiency,” he said.

In response to the dynamic range issues, ARM proposes the move towards its heterogeneous architecture, dubbed big.LITTLE. In January, Samsung rolled out an eight-core application processor based on the big.LITTLE architecture. The Exynos 5 Octa from Samsung consists of four Cortex-A15s to handle processing-intense tasks, while four Cortex-A7s are used for lighter workloads.

“Why would I go to eight cores? Some threads would be much better off using a smaller processor. That would represent our ‘LITTLE’ core. In effect, we have about four to six times power efficiency difference between our ‘big’ and ‘LITTLE’ cores,” Goodacre said.

The question is whether big.LITTLE is best served by bulk or FD-SOI? “Does FD-SOI stretch the voltage further with big.LITTLE? This is yet to be confirmed until we measure it,” he said.

In any case, today’s dual-core architectures, combined with FD-SOI, are potentially a powerful combination. ST-Ericsson itself has rolled out an integrated, dual-core cell-phone chipset based on 28nm FD-SOI. The FD-SOI part is 30% faster than bulk devices, said Joel Hartmann, executive vice president of front-end manufacturing and process R&D at STMicroelectronics. “We have demonstrated a 50% power reduction,” he said.

One company has put a new twist in the FD-SOI debate. “FD-SOI is a simpler technology,” said Asen Asenov, chief executive of Gold Standard Simulations, a provider of simulation services. “There are fewer process steps than bulk.”

At 32nm/28nm, the statistical variability introduced by the random discrete dopants in FD-SOI is lower than bulk, Asenov said. With FD-SOI, the threshold voltage variation is reduced more than six times and the leakage is reduced five times for almost equivalent drive current, he said.

STMicroelectronics’ FD-SOI technology is based on a gate-first technology. With gate-first FD-SOI, chipmakers could reduce the voltage to below 0.7V. However, Gold Standard’s simulations revealed that gate-last FD-SOI at 28nm would enable a supply voltage below 0.5V.

“If you take metal-gate-first FD-SOI, and compare with 28nm bulk, FD-SOI will still have a lower variability. If you develop metal-gate-last, this will bring additional benefits,” Asenov said. “FD-SOI in general has a very good chance to deliver a low-power extension for 28nm. A lot of the infrastructure has been put in place. There is enough evidence to make the big fabless companies think very seriously about moving to FD-SOI.”

By Mark LaPedus
A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace.

At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity.

Today, the 28nm crunch is largely over. The foundries have caught up with the demand and customers no longer are feeling the pinch. And as it turns out, 28nm is a sweet spot for many devices and the technology will remain a long-lasting node.

However, the overzealous foundries may have expanded too fast. In fact, there are some signs of a possible foundry glut, and falling fab utilization rates, for 28nm and other processes in 2013. “I don’t see a shortage problem,” said Samuel Wang, an analyst at Gartner. “But overall utilization rates for advanced technologies will go down this year.”

Mobile chipmakers represent the biggest customers for foundries, but pockets of the business are cooling off to some degree. So, unless there is a steep upturn in the near term, the foundry market may quickly turn into a buyers’ market in 2013. Average selling prices for wafers could steadily drop, putting a squeeze on foundry margins.

Besides 28nm, foundries are simultaneously developing 20nm planar and 14nm-class finFETs. In doing so, foundries are moving toward the long-awaited “virtual IDM” model, where vendors and customers collaborate more closely under the same roof.

The shift towards the “virtual IDM” model is easier said than done, however. “The foundries will have some obstacles,” said Robert Bruck, vice president and general manager of the Technology Manufacturing Engineering Group at Intel. “Design, process technology, development and equipment costs are going up.”

As the costs and challenges mount, there are signs that the leading-edge foundry business is ripe for a shakeout. Currently, there are six companies that provide leading-edge foundry services in one form or another: GlobalFoundries, IBM, Intel, Samsung, TSMC and UMC.

28nm glut?
In total, the IC market is expected to increase 6% in 2013, compared to a drop of 1% in 2012, said Bill McClean, president of IC Insights. Capital spending is expected to fall 10% in 2013, but foundry CapEx will remain flat this year, he added.

For 28nm alone, the foundries had a total capacity of 200,000 wafer starts per month (wspm) by the end of 2012, according to Barclays Capital. In 2013, the foundries are expected to add an additional capacity of 75,000 to 100,000 wspm for 28nm, according to Mike Splinter, chairman and chief executive of Applied Materials.

And at 20nm, the foundries are expected to have a total capacity of 25,000 wspm in 2013, Splinter said in a recent conference call. Most of that capacity will be added in the second half of 2013, he said.

Splinter projects that the worldwide wafer fab equipment (WFE) market will be flat to minus 10% in 2013, up from minus 5% to minus 15% from his previous forecast. “We think the foundries will be down, but not as low as we expected,” he said.

CapEx race
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is showing no signs of a slowdown. The world’s largest foundry vendor has increased its capital spending from $8.3 billion in 2012 to $9 billion or more in 2013.

For 28nm, TSMC is expanding its capacity threefold in 2013 over 2012, said Morris Chang, chairman and chief executive of TSMC. In 2012, the polysilicon version of 28nm represented 100% of TSMC’s output. TSMC is expanding its 28nm high-k/metal-gate technology, which will reach the crossover point in the third quarter of 2013, he said.

The company also sees strong demand for 20nm. Apple will have its upcoming 20nm A7 application processors made on a foundry basis by TSMC, according to Barclays Capital, which noted that Apple is switching foundry vendors from Samsung to TSMC.

Meanwhile, GlobalFoundries, the world’s second largest foundry vendor, has set its capital spending budget at $3.5 billion in 2013, said Ajit Manocha, chief executive of GlobalFoundries. In 2012, GlobalFoundries’ capital spending hit $3.2 billion, according to Barclays.

The spending will help GlobalFoundries’ efforts to become more of a “virtual IDM.” In January, GlobalFoundries announced plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. The company’s new Technology Development Center (TDC) will help accelerate its 10nm and 7nm process development.

The TDC will also house part of GlobalFoundries’ stacked-die packaging and advanced photomask efforts. As photomask complexities soar, “some customers want a turnkey solution,” Manocha said.

Within its new 300mm fab in New York, the company has begun ramping up 28nm and 20nm processes. In 2013, Fab 8 is expected to expand from 10,000 to 30,000 wafers a month. “That’s still on plan,” he said. “We are also expanding our fab production in Dresden and Singapore.”

In total, GlobalFoundries will offer five technology platforms: bulk planar, bulk finFET, super-steep retrograde well (SSRW), FD-SOI (minimum) and FD-SOI (maximum). Customer tapeouts for its 14nm-class finFETs are expected in 2013, with production slated for 2014.

The maximum version of FD-SOI is tuned for specific applications, said Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, Kengeri said.

The company will provide FD-SOI wafers on a foundry basis for STMicroelectronics and other customers. GlobalFoundries’ 28nm FD-SOI process will move into risk production in the fourth quarter of 2013, with production slated for the first quarter of 2014.

Meanwhile, amid the apparent loss of a major customer in Apple, Samsung has cut its logic capital spending from 8 trillion Korean won in 2012 to between 4 trillion and 4.5 trillion Korean won in 2013, according to Barclays. Apple accounts for roughly one-third of Samsung’s logic capacity.

Samsung’s main logic/foundry fab is called S1, which is in Korea. S1 is making 28nm devices and is capable of low-volume finFET production. “S1 has more than doubled its size over the last year,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, has been a dedicated foundry plant for Apple. The other fab in Austin was previously a NAND facility. Last year, Samsung converted that fab from NAND into a 28nm logic/foundry plant.

In 2012, the company put on the brakes on its new S3 fab, a 300mm plant in Korea. “S3 resumed construction at the end of January,” said Christian Gregor Dieseldorff, an analyst at SEMI. “Equipment may begin to move in by mid-year. I think this may be the earliest.”

The S3 fab, which is expected to ramp up in 2014, will manufacture 20nm planar devices and 14nm-class finFETs. With process design kits available today, Samsung is expected to sample finFETs in 2014. In addition, the company has deployed “training teams” to help customers with their finFET designs, Samsung’s Hunter said.

The complexity of new and advanced designs will require more handholding between the foundries and their customers. “The collaboration has to get deeper with customers,” she added.

In moving towards the virtual IDM model, the foundries face some challenges. “There are very large investments that are required,” Intel’s Bruck said. “How do you accelerate the yield learning? What about the IP issues? Another aspect in terms of the foundry model is the delay that we are seeing in terms of revenue on the leading-edge.”

All chipmakers, including Intel, face the same challenge: How to keep up with the soaring R&D costs associated with the new and emerging technologies? “R&D is weighing on every level on the supply chain in this industry,” he added.

Foundry companies are keeping a close eye on Intel. To date, Intel is only providing foundry services to a limited customer base, and shows no signs of expanding the offering to a broader audience. So far, the chip maker is providing its 22nm finFET technology on a foundry basis to flow processor supplier Netronome and two FPGA vendors, Achronix and Tabula. In addition, Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

Meanwhile, Taiwan foundry vendor United Microelectronics Corp. (UMC) continues to fall behind, as the company said it is having yield issues with its 28nm process. In addition, UMC recently said it will move directly from 28nm to 14nm finFETs, thereby skipping the 20nm node.

By Mark LaPedus
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node.

Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts to introduce their initial finFET processes at 14nm. And the foundries are already defining their next-generation finFETs at 10nm.

Chipmakers face numerous challenges in terms of ramping up their first- and next-generation finFETs. But the challenges, and costs, could pale in comparison when vendors extend finFET technology to the 7nm and 5nm nodes—or perhaps beyond.

Starting at 7nm, chipmakers plan to inject finFETs with various and exotic III-V materials in the channels to boost the mobility, which refers to how fast the electrons can move through a device. Currently, the industry has narrowed the options down to about five leading candidates for the high-mobility finFET era: finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET.

The two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs. “Conventional thinking currently suggests that we will see a Ge PFET and an InGaAs NFET at 7nm,” said Dean Freeman, an analyst with Gartner. “If the industry could make a silicon nanowire, and create a transistor using silicon and high-k/metal-gate, then we could see the industry move in that direction.”

The III-V materials themselves exist today, but many of the associated manufacturing techniques are in their infancy or simply don’t exist. Bringing up compound semiconductor materials in silicon fabs is a monumental task. And the ability to design and integrate III-V finFETs in a cost-effective manner is easier said than done. “This is not a straightforward process,” said Luc Van den hove, chief executive of IMEC. “We are talking about materials with different lattice constants.”

The challenges leave some observers wondering whether chipmakers should skip the high-mobility finFET era and move directly to the more exotic technologies like carbon nanotubes and graphene. Perhaps the best avenue is the pursuit of stacked 2.5D/3D devices.

Looking into his crystal ball, Gary Patton, vice president of IBM’s Semiconductor Research and Development Center, predicts the two 3D-like approaches, finFETs and stacked die, will have a long and viable future. “The 3D era should carry us well into the 2020 timeframe,” Patton said. “I expect finFETs will last a decade. But then at some point, we hit the atomic dimension limit. Then, we’re talking about silicon nanowires and carbon nanotubes. And to deal with the interconnect issues, we have to talk about integrating photonics on the chip and stacking multiple chips together. That’s really in the next decade.”

Take III-V
Today, the industry is moving towards an inflexion point. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects. So, at 14nm, foundries will introduce finFETs, which have better short-channel electrostatic characteristics than planar.

Today’s finFETs will likely scale at least two generations to 10nm, said Subramani Kengeri, vice present of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V materials to provide a mobility boost, Kengeri said.

The next roadblock is that today’s strained-silicon technology is under stress. For some time, chipmakers have used a silicon-germanium (SiGe) alloy stressor in the channel to boost carrier mobility. “Starting from the 90nm and 65nm nodes, the source-drain areas have been grown using a SiGe epi process in order to bring strain into the device,” said IMEC’s Van den hove. “With strain, we can increase the drive current and device mobility. In the finFET structure, we can do that as well. But this space is very limited, because of the [difficulties] to introduce enough strain into those tiny channels. An alternative way to boost the drive current is by using materials that have intrinsically higher mobilities. This will reduce power consumption.”

The first of these high-mobility devices is expected to appear at 7nm, with the emergence of a finFET with Ge in the p channel and tensile silicon in the n channel. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,400cm-square-over-Vs for silicon.

“But germanium in the p channel is not a straightforward process,” said Aaron Thean, director of the logic program at IMEC. “Germanium tends to move around once exposed to temperature. So the challenges are defects and the structural stability of the device. The surface passivation (for the high-k/metal-gate stack) is also very tricky.”

Following this device, the industry will move to a next-generation high-mobility finFET at 7nm. The first option is a finFET with Ge for both the p and n channels. The second option is Ge for the p channel and indium gallium arsenide (InGaAs) for the n channel. InGaAs has an electron mobility of 12,000cm-square-over-Vs.

“Those two options are competing,” Thean said. “The germanium-germanium option requires compressively strained Ge in the p channel and relaxed Ge in n channel. There are issues with the gate stack and dopant activation.”

Intel and others are leaning toward the Ge-InGaAs option. “InGaAs is our front-up option. It can offer mobilities up to 10X and higher. It’s a better-understood III-V material. I wouldn’t say InGaAs is easy in terms of processing, but it is not as challenging of a material to handle,” Thean said.

The other 7nm candidate is the gate-all-around (GAA) finFET, which can have two or more gates that are wrapped around by a nanowire channel. Purdue University, for one, recently demonstrated GAA finFET with 20nm channel lengths and a sub-threshold swing of 63mV/decade. “There are still lots of challenges with GAA,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.”

Intel and others also have shown interest in the TFET, which may appear at 5nm. In TFET, a tunnel barrier is created at the source-channel contact to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5 volts, said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “TFETs enable steeper sub-threshold voltages,” he said.

There are other options, such as exotic III-V materials for both NFET and PFET. Other III-V materials, including indium antimonide (InSb), are still in R&D. The Sb materials are promising, but have narrow band gaps.

Tool gaps
All of the futuristic, high-mobility finFET devices suffer from the same problem—they are expensive and difficult to manufacture. The most obvious problem is lithography. It’s still unclear if extreme ultraviolet (EUV) lithography will be ready for the 7nm node, meaning the industry may need to extend 193nm immersion and multiple patterning.

Patterning is only one piece of the finFET puzzle. “Lithography has been the story for at least the last 10 years,” said Mike Splinter, chairman and chief executive of Applied Materials. “Now, we are seeing many of the bottlenecks in interface engineering, precision materials and how are you going to get the low-k values.”

For example, RF chipmakers have been fabricating III-V chips in trailing-edge fabs at smaller wafer sizes. At 7nm, the challenge is to grow III-V materials on 300mm or 450mm silicon wafers with good yields and throughput.

It’s unclear which technology, bulk or FD-SOI, will prevail at 7nm and beyond. STMicroelectronics says FD-SOI can extend to at least 10nm and perhaps beyond. “We are continuing to look at SOI,” said IMEC’s Thean. “The nice thing about fully-depleted devices on SOI is that they have excellent isolation.”

In one emerging SOI effort, Ed Nowak, device chief designer at IBM, recently described a fin-on-oxide (Fox) technology that could scale to 5nm. Fox enables a finFET technology with oxide dielectric isolation. Like SOI, Fox enables the finFET manufacturer to produce a controlled fin height, thereby reducing variability. Silicon wafer maker MEMC recently rolled out SOI substrates based on Fox.

The integration between III-V and silicon is perhaps the biggest issue. “In III-V, for example, we use gold as a contact material,” said Raj Jammy, vice president of emerging technologies at Sematech. “Gold is a poisonous material for silicon. So, you need to come up with a new contact metal scheme.”

There is also a need for new metrology tools to find defects in III-V finFETs. New tools are also are required for GAA finFETs with nanowires. “When it comes to gate all-around, you need selective ALD processes,” Jammy said. “For fin/gate fidelity, this requires selective III-V/Ge epi. For etch, we might not be able to use the processes we have today. We are looking into ALD etch.”

The industry is making progress on one front. “One of the areas we are looking at is a low damage conformal 3D doping technique, which we call monolayer doping,” he said. “This enables selective and very shallow junctions. We have solutions with arsenic and phosphorous. What is exciting about this is that the fins that have monolayer doping don’t have any damage.”

All told, high-mobility finFETs promise to enable chip scaling, but the challenges and costs are steep. “There is no free lunch,” he added.

By Mark LaPedus

The recent Nano Job Fair in New York exceeded the 800 registrant capacity. Due to the overwhelming response, and the need to fill an additional 300 jobs, another job fair will be scheduled in the next few months. The fair itself filled more than 300 current and future openings at the CNSE, including positions with the Global 450mm Wafer Consortium (G450C).

China’s transition from a low-cost manufacturing hub to an innovation hotspot with growing foreign ambitions represents both a threat and an opportunity, according to Lux Research. Foreign acquisitions worth $28 billion are just the beginning of China’s global ambitions, according to the firm.

The Chinese IC market is forecast to have a 2012 to 2017 compound annual growth rate (CAGR) of 13%, five points higher than the 8% CAGR forecast for the total IC market during this same time period, according to IC Insights. By 2017, China is expected to represent 38% of the worldwide IC market, up from 23% in 2007, according to the firm.

Skyworks announced its results for the quarter. The company has also garnered some RF antenna tuning design wins, some of which are based on silicon-on-insulator (SOI) technology, said David Aldrich, president and CEO of the RF chip maker, on the Seeking Alpha Web site.

STMicroelectronics announced its results for the quarter. During a conference call, Carlo Bozotti, president and CEO of ST, said the company is developing ASICs for various applications using FD-SOI technology. ST also is looking at strategic options for ST-Ericsson, the cell-phone chip venture with Ericsson, he said. The venture recently rolled out a chip based on FD-SOI.

Following the announcement of STMicroelectronics’ intention to exit as a shareholder of ST-Ericsson, Ericsson is also exploring various strategic options for the venture.

Kilopass, a provider of semiconductor intellectual property (IP), will demonstrate its one-time programmable (OTP) memory IP on IBM’s 45nm, silicon-on-insulator (SOI) technology at the Common Platform Technology Forum. The event, which is on Feb. 5, will take place in Santa Clara, Calif.

Mentor Graphics announced the latest release of its HyperLynx product for superior high-speed design and analysis.

Chipmakers must explore, and embrace, new design methodologies to cut costs and boost cycle times. One way to bolster the design flow is to rethink the register-transfer level (RTL) synthesis process.

Applied Materials said that George Davis, executive vice president and chief financial officer, will depart the company effective March 8. The company expects to name a successor in the coming weeks. Davis will become CFO for Qualcomm.

SEMI and the U.S. Photovoltaic Manufacturing Consortium (PVMC) announced the signing of a memorandum of understanding (MOU) to enhance their cooperation in the areas of standards and roadmap activities for the solar thin film industry.

Renesas continues to cut costs. The company has sold its backend operations to J-Devices.

American Semiconductor has a process that transforms standard silicon wafers into flexible wafers. The technology is now available on TowerJazz’ CMOS foundry process.

Worldwide tablet shipments outpaced predictions, reaching a record total of 52.5 million units worldwide in the fourth quarter of 2012, according to IDC. Samsung is gaining ground on Apple, according to the firm.

VLSI Research says the IC industry will grow 10.1% in 2013. “We expect (the IC industry) to be an ASP-driven upturn,” according to the firm. “Even though the Chinese New Year is still weeks away, chipmakers are becoming more optimistic about 2013. This is driven in part by a modest improvement that is taking place at the macro level. The visibility for the U.S. economy has improved considerably. China’s macro data has also been positive and the European debt crisis appears to be fading.”

Chip inventory held by semiconductor suppliers reached alarmingly high levels in the third quarter of 2012 amid weak market conditions, according to IHS iSuppli.