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Solid State Watch: June 5-11, 2015

Thursday, June 11th, 2015
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SOI: Revolutionizing RF and expanding in to new frontiers

Friday, April 17th, 2015

By Peter A. Rabbeni, Director, RF Segment Marketing and Business Development, GLOBALFOUNDRIES

Faster connections and greater network capacity for wireless technologies such as LTE, WiFi, and the Internet of Things is driving the demand for more complex radio circuit designs and multi-band operation.  In addition the emergence of wirelessly connected smart wearables is not only driving localized high performance processing power but also extended battery life, two goals which are often in conflict. The predicted explosion in the IoT is shown in Figure 1.

Figure 1. More than 30 billion devices are forecast to be connected to the internet by 2018 (Source: BI Intelligence).

The rapid growth in smartphones and tablet PCs and other mobile consumer applications has created an opportunity and demand for chips based on RF-SOI technology, particularly for antenna interface and RF front end components such as RF switches and antenna tuners.  As a low cost and more flexible alternative to expensive gallium arsenide (GaAs) technologies, the vast majority of RF switches today are built on RF-SOI.

To address the highly complex, multi-band and multi-standard designs, RF front-end modules (RF FEM) require integration of multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management. Today these functions are addressed by different technologies. The RF SOI process technology enables design flexibility by integrating multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management to be integrated—all on the same die. The benefit of integrated radios is they consume   less power and smaller area than traditional radios. Therefore, mobile devices that exploit radio integration using RFSOI can offer more functions with better RF performance at competitive cost.

Mobile devices that implement RF SOI for RF Front End module functions benefit from higher levels of integration that combine with improved linearity and insertion loss, which translates to better transmitter efficiency and thus longer battery life enabling longer talk times (lower power) and faster downloads (higher signal-to-noise ratio).

Emerging technologies like RF-SOI and even FD-SOI have unique properties and capabilities beneficial in enabling RF circuit innovation and integration levels never before seen in silicon-based technologies.  Device ft, gm/I, well bias control and inherent isolation of the substrate all contribute to improved system level performance over competing technology resulting in the ability to achieve higher linearity, lower power, low loss, and low cost/small size.

Innovative solutions

An innovative technology that is currently addressing the ever-increasing challenges of RF front-end design is UltraCMOS 10 (Figure 2). This customer specific process, co-developed by GLOBALFOUNDRIES and Peregrine Semiconductor, demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions. For designers, it dramatically reduces the required engineering and validation time. And, for the end-user, they benefit from longer battery life, better reception, faster data rates and wider roaming range. With the qualification process complete, UltraCMOS 10 technology is now a fully qualified technology platform.

Figure 2. UltraCMOS 10 technology demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions (Source: Peregrine Semiconductor).

High speed digital-to-analog converters (DAC) are an essential component for direct-to-RF conversion architectures. Faster converter sampling speeds and greater peak-to-peak signal fidelity hold high promise in moving mobile digital signal processing closer to the antenna. It has been demonstrated that DACs on fully depleted SOI, achieve high linearity and very low power for nyquist bandwidths as wide as 5.5GHz. The RF architecture with a high-performance DAC results in lower power dissipation while synthesizing very wideband signals (Figure 3). This further demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna.

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Figure 3. Low power RF DAC demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna [1

Agile radio architectures are another key area that can address mobile architecture challenges and cost. Today, the analog RF frontend duplicates much of the circuitry for each band. To simplify, new advancements (Figure 4) in tunable structures and filters are being made to provide a single radio for multi-band/multi-mode frequency. SOI technology offers the possibility to develop tunable/reconfigurable RF FEMs to improve RF performance at competitive cost.

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Figure 4. Cutting-edge developments in tunable filters [2

Creating an Ecosystem to Extend SOI to RF

As RF FEM architectures and design challenges become more and more complex, it becomes necessary to relieve some of the increased burden at all levels of the value chain. In order to provide better RF products—from system design and RF integrated circuits down to engineered substrate design—development teams can no longer expect to design in silos and be successful. Collaboration and co-optimization are becoming much more important as a result of the changing dynamics of the design-technology landscape.

Investing in the future is critical to address certain RF challenges such as radio architecture design in multiband, multimode mobile radios and ultra-low power (ULP) wireless devices. Successful collaboration will require adherence to standards to enable interoperability, otherwise, in this fragmented market, the industry won’t see the full benefit of all of the technology innovation. To succeed, we need collaboration at different levels, from R&D to ensure we have the world’s best talent trying to solve all of these problems, all the way through to business models.

There is no doubt that demand on our networks will continue grow and there are advanced chip technology challenges the industry needs to address to enable a higher level of integration and lower power consumption for future wireless communication. GLOBALFOUNDRIES is committed to enabling an SOI portfolio and ecosystem—from process, device, and circuit through system level IP— to lower customer design barriers and complexity and introduce new RF architectures that leverage SOI-based technologies.

References

1. E. Olieman, A.-J. Annema and B. Nauta, “A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist,,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium on , Honolulu, 2014.

2. Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumpernik, Bram Nauta, “A Forward-Body-Bias Tuned 450MHz Gm-C 3rd-Order Low Pass Filter in 28nm UTBB FD-SOI with >1VdBVp IIP3 over a 0.7 to 1V Supply”, ISSCC, San Francisco, 2015.

Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

Blog review October 27, 2014

Monday, October 27th, 2014

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

Phil Garrou blogs that most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers. NANIUM also has extensive volume manufacturing experience in WB multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

Gabe Moretti says it is always a pleasure to talk to Dr. Lucio Lanza and I took the opportunity of being in Silicon Valley to interview Lucio since he has just been awarded the 2014 Phil Kaufman award. Dr. Lanza poses this challenge: “The capability of EDA tools will grow in relation to design complexity so that cost of design will remain constant relative to the number of transistors on a die.”

Are we at an inflection point with silicon scaling and homogeneous ICs? Bill Martin, President and VP of Engineering, E-System Design thinks so. I lays out the case for considering Moore’s Law 2.0 where 3D integration becomes the key to continued scaling.

Congratulations to Applied Materials Executive Chairman Mike Splinter on receiving the Silicon Valley Education Foundation’s (SVEF) Pioneer Business Leader Award for driving change in business and education philanthropy by using his passion and influence to make a positive impact on people’s lives.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. As Adele Hars reports, speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM.

Blog review October 20, 2014

Monday, October 20th, 2014

Matthew Hogan of Mentor Graphics blogs about how automotive opportunities are presenting new challenges for IC verification. A common theme for safety systems involves increasingly complex ICs and the need for exceptional reliability.

Anish Tolia of Linde blogs that technology changes in semiconductor processing and demands for higher-purity and better-characterized electronic materials have driven the need for advanced analytical metrology. Apart from focusing on major assay components, which are the impurities detailed in a Certificate of Analysis (CoA), some customers are also asking that minor assay components or other trace impurities must be controlled for critical materials used in advanced device manufacturing.

Karey Holland of Techcet provides an excellent review of SEMI’s Strategic Materials Conference. The keynote presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm. He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices.

The age of the Internet of Things is upon us, blogs Pete Singer. There are, of course, two aspects of IoT. One is at what you might call the sensor level, where small, low power devices are gathering data and communicating with one another and the “cloud.” The other is the cloud itself. One key aspect will be security, even for low-level devices such as the web-connected light bulb. Don’t hack my light bulb, bro!

Linde Electronics has developed the TLIMS/SQC System. Anish Tolia writes that this system includes an information management database plus SQC/SPC software and delivers connectivity with SAP, electronically pulling order information from SAP to TLIMS and pushing CoA data from TLIMS to SAP.

Ed Korczynski blogs about how IBM researchers showed the ability to grow sheets of graphene on the surface of 100mm-diameter SiC wafers, the further abilitity to grow epitaxial single-crystalline films such as 2.5-μm-thick GaN on the graphene, the even greater ability to then transfer the grown GaN film to any arbitrary substrate, and the complete proof-of-manufacturing-concept of using this to make blue LEDs.

Phil Garrou says it’s been awhile since we looked at what is new in the polymer dielectric market so he checked with a number of dielectric suppliers – specifically Dow Corning, HD Micro and Zeon — and asked what was new in their product lines.

Karen Lightman, Executive Director, MEMS Industry Group, had the pleasure to learn more about the challenges and opportunities affecting MEMS packaging at a recent International Microelectronics Assembly and Packaging Society (IMAPS) workshop held in her hometown of Pittsburgh and at her alma mater, Carnegie Mellon University (CMU).

Ed Korczynski blogs that The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources.”

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014) blogs Adele Hars.

Blog review September 8, 2014

Monday, September 8th, 2014

Jeff Wilson of Mentor Graphics writes that, in IC design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Is 3D NAND a Disruptive Technology for Flash Storage? Absolutely! That’s the view of Dr. Er-Xuan Ping of Applied Materials. He said a panel at the 2014 Flash Memory Summit agreed that 3D NAND will be the most viable storage technology in the years to come, although our opinions were mixed on when that disruption would be evident.

Phil Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out packaging (P-FO), Nanium’s eWLB Dielectric Selection, and an electronics contact lens for diabetics from Google/Novartis.

Ed Koczynski says he now knows how wafers feel when moving through a fab. Leti in Grenoble, France does so much technology integration that in 2010 it opened a custom-developed people-mover to integrate cleanrooms (“Salles Blanches” in French) it calls a Liaison Blanc-Blanc (LBB) so workers can remain in bunny-suits while moving batches of wafers between buildings.

Handel Jones of IBS provides a study titled “How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales” that concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics.

Gabe Moretti of Chip Design blogs that a grown industry looks at the future, not just to short term income.  EDA is demonstrating to be such an industry with significant participation by its members to foster and support the education of its future developers and users through educational licenses and other projects that foster education.

Blog review June 30, 2014

Monday, June 30th, 2014

Pete Singer blogs that at The ConFab last week, IBM’s Gary Patton gave us three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

Tony Chao of Applied Materials writes that Applied Ventures will be participating in the second-annual Silicon Innovation Forum (SIF) held in conjunction with SEMICON West 2014 in San Francisco on Tuesday, July 8. The forum is designed to bring new and emerging innovators together with the semiconductor industry’s top strategic investors and venture capitalists (VCs), in order to enable closer collaboration and showcase the next generation of entrepreneurs in microelectronics.

Adele Hars of ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. Malier said that CEA-Let has been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development.

Phil Garrou blogs that last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core.

Solid State Watch: May 9-15, 2014

Friday, May 16th, 2014
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ST licenses 28nm FD-SOI to Samsung

Friday, May 16th, 2014

By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

On May 14, 2014 it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

“Building upon the existing solid relationship between ST and Samsung within the framework of the International Semiconductor Development Alliance, this 28nm FD-SOI agreement expands the ecosystem and augments fab capacity for ST and the entire electronics industry,” said Jean-Marc Chery, COO, STMicroelectronics. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”

According to Handel Jones, founder and CEO of International Business Strategies Inc. (IBS), “The 28nm node will be long-lived; we expect it to represent approximately 4.3 million wafers in the 2017 timeframe, and FD-SOI could capture at least 25 percent of this market.”

Table 1 shows IBS data estimating costs for different 28nm fab process technologies.

“We are pleased to announce this 28nm FD-SOI collaboration with ST. This is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Seh-Woong Jeong, executive vice president of System LSI Business, Samsung Electronics. “28nm process technology is a highly productive process technology and expected to have a long life span based on well-established manufacturing capabilities.”

In June 2012, ST announced that GLOBALFOUNDRIES had joined the FD-SOI party for the 28nm and 20nm nodes. However, though the name has since changed from “20nm” to “14nm” (Table 2), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.

“Leti continues its development of further generations and our technology and design results show great promise for the 14nm and 10nm nodes,” said Laurent Malier, CEO of CEA-Leti (Laboratory for Electronics and Information Technology). Leti and ST are not against finFET technology, but sees it as complementary to SOI. In fact the ecosystem plans to add finFETs to the FD-SOI platform for the 10nm node, at which point Taiwanese foundry UMC plans to join.

FD-SOI Substrate Technology

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, supplies most of the world’s SOI wafers. Paul Boudre, COO of Soitec, commented, “Our FD-SOI wafers represent an incredible technology achievement, resulting from over 10 years of continuous research and high-volume manufacturing expertise. With our two fabs and our licensing strategy, the supply chain is in place and we are very excited by this opportunity to provide the semiconductor industry with our smart substrates in high volume to enable widespread deployment of FD-SOI technology.”

Soitec’s R&D of ultra-thin SOI was partly funded and facilitated by the major French program called “Investments for the Future.” Soitec has collaborated with CEA-Leti on process evolution and characterization, with IBM Microelectronics for device validation and collaboration, and with STMicroelectronics to industrialize and demonstrate the first products.

Boudre, in an exclusive interview with SST/SemiMD, explained, “For 28nm node processing we use a 25+-1nm buried oxide layer, which is reduced in thickness to 20+-1nm when going to the 14nm node and we don’t see any differences in the substrate production. However, for the 10nm node the buried oxide layer needs to be 15nm thin, and we will need some new process steps to be able to embed nMOS strain into substrates.”

—E.K.

The Week in Review: Nov. 29, 2013

Friday, November 29th, 2013
Soitec and SunEdison, Inc. announced today that they have entered into a patent cross-license agreement relating to silicon-on-insulator (SOI) wafer products.  The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all outstanding legal disputes between the companies. This agreement provides access to a portfolio of patents from both companies and covers the manufacturing of existing engineered unpatterned handle-substrates such as partially depleted SOI (PD-SOI), fully depleted SOI (FD-SOI) and radio-frequency SOI (RF-SOI) as well as advanced FinFETs.
The Semiconductor Industry Association announced that Assistant U.S. Attorney Sherri Schornstein is the recipient of the Anti-counterfeiting Task Force (ACTF) 2013 Distinguished Service Award in appreciation for her many years of service with the U.S. Department of Justice (DOJ) and her successful efforts to combat semiconductor fraud and counterfeiting.
Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, announced that IO Semiconductor Inc., a fabless semiconductor company, has selected the company’s Analog FastSPICE AMS for RF front-end mixed-signal design verification. The Analog FastSPICE Platform provides circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits.
CEA-Leti announced a development agreement that will utilize Leti’s MEMS expertise and leading-edge infrastructure with OMRON, a global leader in factory automation and control solutions for the transportation, healthcare and consumer-goods industries. While Leti has a Tokyo office and has partnered with Japanese companies and research organizations for many years, the agreement is Leti’s first collaboration with a Japanese MEMS producer.
PPG Industries and Universal Display Corporation marked the opening of a world-class organic light-emitting diode (OLED) materials production facility at PPG’s Barberton, Ohio plant. This new site, which PPG owns and operates, commenced manufacturing earlier this month and will foster the expanded development and production of Universal Display’s phosphorescent OLED (UniversalPHOLED) materials.
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