By Mark LaPedus

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena–a series of events that brings the technology one step closer to mass production.

On the 3D front, GlobalFoundries has produced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in Saratoga County, N.Y., the silicon foundry vendor manufactured TSV test wafers using its 20nm-LPM process technology.

At the same time, the company also demonstrated a 32mm x 26mm interposer test vehicle for 2.5D chips. For some time, it has been developing a 65nm interposer manufacturing line within its Fab 7 complex in Singapore.

These are key steps to enable the eventual production of 2.5D and 3D chips. GlobalFoundries’ next step is to work in conjunction with its chip-assembly partners. At some point in the future, the OSATs will take the TSV-enabled wafers and then assemble and qualify 3D test vehicles for customers.

GlobalFoundries is making progress on other fronts. It is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. “2.5D is already here,” said David McCann, vice president of packaging technology at GlobalFoundries.  “Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality.”

Other foundries, including IBM, Samsung, Tezzaron, TSMC and UMC, are also ramping up or developing their respective 2.5D/3D capabilities. But advanced chip stacking has several challenges and is still a few years away from mass production. Some estimate that volume production won’t occur until 2014 or 2015.

E. Jan Vardaman, president of TechSearch International, said the ability to obtain stacked memory is one of the stumbling blocks for 3D designs.  Devices based on the Wide I/O-2 standard are not due out until 2014 or 2015. “Everyone is waiting for the memory cubes,” Vardaman said. “The main question is when are the memory cubes going to ship?”

There are other issues as well. “I think that a number of people are trying out new materials to handle the bond/debond step. That takes more time,” she said. “Many companies indicated they still needed floor planning tools.”

Cost, of course, is still a factor. “Once the technology issues are resolved, the industry will need to bring up the yields in order to lower the cost,” she added.

Still, GlobalFoundries is moving full speed ahead in the arena. Last year, the company entered the 2.5D/3D chip-stacking foundry market and began to install the production tools within its Fab 8 complex.

Now, the company has developed the first 20nm silicon with TSVs, which measure 6u in diameter and 60u deep. “Our integration strategy works for TSV,” McCann said. It is also obtaining good results and yields with its silicon interposer technology in Singapore, he added.

GlobalFoundries’ strategy is far different than TSMC and Samsung, both of which are offering turnkey solutions. In contrast, GlobalFoundries will handle the traditional front-end steps and the “via creation” process. Then, the foundry vendor will hand off the traditional backend steps—such as temporary bonding/debonding, grinding, assembly and test—to the third-party packaging houses.

GlobalFoundries’ strategy, according to McCann, is more flexible and has more advantages over the turnkey model. “Our supply chain is an open model,” he said.

Like its rivals, GlobalFondries utilizes a “via-middle” approach to TSV integration. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, the company has developed a proprietary contact protection scheme. This scheme enables the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

By Mark LaPedus

GlobalFoundries’ recent move to announce a new R&D center will accelerate its efforts to bring technologies from the lab to the fab. And the R&D facility will speed up the foundry company’s efforts to develop its 10nm and 7nm processes, according to Ajit Manocha, chief executive of GlobalFoundries, at an event.

At the same event, Manocha also dismissed reports that the silicon foundry vendor will shortly announce a new fab. “We are not announcing another fab,” he said.

Last week, the company did announce plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. Representing an investment of nearly $2 billion, the new Technology Development Center (TDC) is expected to play a key role in the development of next-generation process technology, 2.5D/3D packaging, lithography and photomasks.

The TDC will “accelerate our ramp to 10nm and 7nm,”  Manocha said during a keynote at the Industry Strategy Symposium (ISS) on Monday (Jan. 14). The ISS is sponsored by SEMI.  “The $2 billion investment (will) help close the gap between the lab and fab.”

The keynote was entitled, “Reshaping the Foundry Industry: Welcome to Foundry 2.0.” In the new model, there is a deeper and earlier collaboration between foundries and their customers. The collaboration, coupled with the new R&D center, enables GlobalFoundries to realize the “virtual IDM model,” he said.

The industry must collaborate more amid the shift towards new and complex process nodes. In September, GlobalFoundries rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM.

By taking the modular approach, the company has accelerated its process roadmap by a year. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.

The foundry vendor plans to move into production with its 10nm finFET process in 2015, a year after its 14nm finFET technology ramp. GlobalFoundries plans to make an announcement regarding the 10nm technology this year, Manocha said.

Then, in 2017, the company plans to roll out its 7nm technology. To help those efforts, it plans to build the new R&D center. The TDC will feature more than a half million square feet of space, which includes a cleanroom and a laboratory. The facility will increase the total capital investment for the Fab 8 campus to more than $8 billion. Construction of the TDC is planned to begin in early 2013, with completion targeted for late 2014.

The TDC will house a variety of semiconductor development and manufacturing spaces to support the transition to new technology nodes. It will provide a collaborative space for the company to devise new interconnect and packaging technologies, photomasks, and lithography technologies like extreme ultraviolet (EUV).

Since breaking ground on Fab 8 in 2009, the foundry vendor has created approximately 2,000 new direct jobs and that number is expected to grow by another 1,000 employees for a total of about 3,000 new jobs by the end of 2014.

Samsung Electronics Co. Ltd. said it is planning to build its NAND flash fab in China in the city of Xi’an. On April 2, 2012, Samsung approved the investment for establishing the fab in China at a cost of $2.3 billion. That figure is part of the total investment amount of $7 billion to be invested over the next several years.

The company is considering establishing a 10nm-class NAND Flash memory production line in Xi’an, China to meet growing market demand for NAND products.

Xi’an, the capital of the Shaanxi province, is famous for the “Terracotta Army” site. This is a collection of terracotta sculptures depicting the armies of Qin Shi Huang, the first Emperor of China.

Samsung ”selected Xian because the city has sound industrial infrastructure such as water and electricity supply and can supply a talented workforce,” according to The Korea Herald, a newspaper and Web site. ”The city has a number of universities and research and development centers for IT firms.”

Last December, Samsung said it applied for the Korean government’s approval for establishing a NAND fab in China, but it did not announce the exact site. The idea behind the fab is to mass produce NAND products at 20 nanometer-class or below, according to Samsung. The company aims to start building the production line in 2012 and begin operation in 2013. The company plans to invest between 4 trillion won ($3.5 billion) and 5 trillion won on the fab, according to reports.

In 2012, Samsung’s capital expenditures are forecast to amount to 25 trillion won ($22.3 billion), in which 15 trillion won ($13.39 billion) will be invested in the semiconductor business.

Specialty foundry vendor TowerJazz Inc. has made a bid with a leading Indian infrastructure conglomerate to build and operate a 300mm fab in India.

This will enable the Israeli company to offer 300mm wafer sizes, 90nm analog technology and companion chips at from 65nm to 45nm.

This is still not a done deal, however. The company presented the fab deal to an Indian government committee as three-way consortia with a leading Indian infrastructure conglomerate. However, TowerJazz said it cannot predict the outcome of government selection, and hence neither has nor can give assurance it will win this bid.

Amir Elstein, chairman of TowerJazz, said: “The recently signed India MOU is a tremendous opportunity for TowerJazz to utilize its manufacturing knowhow and technical expertise to gain a low cost entrance into an emerging market at a 300mm wafer size level. Should this proposal not be accepted, we remain active in pursuing such models where we add benefit to our partners and customers through our expertise and execution and benefit to the shareholders through profitable upside growth.”

Last year, TowerJazz completed its previously announced acquisition of Micron Technology’s fabrication facility in Nishiwaki City, Hyogo, Japan. The acquisition nearly doubles TowerJazz’s current internal manufacturing capacity, cost-effectively increasing production by 60,000 wafers per month. The facility can support geometries down to 95nm and can also be used to manufacture other products using TowerJazz process technologies. The total value of the transaction, including assumption of liabilities, is approximately $140 million.

TowerJazz also reported its results. Fourth quarter 2011 revenue was $174.6 million, compared with $135.1 million in revenues for the fourth quarter of 2010, growth of 29 percent, and compared to $176.1 million in the prior quarter. Net profit on a non-GAAP basis was $34 million and on a GAAP basis net loss was $17 million, or $0.05 per share, compared with a GAAP net profit of $2 million, or $0.01 per share, as achieved in the third quarter of 2011.

2011 revenues were a record $611 million, an increase of 20 percent over revenues of $509 million as reported for 2010 and more than double the $299 million revenues as reported for 2009. On a GAAP basis, net loss narrowed substantially to $19 million, or $0.06 per share, compared with a net loss of $42 million, or $0.18 per share in 2010, and $120 million, or $0.71 per share in 2009.

TowerJazz forecasts first quarter 2012 revenue to range between $165 and $175 million, representing 40 percent year-over-year growth.

By Mark LaPedus, SemiMD senior editor

The semiconductor industry must continue to invest in new fabs, technologies and processes to keep up with current and future IC demand. But only the chip makers with deep pockets and strong technology can play in the leading-edge and high stakes IC game.

For example, to keep up with the insatiable demand for transistors, a leading-edge chip maker may have to spend more than a staggering $100 billion on IC manufacturing and R&D costs alone over a ten-year period in the future, said William Holt, senior vice president and general manager for the Technology and Manufacturing Group at Intel Corp. (Based on historical IC unit demand and die sizes, Holt’s figures are theoretical and not actual forecasts for Intel.)

In any case, to contain soaring IC manufacturing costs, the industry must take some dramatic steps: Chip makers must continue to innovate, look for new solutions and continue stay on the two-year process technology cycle, Holt urged.

There are only a handful of companies that have the funds to stay on the leading edge. GlobalFoundries, Intel, Samsung and TSMC are among the few, it was noted.

Interestingly, during a presentation at SEMI’s Industry Strategy Symposium (ISS) at Half Moon Bay, Calif., Holt did not address one hot topic in the industry: 450mm. But he did briefly discuss the benefits of 3D chips using through-silicon-vias (TSVs).

During the presentation at ISS, Holt said the demand for transistors increased by 15x from 2005 to 2010, thanks to the “explosion of devices and data center build-out” during that period. From 2010 to 2015, the industry will need “15x more” transistors just “to manage, store and interpret data,” he said.

As a result, leading-edge chip makers cannot afford to stand still and must invest. For example, if the IC industry continues on the two-year process development cycle, the cost of manufacturing and process R&D alone for a leading-edge chip maker will run a total of some $104 billion over the next decade, Holt said.

But if the IC industry does not continue on the two-year process development cycle — and remains on the same node — the ten-year cost of manufacturing and process R&D for a leading-edge chip maker will actually increase and run $302 billion over the next ten years, he said.

In addition, some chip makers believe that Moore’s Law should slow down as a means to reduce manufacturing costs. In contrast, Holt believes that the “costs are lower with shorter process cycles.” According to Holt, the manufacturing and R&D costs for a 30-month process cycle is $17 billion, as compared to $10 billion for a two-year cycle and $4 billion for a 18-month cycle. The “optimal cycle is eight quarters,” he said.

Not surprisingly, Holt insists Moore’s Law is alive and well. But to stay on the curve, the industry must overcome several challenges and barriers. “The challenges going forward look harder,” he said, but the “perceived barriers are meant to be surmounted, circumvented or tunneled through.”

The industry, according to Holt, must look for new solutions on several fronts:

-There is a pressing need for new structures. This includes UTB SOI, finFETs, wires/dots, among others.

-There is an opportunity for new materials in transistor design. This includes III-V, carbon nanotubes, and graphene.

-The industry must re-think device density and interconnects. As part of the interconnect equation, Intel sees the benefits going to 3D chips using TSVs.

Future structures and materials enable new devices (Source: Intel)

Holt did not disclose what Intel is doing in the 3D arena. In a brief interview with SemiMD after his presentation, Holt said Intel’s stance has not changed in 450mm. The next-generation wafer size is a viable path to reduce manufacturing costs, he said.

The migration to 450mm will not happen overnight. It is an “industrywide approach,” he said. “I think this is a process.”

As reported, Intel and others are pushing 450mm with a new consortium. The recently-announced 450mm consortium, dubbed G450C, includes five IC manufacturers – with IBM and GlobalFoundries joining the original “IST” members, Intel, Samsung, and TSMC. Those companies, along with Sematech and the SUNY-Albany College of Nanoscale Science and Engineering (CNSE), will sit on a board of directors that will govern the consortium. The G450C demonstration line in Albany is targeted for 14nm design rules early 2013 with imprint technology used for test wafer patterning of over the first year.

More challenges seen for industry

From an equipment point of view, the industry faces several challenges, said Steve Newberry, vice chairman of Lam Research Corp. “Continuation of Moore’s Law is important for the industry to help reduce cost per function and to provide for increased electronics value,” Newberry said during a separate presentation at ISS.

The “semiconductor roadmap (is) facing steep technology and cost challenges,” Newberry said. The “industry needs to figure out how to continue to provide increasing performance and functionality at potentially higher cost without reducing demand or profits.”

In addition, there are “significant R&D challenges ahead with new device structures and 450mm,” he said. Therefore, “more effective supply chain R&D collaboration is needed between the biggest and most capable IC manufacturers with the biggest and most capable equipment suppliers (to) improve R&D development efficiency and cycle time.”

There are also some troubling trends, however. “The IC industry is driven by its ability to continually improve performance while simultaneously driving down cost,” according to IC Insights Inc., a research firm. “Since 1970, the price of a specific IC function has been declining at an incredible rate. The price for a million bits of DRAM memory has declined at 33 percent per year, the price for a million instructions per second (MIPS) of Intel microprocessor power has declined at approximately 30 percent per year and the price per million transistors worldwide has declined about 39 percent per year. More recently, NAND flash memory prices per million bits of memory has declined at approximately 62 percent per year.”

Semiconductor R&D spending hit $48.5 billion in 2011, up 6 percent over 2010, according to IC Insights. R&D as a percentage of revenue was 15.2 percent last year, compared to the industry average of 14.3 percent, according to the firm. Semiconductor R&D spending is expected to hit $54.1 billion in 2012, up 12 percent over 2011, according to IC Insights. R&D as a percentage of revenue is expected to hit 15.7 percent this year.

Fab costs continue to soar. The cost of a fab passed the $100 million level in the 1980s and $1 billion in the mid-1990s. Today a typical 300mm fab cost is $3.8 billion, but that will soar to $5.5 billion by 2016, according to the firm. By 2020, a fab will exceed $10 billion, according to the firm.

Design and mask costs continue to rise. “For a 22nm complex logic process, the cost of the mask set is in the range of $6 million to $10 million depending on process complexity. That compares to about $4 million for 32nm-generation devices and $2 million for 45nm-­generation,” according to IC Insights.

Chip design costs continue to soar

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) held a groundbreaking ceremony in Taichung’s Central Taiwan Science Park for Phase 3 of its Fab 15 GigaFab.

Fab 15, Phase 3 will be TSMC’s second GigaFab equipped for 20nm process technology. The first 300mm GigaFab, Fab 12 module 5, is located in Hsinchu.

Capacity for the Fab 15 Phase 3 is 40,000 300mm wafers per month. In the future, TSMC will make 450mm wafers as well as finFETs at 14nm in Fab 15.

TSMC began construction on Fab 15, Phase 1, in July 2010, and completed equipment move-in in mid-2011 with volume production scheduled for early 2012.

At the same time, Fab 15, Phase 2 started construction in mid-2011 and is expected to begin volume production next year. Fab 15 Phases 1 and 2 are forecast to generate as much as $3 billion in revenue per year once they enter volume production, and Phase 3 will also reach a similar scale in the future. Fab 15 currently employs approximately 1,400 employees.

Billed as a “green” fab, Fab 15, Phase 3 applies numerous pollution prevention and energy conservation methods, including classification of process wastewater into 25 categories, an effective process water recycling rate of 90 percent, water use reduction of 62 percent, and 5 percent less power consumption than earlier facilities.

In addition, Fab 15, Phase 3 has a rainwater collection surface of 40,000 square meters, and all collected rainwater is used in landscaping, consuming no water from public utilities. In addition, TSMC aims to create a benchmark in high-quality green buildings with treatment effectiveness of cleanroom exhaust reaching as high as 98 percent.

TSMC Chairman Morris Chang said: “Fab 15, Phase 3 plays an important role in our plans for advanced technology development and capacity expansion.”

TSMC also announced its net sales for November 2011. On an unconsolidated basis, net sales were approximately NT$35.22 billion, a decrease of 5.4 percent over October 2011 and a decrease of 1.4 percent over November 2010. Revenues for January through November 2011 totaled NT$387.68 billion, an increase of 3.9 percent compared to the same period in 2010.

The fab tool business is slowing. North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.80 in August, down from 0.85 in July, according to SEMI.

A book-to-bill of 0.80 means that $80 worth of orders were received for every $100 of product billed for the month. The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers.

The three-month average of worldwide bookings in August 2011 was $1.18 billion. This is 8.8 percent less than the July level of $1.30 billion, and is 34.8 percent below the $1.82 billion in orders posted in August 2010.

The three-month average of worldwide billings in August 2011 was $1.48 billion. The billings figure is 3.0 percent less than the final July 2011 level of $1.52 billion, and is 5.1 percent less than the August 2010 billings level of $1.55 billion.

“Weaker DRAM demand, foundry spending reductions and near-term uncertainties about electronics demand are reflected in declining sales trends for new semiconductor manufacturing equipment,” said Stanley  Myers, president and CEO of SEMI.  “Consequently, the SEMI 3-month average billings are at levels last seen in June of 2010.”

Through-silicon vias (TSV) allow for 3D stacking of chips, as well as “2.5D” integration of multiple chips using silicon interposers. During SEMICON West 2011, Damo Srinivas, Novellus Systems’ senior director of 3D applications, sat down with Semiconductor Manufacturing and Design to talk about near-term 3D product trends and how responsibilities might shift between IC foundries and Outsourced Semiconductor Assembly and Test (OSAT) lines.

TSV in ICs have been in R&D for over 10 years, and are finally scheduled to reach commercial use in IC manufacturing this year. Vias will be made through silicon in DDR3 DRAM dice to reduce size and power consumption for mobile devices, as scheduled for sampling by Elpida in the 2nd-half of 2011. Typical vias through 10-50 micron thick ICs have used 5:1 to 10:1 aspect-ratios (AR) for copper electroplating. Next year should see more 3D chip stacks being sampled. “In four to five years, all the memory manufcturers will have to have TSV,” predicted Srinivas.

TSV through interposers will be made by many OSATs. For interposers, the final silicon target thickness will be 100-140µm. Interposer thickness cannot be reduced below 100 µm without rigid silicon wafers becoming flexible silicon foils. Interposers allow for easy heterogeneous integration of ICs, and also provide a great substrate for wafer-level integration of passive thin-film resistors, capacitors, and inductors.

“I think the interposer will be a bridge to 3D IC,” said Srinivas. “If you had sufficient volume with 2.5 interposers, then you could do a transiton to true 3D.” Novellus supports customers working on both directions, and also provides low-temperature deposition technologies for backside Re-Distribution Layer (RDL) interconnects.

OSAT Business Models

In addition to the many processing challenges associated with the technology, TSV will likely shake-out traditional business models in the IC industry. To fulfill their ultimate potential as means to provide 3D integration of heterogeneous IC technologies, TSV will trigger changes in the way the industry deals with OSATs.

OSATs are already feeling threatened by IDMs and IC foundries starting to do wafer-level packaging. TSMC, for example, has been expanding it’s offerings to provide more upsteam and downstream survices and today can take a design and return tested and packaged chips. The IC fabs will have to own the via-middle TSV process and perhaps the RDL, so they are actually bringing steps back in-house after decades of outsourcing more and more work.

However, for OSATs, TSV could represent the first time that real differentiations could be shown to customers. OSATs are still going to have to do the test, since IDMs don’t want to invest in test infrastructure. An OSAT could negotiate taking some of the wafer-level packaging in exchange for handling the needed test, and the wafer-level work could be highly specialized and add more value.

For dense package-level interconnects, inexpensive ball drop cannot be used. To get to the tightest needed interconnect pitches, some manner of metal plating technology is needed. TSV using Cu metal are particularly easy to integrate with Cu pillars. A hidden benefit in the use of Cu-pillars is that they cost less to plate than lead-free solder.

Managing TSV Backside Reveal

The backside reveal aspect of TSV formation is integrated with the wafer thinning. OSATs typically grind wafers with successively finer grade absrasives to thin down to near the final target, with perhaps 5 microns at most in residual crystalline damage in the silicon. CMP can reduce the damage layer significantly, and in principle a final ultra-low-pressure chemical polish step in CMP could eventually remove all damage.

Wafer or die thinning to 50 micron for wire-bonding—with no need for TSV—is relatively easy. However, once Cu TSV are embedded in via-middle process flows then the backside reveal becomes one of the trickier aspects of integration. If you use chemical or plasma etches for the reveal step then removal rate variations between different materials allows for tuning of the profile between the vias, the isoloation collars, and the silicon field. Purely mechanical mean of backside reveal will almost certainly smear the copper across the backside silicon surface, and so steps must be taken to somehow clean this contaminatation from the surface.

A residual smear of Cu could short a line and kill a circuit, and so the OSATs that will likely be responsible for TSV backside reveal in 3D chip stacks will have to manage the process well. This new process challenge will be an opportunity for OSATs to differentiate themselves and maybe even raise profit margins a bit.

by Ed Korczynski

Resistance-change Random Access Memory (RRAM or ReRAM) devices continue to be developed at labs and fabs around the world, as seen by more than 40 papers at the spring Materials Research Society (MRS) spring meeting which was held April 25-29 in San Francisco, California. RRAMs are based on resistive switching in metal oxides, such as titantia and niobia, that show memristor properties. With single-digit nanosecond switching-speeds and 10-year non-volatile data retention, RRAMs may represent the future of solid-state memory after DRAM and Flash devices eventually reach scaling limits below 22nm half-pitch.

Technically, the other devices competing with RRAM for the future of memory are themselves based on changes in resistance. Phase-change memory (PCM) using GST material switches between low- and high-resistance states, but requires large drive currents to heat the material to effect the phase-change. Spin-transfer-torque RAM (STT-RAM) is also read as a change in resistance, but the cell size is relatively large. RRAM devices built using cross-point arrays could provide the smallest, fastest, leanest, and cheapest non-volatile memory chips.

Between oral presentations and posters, the Spring 2011 MRS Meeting showed many different groups using different switching materials for RRAMs:

8 – TiO

7 – NiO

6 – Zn0:metal

4 – SiO:Cu

3 – HfO:metal

3 – TMO:metal

3 – polymers

2 – TaO

2 – SrTiO

1 – CuO

1 – HfSiO

1 – WO

1 – solid electrolyte

42 + 11 more novel materials in session Q10

= 53 total RRAM presentations.

HP Labs RRAM Update

Stan Williams’ group at HP Labs has led the world in memristor and RRAM R&D using the titania family of materials as the switch since 2006. They claim that their champion device switches in <2ns, and has world-record endurance of >1.2E10 cycles. Stan Williams provided a keynote address to an MRS workshop last year, in which he explained how his group finally discovered that the conducting channel consists of a 1-2nm thin TiO2 tunnel barrier adjacent to a ~30nm thick “magneli-phase” Ti4O7 layer. Modulating the width of the tunnel barrier through diffusion of oxygen-vacancies controls the electrical resistance of the stack.

This year, HP Labs updated their titania work by reporting on two different electroforming mechanisms seen in the same 50nm × 50nm crossbar memristive device. A “soft” electroforming step uses <140µAmp at ~5V to create a high-resistance mode, while a “hard” electroforming step uses ~250µAmp at ~9V to create a low resistance mode. The two switching modes possessed opposite switching polarities that shared a metastable intermediate resistance state. The two modes can be explained by two switching layers at the top- and bottom-electrode interfaces:

• intermediate state, the bottom layer is ON with conducting channels made of both oxygen-vacancies and charge-traps, while the top layer consists of a tunnel gap;
• OFF state, both layers consist of tunnel gaps; and
• ON state, the top layer is ON with conducting channels made of oxygen-vacancies, while the bottom layer consists of a tunnel gap.

J. Joshua (Jianhua) Yang, provided an update on HP Labs’s RRAM work by surprisingly stating that titanium-oxides have stability issues which may limit device lifetimes, but that tantalum-oxides are free of such issue. The titania family seems to show issues getting beyond 100-1000 cycles, due to excessive heating inside the switch material due to the tendency to apply overvoltage. The two phases of titania will react with each other during heating, so the ON/OFF resistance differences are not so stable. “You need stability, and larger oxygen stability in the materials,” explained Yang. Presumably, the world-record cycling performance using titania was achieved using careful limits on overvoltage.

To improve lifetime with overvoltage margin, HP now uses a tantalum-oxide switching layer, a platinum bottom-electrode, and a tantalum top-electrode. The company claims that this system should be scalable to <5nm, the switching speed is merely 5ns, and the resistance state should be stable for 10 years. TaOx as deposited is amorphous, and even after heating steps it may retain some amorphous character.

RRAM Electroforming Avoidance

The ability to create functional RRAMs without electroforming would provide a significant cost and yield advantage in manufacturing. Though there is still debate as to the exact nature of the solid-state ion-diffusion mechanism(s) responsible for the change in resistance, it is clear that proper stacks of nano-scale oxides and sub-oxides are needed. Consequently, once trial-and-error has identified an ideal materials stack, it is likely that a wafer-scale process flow will be found to create the desired stack without the need for electroforming. For example, annealing in a reducing ambient or solid-phase gettering techniques may be used to adjust the stoichiometry of thin-films.

Using a tungsten-plug from a 90nm node DRAM process flow as one electrode, researchers from Research Center Juelich (with funding from Intel) used TiO2 thickness of 25nm and a Pt/Ti top electrode to make inherently electroforming-free RRAMs (Session Q8.4). Initially the devices were found to be in an intermediate state, and can be SET with positive bias voltage to the low resistance state (LRS). Without bias the intermediate state undergoes a RESET process to a high resistance state (HRS). Under negative voltage bias both processes can be reversed and the device returns into the intermediate state. This flipping of the SET and RESET process from positive to negative bias voltage polarity and vice versa can repeatedly be adjusted in one device. This versatile switching scenario is possible due to the use of the low-workfunction Ti and W electrodes which result in low barriers to the oxide.

The Juelich process flow is as follows:

1. Plasma etch to clean the W plug,
2. Reactive sputter TiO2 (300W, 46sccm AR, 17 sccm O2), and
3. PVD of top-electrode.

The top-electrode was 30nm Pt with an optional 5nm layer of Ti or W below. “As long as there is a Pt/TiO2 interface we need forming,” explained Rainer Bruchhaus of Juelich. However, when using either W or Ti as a barrier between the Pt and TiO2 (while maintaining W as bottom electrode) they see no need for electroforming. In all cases, the voltage range is limited to +- 1V.

RRAM scalability

Much of the global interest in RRAM structures is due to the ability of cross-point memory architectures to be shrunk far more easily than other device structures. The process flow to make cross-point arrays is particularly attractive from an overlay perspective, since the top- and bottom-electrodes are perpendicular to each other and the switching material is patterned along with the top-electrode.

The world record for the smallest resistive memory element is currently held by the National Nano Device Laboratories (NNDL) in Taiwan, which showed a 9nm half-pitch functional RRAM at IEDM last December (Paper #19.1, “9nm Half-Pitch Functional Resistive Memory Cell with <1 µA Programming Current Using Thermally Oxidized Sub-Stochiometric WO_x Film,” C. Ho et al, National Nano Device Laboratories, Taiwan/University of California at Berkeley). It features the lowest reported programming current to date of just <1µA using tungsten-oxide, compared to ~20mA for phase-change memories. The device was built using nano-injection lithography which employs a chemical reaction activated with a finely controlled electron beam to deposit a hard-mask for etching, but could have used Nano-imprint Lithography (NIL) or other patterning to form the array.

For more details on the physics of these devices, Applied Physics A, Vol.A102, No.4 is a special issue on “Memristive and Resistive Devices and Systems,” and is now available for free download as individual PDFs.

by Ed Korczynski

Many presentations at SPIE Advanced Lithography this year focused on the need to shift from 2D to essentially 1D layouts in masks as double-patterning is pushed to ever smaller geometries. For the third year in a row Valery Axelrad of Sequoia Design Systems and Michael Smayling of Tela Innovations presented results from collaborations. Canon has been working with both companies for some time now. The update this year was a combined presentation from all three companies entitled, “Optical lithography applied to 20nm CMOS logic and SRAM” [7973-39].

Patterning 20nm node chips with 193nm lithography is difficult even with immersion technology, since the Metal-1 (M1) pitch will be ~64nm, which is well below the 80nm limit for single exposure. Pushing the limits is possible with double-patterning (DP) when each pattern to essentially a 1D layout: Gridded Design Rules (GDR) to make uniform arrays, followed by a “cut” pattern of selectively placed orthogonal line segments. The cut layer thus becomes the most critical in terms of lithographic parameters, with similarities to the hole patterns used in contact layers. For both critical layers, density variations arise due to differences between logic and memory areas.

With Optical Proximity Correction (OPC) now at the limit, source-mask optimization (SMO) improves margins at the resolution limit, but can only make major improvements to small cells or repetitive designs like memory. OPC has been used for full-chip manufacturability improvements at previous technology nodes, but will not converge these days. “Convergence problems always arise when you have near neighbors and correlations between them,” explained Axelrad.

The authors also considered fundamental lithographic manufacturability parameters such as Depth of Focus (DOF), Normalized Illumination Log Slope (NILS), and Mask Error Enhancement Factor (MEEF) before and after SMO. Working with Canon steppers, realistic lens distortions using experimentally obtained Jones-Zernike expansions as well as realistic entrance pupil illumination were obtained as inputs to models.

Co-Optimization of Layout and Lithography

Simultaneous optimization of layout patterns and lithography settings is made possible by the uniformity and repeatability of the lines/cuts patterns. Optimization variables for the cut layer include the cut geometry (width, height, serifs), illumination of the scanner lens entrance pupil, and grouping cuts in similar optical environments to allow for local OPC. The optimization was for the CD error across all cuts, which also reduces variation among cuts by getting all CDs close to the same target value. This reduction of variation substantially simplifies the layout and OPC and produces manufacturable designs including both SRAM and logic.

There are many ways to formalize GDR+cut DP litho, but Tela and partners propose the following 1D rules :

• Highly uniform 1D GDR layouts with sparse identical cuts,
• critical layers are cuts,
• all cuts identical to each other and tripled to ensure yield,
• cuts also on a fixed grid (avoiding difficult neighborhoods),
• interactions between cuts sufficiently small for local iterative OPC to converge using SMO, and
• Use of a M0 layer to reduce the number of cuts and improve uniformity of cut density.

An algorithm was developed to resolve OPC and SMO for critical cut and hole layers:

STEP1: SMO (a.k.a. “co-optimization”) to find optimal cut shape and size, and illumination of the scanner lens entrance pupil (source), using a small representative sample portion of the layout.

STEP2: Local layout correction (pseudo-OPC) using information from Step1 to create the ideal size for the rectangles at each location, some a little smaller and some a little larger. Typically only 3-5 iterations are needed reach <1 nm RMS CD for a 42 nm target CD, which takes 30-60 seconds on a quad-core CPU, for a total simulation time of ~2 hours on a single CPU for ~120 windows.

The test chip is a 100k MOSFET including 50 different standard cells for SRAM and logic, in 50 x 60 microns area, using a 3 x 3 microns SMO sample window. The optimal illumination is a horizontal dipole. Axelrad claimed that after this extensive Source-Mask Optimization (SMO) the critical dimension (CD) error could be <1 nm at best focus conditions for both logic and SRAM cells at the 20nm node.