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The Week in Review: October 10, 2014

Friday, October 10th, 2014

Samsung Electronics announced plans on Monday to invest $14.7 billion (15.6 trillion Korean won) in a new semiconductor fabrication facility in Pyeongtaek, South Korea to meet growing demand from smartphones, enterprise computing and the emerging “Internet of Things” market.

Soraa, a developer of GaN on GaN LED technology, announced today that one of its founders, Dr. Shuji Nakamura, has been awarded the 2014 Nobel Prize in Physics. Recognizing that Nakamura’s invention, the blue light emitting diode (LED), represents a critical advancement in LED lighting, the Nobel committee explained the innovation “has enabled bright and energy-saving white light sources.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA’s highest honor, the Robert N. Noyce Award.

The Board of Directors of United Microelectronics Corporation (UMC), a global semiconductor foundry, this week announced a joint venture company focused on 12″ wafer foundry services with Xiamen Municipal People’s Government and FuJian Electronics & Information Group.

Emergence of new wide bandgap (WBG) technologies such as SiC and GaN materials will definitely reshape part of the established power electronics industry, according to Yole Développement (Yole).

Atomic Layer Etch now in Fab Evaluations

Monday, August 4th, 2014

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By Ed Korczynski, Sr. Technical Editor

Atomic-Layer Etch (ALE) technology from Lam Research Corp. is now in beta-site evaluations with IC fabrication (fab) customers pursuing next generation manufacturing capabilities. So said Dr. David Hemker, Lam’s senior vice president and chief technical officer, in an exclusive interview with Solid State Technology and SemiMD during this year’s SEMICON West trade-show in San Francisco. Hemker discussed the reasons why ALE is now under evaluation as a critically enabling technology for next generation IC manufacturing, and forecast widespread adoption in the industry by 2017.

As detailed in the feature article “Moving atomic layer etch from lab to fab” in last December’s issue of Solid State Technology, ALE can be plasma enhanced with minor modifications to a continuous plasma etch chamber. The lab aspects including the science behind the process were discussed in a TechXPOT during SEMICON West this year in a presentation titled “Plasma Etch in the Era of Atomic Scale Fidelity” by Lam’s Thorsten Lill based on work done in collaboration with KU Leuven and imec. In that presentation, Lill reminded the attendees that the process has been explored in labs under a wide variety of names:  ALET, atomistic etching, digital etch, layer-by-layer etch, PALE, PE-ALE, single layer etch, and thin layer etching.

ALE can be seen as a logic counter-part to atomic-layer deposition (ALD), with the commonality that both processes become cost-effective when the amount of material being either added or removed are readily measured in atomic layers. It’s comforting that when the industry needs control to the atomic-level we are dealing with such tiny structures that ALD and ALE can provide acceptable throughputs. “By 2017, we see able 15% of the opportunity for us could be addressed by atomic processing,” projected Hemker.

However, ALE as promoted by Lam differs from ALD, because etch processes generally need directionality. “That’s where it diverges from ALD,” explained Hemker. “Using ions we get all the benefits of directionality and selectivity. Likewise, if we design the process correctly, we could theoretically have infinite selectivity with under layers.” Figure 1 shows a trench formed in single-crystal silicon using ALE, with vertical side-walls and a bottom surface smooth at the atomic scale. Such process capability is based on the pulsing of both energy and chemistry into the reaction chamber.

Fig. 1: (Left) Schematic cross-section of Atomic-Layer Etch (ALE) of silicon using a silicon-oxide top mask, (Middle) SEM cross-section of nominal 40-nm silicon trench, and (Right) TEM close-up of the silicon surface showing atomic-scale smoothness.

“We need to be able to pulse multiple things at the same time,” explained Hemker. “So we can absorb a reactant, and then switch over to a plasma. The breakthrough in this is being able to pulse everything correctly.” Labs have been doing this but on a timescale of minutes per atomic layer removed. Lam productized the principle to run on a time-scale of seconds on the 2300 Kiyo tool, which is the current leading-edge hardware for conductor etch from the company.

Pulsing of energy into a reaction chamber has been used in the company’s high aspect-ratio etch process for 3D NAND which runs on the 2300 Flex tool for dielectrics. In this process flow, vias through alternating layers of oxide and nitride in a stack must be etched at 40:1 aspect-ratio today, with 60:1 and even 100:1 aspect-ratio specifications from Samsung for device evaluations. “You see it coming in with pulsing the plasma, allowing us to get ions in and reactants out,” explained Hemker. So the ALE process can be seen as an extension of this pulsing plasma approach, with the extra sophistication of pulsing the chemical precursors into the chamber. “The trick is how to do it repeatably and reliably so that it’s production worthy,” reminded Hemker.

When the ALE precursor adsorbs as a single-layer on surfaces, the connection to the surface could be merely van der Waals forces, or depending upon the application could include some reaction with underlying atoms. “The process conditions have to tailored for flows and gases, but it does open up the possibility of using less expensive process gases. There’s no new gases needed,” declared Hemker. “The real message is not that this is just a new process, but this shares a common background with ALD in pulsing things and having sophisticated enough control of the process.”

Such commonalities would seemingly extend to some chamber hardware and the vacuum and effluent abatement systems, such that it would be very straightforward to cluster single-wafer processing chambers for ALD with ALE with plasma pre-treat and possibly even with annealing. Such a cluster would allow for sophisticated “dep/etch” recipes to be developed for atomic-scale device fabrication.

Fig. 2: Commonality in the need for ALD and ALE process technologies when IC device dimensions scale to atomic levels.

Figure 2 shows the comparison between ALD and ALE processes for a trench structure, and why both are needed when device geometries reach atomic-scales. When trench aspect ratios (AR) are ~1:1 continuous deposition and etch processes can be fairly easily developed to provide uniform results. However, as the AR increases, reaction byproducts tend to non-uniformly deposit on sidewalls and especially at the corners of structures. Eventually, the top of high AR trenches “pinch-off” to create an open in IC circuitry, even when slowing down continuous processes to allow more time for byproducts to escape reaction areas.

Lam expects ALE to be used on the leading-edge of IC manufacturing within a few years, with increasing applications as more critical layers in a device must be patterned to smaller than 22nm half-pitch. “It’s not that you can’t do some of these processes with continuous etch, but ALE really opens up the process window,” explained Hemker. Now is the time for ALE, since the minimum variability of continuous etching consumes more and more of the critical dimension with ever smaller feature sizes.

“If you look at ALD as the for-runner of this, it was first adopted for capacitor deposition in a batch process, then it migrated to single-wafer for high-k metal-gate formation where greater control was needed,” reminded Hemker. “It was used but somewhat niche, and now we’re seeing traction on ALD for many more applications such as quadruple-patterning. The spacers themselves have to be perfectly conformal, because any thickness variation will be a CD variation and it compounds with quadruple patterning.”

Control of pattern fidelity at the atomic-scale will be needed as the commercial IC fab industry integrates new materials for improved device functionalities. ALE and other technologies that can control processing of individual atomic layers should be used to pattern ICs for the indefinite future.

The Week in Review: March 7, 2014

Friday, March 7th, 2014

The Semiconductor Industry Association this week presented its University Research Award – in consultation with Semiconductor Research Corporation (SRC) – to University of Minnesota professor Sachin Sapatnekar in recognition of his outstanding contributions to semiconductor research.

The release this week of the SEMI World Fab Forecast update reveals a 20 to 30 percent projected increase in semiconductor fab equipment spending in 2014.

Researchers from the University of Surrey worked together with scientists from Philips to further develop the ‘Source-Gated-Transistor’ – a simple circuit component invented jointly by the teams.

Global failure analysis equipment market was valued at USD 4.08 billion in 2012, growing at a CAGR of 8.8% from 2013 to 2019.

Semiconductor industry revenues reported by the World Semiconductor Trade Statistics reached a record high in 2013 with global revenues totaling over $305 million.

Solid State Watch: February 28-March 6, 2014

Friday, March 7th, 2014
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The Week in Review: Dec. 6, 2013

Friday, December 6th, 2013

Worldwide sales of semiconductors reached $27.06 billion for the month of October 2013, a 7.2 percent increase from the same month last year when sales were $25.24 billion, according to preliminary results by Gartner, Inc. The top 25 semiconductor vendors’ combined revenue increased 6.2 percent, a significantly better performance than the rest of the market, whose revenue growth was 2.9 percent. This was, in part, due to the concentration of memory vendors, which saw significant growth in the top ranking.

Soitec, a manufacturer semiconductor materials for the electronics and energy industries, this week announced it has reached high-volume manufacturing of its new Enhanced Signal Integrity (eSI) substrates. Soitec’s eSI products, based on Smart Cut technology, are the first “trap-rich” type of material in full production. These substrates, on which devices are manufactured, have a significant impact on the final devices’ performance. Soitec’s eSI substrates are designed by introducing an innovative material (a trap-rich layer) between the high-resistivity handle wafer and the buried oxide. This layer limits the parasitic surface conduction present in standard high-resistivity silicon-on-insulator (HR-SOI) substrates, boosting the performance of RF devices. Because this layer is built into the substrate, it reduces the number of process steps and relaxes design rules, leading to a lower cost process and possibly a smaller die area per function.

SEMI projects that worldwide sales of new semiconductor manufacturing equipment will contract 13.3 percent to $32.0 billion in 2013, according to the SEMI Year-end Forecast, released this week at the annual SEMICON Japan exposition.  In 2014, all regions except Rest of World are expected to have strong positive growth, resulting in a global increase of 23.2 percent in sales. 2015 sales are expected to continue to grow — increasing 2.4 percent with Japan, Europe, Korea, China, and Rest of World regions registering positive growth.

Micron Technology, Inc. announced that the company has named Rajan Rajgopal, vice president of Quality. Rajgopal will be responsible for overseeing all aspects of Micron’s quality systems including manufacturing, customer program management and product ramps. He brings more than 25 years of experience to Micron and most recently served as the vice president of Global Quality and Customer Enablement for GLOBALFOUNDRIES in Singapore.

SEMI’s World Fab Forecast report, published in November, predicts that fab equipment spending will decline about -9 percent (to US$32.5 billion) in 2013 (including new, used and in-house manufactured equipment).  Setting aside the used 300mm equipment GlobalFoundries acquired from Promos at the beginning of 2013 (NT$20-30 billion), fab equipment spending sinks further, to -11 percent in 2013.  The previous World Fab Forecast in August predicted an annual decline of just -1 percent (-3 percent without the used Promos 300mm equipment).

Worldwide sales of semiconductors reached $27.06 billion for the month of October 2013, a 7.2 percent increase from the same month last year when sales were $25.24 billion, and 0.8 percent higher than last month’s total, according to The Semiconductor Industry Association (SIA). “With eight straight months of growth and a new monthly sales record in October, the global semiconductor industry is on track to exceed $300 billion in annual sales for the first time ever in 2013,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “The industry is projected to maintain solid growth for the remainder of 2013 and into 2014, led largely by the Americas, which has remained well ahead of last year’s pace. Congress and the Administration can help maintain and strengthen growth by resolving fiscal uncertainty and investing in scientific research.”

Advances in Post-Tape Out Resource Management

Monday, November 25th, 2013

By Mark Simmons, CalCM Product Manager, Mentor Graphics, Corp.

Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). As technology nodes advance, achieving targeted production runtimes in the post-tapeout flow gets ever more challenging. TAT is important to the fab’s customers, who are keenly interested in meeting their aggressive time-to-market schedules, and also to the fab because time means resources and money. Although a need for better control of and (in most cases) improved reduction of TAT has always been a challenge, the need for a TAT automated controlling mechanism in the post-tapeout flow has been continually neglected because simply adding more hardware has sufficed up until recently. In addition to adding compute hardware, companies also use these three strategies to achieve faster turnaround time (TAT):

  • Fine tuning OPC recipes
  • Improving input hierarchical handling of incoming designs
  • Upgrading to newer software versions to take advantage of new functionalities and performance benefits

Historically, distributed processing tasks require an upfront allocation of hardware and software resources. These resources must be pre-determined prior to starting the run, and are held for the duration of the run. As the jobs run, you can see periods when not all of the allocated resources are being used. Those resources could be used by other jobs, but there is no way to gain access to them. Clearly, this situation can be improved by better utilizing what you have through dynamic resource allocation. In fact, recently published results using a cluster manager software (Guo et. al. 2013, SPIE 8684) demonstrated just over a 30% aggregate TAT improvement for a large set of jobs in conjunction with a greater than 90% average utilization across all hardware resources.

Here’s how it works. The cluster manager software governs the hardware and software resources for all jobs running on a remote compute cluster (Figure 1). It automatically provides idle resources to jobs that can use them, and revokes resources from jobs when they are not being used. In conjunction with focusing on a single job’s performance, it also improves the efficiency of resources at the cluster level, considering all cluster tasks together as a whole. The software optimizes the distribution of resources to all of the jobs running simultaneously on the cluster. In doing so, the result is both an overall aggregate runtime performance improvement and an effective maximization of utilization across the cluster resources.

Figure 1. CalCM integration with resource management tool. (Click to view full screen)

This type of dynamic resource management does the important work of reducing TAT, which is imperative in the competitive foundry industry. It achieves dynamic resource re-distribution by automatically allocating available CPUs to jobs that can use more capacity and by removing CPUs from jobs that are already at or over capacity. Resource allocation is determined by job need, level of importance, resource partitioning, and available resources. But, this system also gives the foundry monitoring information and system- and job-level controls. These features are vital to making decisions regarding the post-tapeout flow and then providing a means to react to them in ways that make the process more efficient and improve the bottom line.

If you want to read about our experiment with deploying this cluster manager software, you can access the SPIE paper “An Automated Resource Management System to Improve Production Tapeout Turn-Around Time” http://go.mentor.com/3_7w_ (registration required).

Mark Simmons is a product manager responsible for CalCM, the cluster management product, at Mentor Graphics. He works closely with foundries and large IDMs and has gained insight into their needs and challenges. He holds a B.S in physics from the State University of New York at Geneseo, a Masters in Microelectronic Manufacturing Engineering from the Rochester Institute of Technology in Rochester, NY, and an MBA from Portland State University in Portland, Oregon. He can be reached at mark_simmons@mentor.com.

Forecast for 2013

Saturday, December 1st, 2012

By Pete Singer

Nobody can predict the future, of course, but 2013 is shaping up to be a good year for the semiconductor industry and its suppliers. According to SEMI, total fab spending for equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size could increase 16.7 percent in 2013 to reach a new record high of $42.7 billion. The estimate includes new equipment, used equipment, or in-house equipment but excludes test assembly and packaging equipment (which, if included, would bring the number up to about $50 billion). The market for semiconductor manufacturing materials, which was $48.6 billion this year, is expected to grow 4% to more than $50 billion in $2013.

There’s been some hand-wringing in 2012 about continued consolidation and the number of companies that will be moving to 450mm: most pundits guess that only 5-7 companies will be able to make the move. However, that’s a limited view of the industry, since there are hundreds of facilities around the world cranking out chips, LEDs, optoelectronics, power devices, MEMS and other components. The latest edition of the SEMI World Fab Forecast lists over 1,150 facilities (including 300 opto/LED facilities), with 76 facilities starting production in 2012 and in the near future.

There’s sure to be much talk in 2013 about technology requirements at the leading edge, including the 450mm transition, progress in EUV, 3D integration and FinFET optimization. Sustainability will be key, with an emphasis on reducing power consumption, which means lower leakage currents and reduced Vdd.

The demand for semiconductors will never be higher, particularly as the middle class rise on dominance in places such as Brazil, Russia, India and China. First on the wish list it seems, after shelter, food and clothing, is a smart phone.
After a trip to imec in Leuven, Belgium, I’m particularly bullish on opportunities in healthcare, which range from body area sensor networks to amazingly advanced labs-on-a-chip that can screen 20 million blood cells per second to find a single tumor cell in 5 billion blood cells. It is these kinds of applications that could lead to a new revolution in how electronics are designed and manufactured.