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Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015


By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types. (Source: Mentor Graphics)

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how data can move through the supply chain. (Source: Texas Instruments)

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.


3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015


By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

Germanium Junctions for CMOS

Tuesday, November 25th, 2014


By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases.  Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Fig.1: Sheet-resistance (Rs) versus RTA temperatures for P, As, and Sb implanted dopants into Ge and Si. (Source: Borland)

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Fig. 2: Cross-section TEM of 1µm Ge-epi after 625°C and 900°C RTA, showing great reduction in stacking-faults with the higher annealing temperature. (Source: Borland)

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

— E. K.

The Week in Review: October 10, 2014

Friday, October 10th, 2014

Samsung Electronics announced plans on Monday to invest $14.7 billion (15.6 trillion Korean won) in a new semiconductor fabrication facility in Pyeongtaek, South Korea to meet growing demand from smartphones, enterprise computing and the emerging “Internet of Things” market.

Soraa, a developer of GaN on GaN LED technology, announced today that one of its founders, Dr. Shuji Nakamura, has been awarded the 2014 Nobel Prize in Physics. Recognizing that Nakamura’s invention, the blue light emitting diode (LED), represents a critical advancement in LED lighting, the Nobel committee explained the innovation “has enabled bright and energy-saving white light sources.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA’s highest honor, the Robert N. Noyce Award.

The Board of Directors of United Microelectronics Corporation (UMC), a global semiconductor foundry, this week announced a joint venture company focused on 12″ wafer foundry services with Xiamen Municipal People’s Government and FuJian Electronics & Information Group.

Emergence of new wide bandgap (WBG) technologies such as SiC and GaN materials will definitely reshape part of the established power electronics industry, according to Yole Développement (Yole).

Atomic Layer Etch now in Fab Evaluations

Monday, August 4th, 2014


By Ed Korczynski, Sr. Technical Editor

Atomic-Layer Etch (ALE) technology from Lam Research Corp. is now in beta-site evaluations with IC fabrication (fab) customers pursuing next generation manufacturing capabilities. So said Dr. David Hemker, Lam’s senior vice president and chief technical officer, in an exclusive interview with Solid State Technology and SemiMD during this year’s SEMICON West trade-show in San Francisco. Hemker discussed the reasons why ALE is now under evaluation as a critically enabling technology for next generation IC manufacturing, and forecast widespread adoption in the industry by 2017.

As detailed in the feature article “Moving atomic layer etch from lab to fab” in last December’s issue of Solid State Technology, ALE can be plasma enhanced with minor modifications to a continuous plasma etch chamber. The lab aspects including the science behind the process were discussed in a TechXPOT during SEMICON West this year in a presentation titled “Plasma Etch in the Era of Atomic Scale Fidelity” by Lam’s Thorsten Lill based on work done in collaboration with KU Leuven and imec. In that presentation, Lill reminded the attendees that the process has been explored in labs under a wide variety of names:  ALET, atomistic etching, digital etch, layer-by-layer etch, PALE, PE-ALE, single layer etch, and thin layer etching.

ALE can be seen as a logic counter-part to atomic-layer deposition (ALD), with the commonality that both processes become cost-effective when the amount of material being either added or removed are readily measured in atomic layers. It’s comforting that when the industry needs control to the atomic-level we are dealing with such tiny structures that ALD and ALE can provide acceptable throughputs. “By 2017, we see able 15% of the opportunity for us could be addressed by atomic processing,” projected Hemker.

However, ALE as promoted by Lam differs from ALD, because etch processes generally need directionality. “That’s where it diverges from ALD,” explained Hemker. “Using ions we get all the benefits of directionality and selectivity. Likewise, if we design the process correctly, we could theoretically have infinite selectivity with under layers.” Figure 1 shows a trench formed in single-crystal silicon using ALE, with vertical side-walls and a bottom surface smooth at the atomic scale. Such process capability is based on the pulsing of both energy and chemistry into the reaction chamber.

Fig. 1: (Left) Schematic cross-section of Atomic-Layer Etch (ALE) of silicon using a silicon-oxide top mask, (Middle) SEM cross-section of nominal 40-nm silicon trench, and (Right) TEM close-up of the silicon surface showing atomic-scale smoothness.

“We need to be able to pulse multiple things at the same time,” explained Hemker. “So we can absorb a reactant, and then switch over to a plasma. The breakthrough in this is being able to pulse everything correctly.” Labs have been doing this but on a timescale of minutes per atomic layer removed. Lam productized the principle to run on a time-scale of seconds on the 2300 Kiyo tool, which is the current leading-edge hardware for conductor etch from the company.

Pulsing of energy into a reaction chamber has been used in the company’s high aspect-ratio etch process for 3D NAND which runs on the 2300 Flex tool for dielectrics. In this process flow, vias through alternating layers of oxide and nitride in a stack must be etched at 40:1 aspect-ratio today, with 60:1 and even 100:1 aspect-ratio specifications from Samsung for device evaluations. “You see it coming in with pulsing the plasma, allowing us to get ions in and reactants out,” explained Hemker. So the ALE process can be seen as an extension of this pulsing plasma approach, with the extra sophistication of pulsing the chemical precursors into the chamber. “The trick is how to do it repeatably and reliably so that it’s production worthy,” reminded Hemker.

When the ALE precursor adsorbs as a single-layer on surfaces, the connection to the surface could be merely van der Waals forces, or depending upon the application could include some reaction with underlying atoms. “The process conditions have to tailored for flows and gases, but it does open up the possibility of using less expensive process gases. There’s no new gases needed,” declared Hemker. “The real message is not that this is just a new process, but this shares a common background with ALD in pulsing things and having sophisticated enough control of the process.”

Such commonalities would seemingly extend to some chamber hardware and the vacuum and effluent abatement systems, such that it would be very straightforward to cluster single-wafer processing chambers for ALD with ALE with plasma pre-treat and possibly even with annealing. Such a cluster would allow for sophisticated “dep/etch” recipes to be developed for atomic-scale device fabrication.

Fig. 2: Commonality in the need for ALD and ALE process technologies when IC device dimensions scale to atomic levels.

Figure 2 shows the comparison between ALD and ALE processes for a trench structure, and why both are needed when device geometries reach atomic-scales. When trench aspect ratios (AR) are ~1:1 continuous deposition and etch processes can be fairly easily developed to provide uniform results. However, as the AR increases, reaction byproducts tend to non-uniformly deposit on sidewalls and especially at the corners of structures. Eventually, the top of high AR trenches “pinch-off” to create an open in IC circuitry, even when slowing down continuous processes to allow more time for byproducts to escape reaction areas.

Lam expects ALE to be used on the leading-edge of IC manufacturing within a few years, with increasing applications as more critical layers in a device must be patterned to smaller than 22nm half-pitch. “It’s not that you can’t do some of these processes with continuous etch, but ALE really opens up the process window,” explained Hemker. Now is the time for ALE, since the minimum variability of continuous etching consumes more and more of the critical dimension with ever smaller feature sizes.

“If you look at ALD as the for-runner of this, it was first adopted for capacitor deposition in a batch process, then it migrated to single-wafer for high-k metal-gate formation where greater control was needed,” reminded Hemker. “It was used but somewhat niche, and now we’re seeing traction on ALD for many more applications such as quadruple-patterning. The spacers themselves have to be perfectly conformal, because any thickness variation will be a CD variation and it compounds with quadruple patterning.”

Control of pattern fidelity at the atomic-scale will be needed as the commercial IC fab industry integrates new materials for improved device functionalities. ALE and other technologies that can control processing of individual atomic layers should be used to pattern ICs for the indefinite future.

The Week in Review: March 7, 2014

Friday, March 7th, 2014

The Semiconductor Industry Association this week presented its University Research Award – in consultation with Semiconductor Research Corporation (SRC) – to University of Minnesota professor Sachin Sapatnekar in recognition of his outstanding contributions to semiconductor research.

The release this week of the SEMI World Fab Forecast update reveals a 20 to 30 percent projected increase in semiconductor fab equipment spending in 2014.

Researchers from the University of Surrey worked together with scientists from Philips to further develop the ‘Source-Gated-Transistor’ – a simple circuit component invented jointly by the teams.

Global failure analysis equipment market was valued at USD 4.08 billion in 2012, growing at a CAGR of 8.8% from 2013 to 2019.

Semiconductor industry revenues reported by the World Semiconductor Trade Statistics reached a record high in 2013 with global revenues totaling over $305 million.

Solid State Watch: February 28-March 6, 2014

Friday, March 7th, 2014
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The Week in Review: Dec. 6, 2013

Friday, December 6th, 2013

Worldwide sales of semiconductors reached $27.06 billion for the month of October 2013, a 7.2 percent increase from the same month last year when sales were $25.24 billion, according to preliminary results by Gartner, Inc. The top 25 semiconductor vendors’ combined revenue increased 6.2 percent, a significantly better performance than the rest of the market, whose revenue growth was 2.9 percent. This was, in part, due to the concentration of memory vendors, which saw significant growth in the top ranking.

Soitec, a manufacturer semiconductor materials for the electronics and energy industries, this week announced it has reached high-volume manufacturing of its new Enhanced Signal Integrity (eSI) substrates. Soitec’s eSI products, based on Smart Cut technology, are the first “trap-rich” type of material in full production. These substrates, on which devices are manufactured, have a significant impact on the final devices’ performance. Soitec’s eSI substrates are designed by introducing an innovative material (a trap-rich layer) between the high-resistivity handle wafer and the buried oxide. This layer limits the parasitic surface conduction present in standard high-resistivity silicon-on-insulator (HR-SOI) substrates, boosting the performance of RF devices. Because this layer is built into the substrate, it reduces the number of process steps and relaxes design rules, leading to a lower cost process and possibly a smaller die area per function.

SEMI projects that worldwide sales of new semiconductor manufacturing equipment will contract 13.3 percent to $32.0 billion in 2013, according to the SEMI Year-end Forecast, released this week at the annual SEMICON Japan exposition.  In 2014, all regions except Rest of World are expected to have strong positive growth, resulting in a global increase of 23.2 percent in sales. 2015 sales are expected to continue to grow — increasing 2.4 percent with Japan, Europe, Korea, China, and Rest of World regions registering positive growth.

Micron Technology, Inc. announced that the company has named Rajan Rajgopal, vice president of Quality. Rajgopal will be responsible for overseeing all aspects of Micron’s quality systems including manufacturing, customer program management and product ramps. He brings more than 25 years of experience to Micron and most recently served as the vice president of Global Quality and Customer Enablement for GLOBALFOUNDRIES in Singapore.

SEMI’s World Fab Forecast report, published in November, predicts that fab equipment spending will decline about -9 percent (to US$32.5 billion) in 2013 (including new, used and in-house manufactured equipment).  Setting aside the used 300mm equipment GlobalFoundries acquired from Promos at the beginning of 2013 (NT$20-30 billion), fab equipment spending sinks further, to -11 percent in 2013.  The previous World Fab Forecast in August predicted an annual decline of just -1 percent (-3 percent without the used Promos 300mm equipment).

Worldwide sales of semiconductors reached $27.06 billion for the month of October 2013, a 7.2 percent increase from the same month last year when sales were $25.24 billion, and 0.8 percent higher than last month’s total, according to The Semiconductor Industry Association (SIA). “With eight straight months of growth and a new monthly sales record in October, the global semiconductor industry is on track to exceed $300 billion in annual sales for the first time ever in 2013,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “The industry is projected to maintain solid growth for the remainder of 2013 and into 2014, led largely by the Americas, which has remained well ahead of last year’s pace. Congress and the Administration can help maintain and strengthen growth by resolving fiscal uncertainty and investing in scientific research.”

Advances in Post-Tape Out Resource Management

Monday, November 25th, 2013

By Mark Simmons, CalCM Product Manager, Mentor Graphics, Corp.

Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). As technology nodes advance, achieving targeted production runtimes in the post-tapeout flow gets ever more challenging. TAT is important to the fab’s customers, who are keenly interested in meeting their aggressive time-to-market schedules, and also to the fab because time means resources and money. Although a need for better control of and (in most cases) improved reduction of TAT has always been a challenge, the need for a TAT automated controlling mechanism in the post-tapeout flow has been continually neglected because simply adding more hardware has sufficed up until recently. In addition to adding compute hardware, companies also use these three strategies to achieve faster turnaround time (TAT):

  • Fine tuning OPC recipes
  • Improving input hierarchical handling of incoming designs
  • Upgrading to newer software versions to take advantage of new functionalities and performance benefits

Historically, distributed processing tasks require an upfront allocation of hardware and software resources. These resources must be pre-determined prior to starting the run, and are held for the duration of the run. As the jobs run, you can see periods when not all of the allocated resources are being used. Those resources could be used by other jobs, but there is no way to gain access to them. Clearly, this situation can be improved by better utilizing what you have through dynamic resource allocation. In fact, recently published results using a cluster manager software (Guo et. al. 2013, SPIE 8684) demonstrated just over a 30% aggregate TAT improvement for a large set of jobs in conjunction with a greater than 90% average utilization across all hardware resources.

Here’s how it works. The cluster manager software governs the hardware and software resources for all jobs running on a remote compute cluster (Figure 1). It automatically provides idle resources to jobs that can use them, and revokes resources from jobs when they are not being used. In conjunction with focusing on a single job’s performance, it also improves the efficiency of resources at the cluster level, considering all cluster tasks together as a whole. The software optimizes the distribution of resources to all of the jobs running simultaneously on the cluster. In doing so, the result is both an overall aggregate runtime performance improvement and an effective maximization of utilization across the cluster resources.

Figure 1. CalCM integration with resource management tool. (Click to view full screen)

This type of dynamic resource management does the important work of reducing TAT, which is imperative in the competitive foundry industry. It achieves dynamic resource re-distribution by automatically allocating available CPUs to jobs that can use more capacity and by removing CPUs from jobs that are already at or over capacity. Resource allocation is determined by job need, level of importance, resource partitioning, and available resources. But, this system also gives the foundry monitoring information and system- and job-level controls. These features are vital to making decisions regarding the post-tapeout flow and then providing a means to react to them in ways that make the process more efficient and improve the bottom line.

If you want to read about our experiment with deploying this cluster manager software, you can access the SPIE paper “An Automated Resource Management System to Improve Production Tapeout Turn-Around Time” (registration required).

Mark Simmons is a product manager responsible for CalCM, the cluster management product, at Mentor Graphics. He works closely with foundries and large IDMs and has gained insight into their needs and challenges. He holds a B.S in physics from the State University of New York at Geneseo, a Masters in Microelectronic Manufacturing Engineering from the Rochester Institute of Technology in Rochester, NY, and an MBA from Portland State University in Portland, Oregon. He can be reached at

Forecast for 2013

Saturday, December 1st, 2012

By Pete Singer

Nobody can predict the future, of course, but 2013 is shaping up to be a good year for the semiconductor industry and its suppliers. According to SEMI, total fab spending for equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size could increase 16.7 percent in 2013 to reach a new record high of $42.7 billion. The estimate includes new equipment, used equipment, or in-house equipment but excludes test assembly and packaging equipment (which, if included, would bring the number up to about $50 billion). The market for semiconductor manufacturing materials, which was $48.6 billion this year, is expected to grow 4% to more than $50 billion in $2013.

There’s been some hand-wringing in 2012 about continued consolidation and the number of companies that will be moving to 450mm: most pundits guess that only 5-7 companies will be able to make the move. However, that’s a limited view of the industry, since there are hundreds of facilities around the world cranking out chips, LEDs, optoelectronics, power devices, MEMS and other components. The latest edition of the SEMI World Fab Forecast lists over 1,150 facilities (including 300 opto/LED facilities), with 76 facilities starting production in 2012 and in the near future.

There’s sure to be much talk in 2013 about technology requirements at the leading edge, including the 450mm transition, progress in EUV, 3D integration and FinFET optimization. Sustainability will be key, with an emphasis on reducing power consumption, which means lower leakage currents and reduced Vdd.

The demand for semiconductors will never be higher, particularly as the middle class rise on dominance in places such as Brazil, Russia, India and China. First on the wish list it seems, after shelter, food and clothing, is a smart phone.
After a trip to imec in Leuven, Belgium, I’m particularly bullish on opportunities in healthcare, which range from body area sensor networks to amazingly advanced labs-on-a-chip that can screen 20 million blood cells per second to find a single tumor cell in 5 billion blood cells. It is these kinds of applications that could lead to a new revolution in how electronics are designed and manufactured.