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Posts Tagged ‘EUVL’

Lithographic Stochastic Limits on Resolution

Monday, April 3rd, 2017

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By Ed Korczynski, Sr. Technical Editor

The physical and economic limits of Moore’s Law are being approached as the commercial IC fab industry continues reducing device features to the atomic-scale. Early signs of such limits are seen when attempting to pattern the smallest possible features using lithography. Stochastic variation in the composition of the photoresist as well as in the number of incident photons combine to destroy determinism for the smallest devices in R&D. The most advanced Extreme Ultra-Violet (EUV) exposure tools from ASML cannot avoid this problem without reducing throughputs, and thereby increasing the cost of manufacturing.

Since the beginning of IC manufacturing over 50 years ago, chip production has been based on deterministic control of fabrication (fab) processes. Variations within process parameters could be controlled with statistics to ensure that all transistors on a chip performed nearly identically. Design rules could be set based on assumed in-fab distributions of CD and misalignment between layers to determine the final performance of transistors.

As the IC fab industry has evolved from micron-scale to nanometer-scale device production, the control of lithographic patterning has evolved to be able to bend-light at 193nm wavelength using Off-Axis Illumination (OAI) of Optical-Proximity Correction (OPC) mask features as part of Reticle Enhancement Technology (RET) to be able to print <40nm half-pitch (HP) line arrays with good definition. The most advanced masks and 193nm-immersion (193i) steppers today are able to focus more photons into each cubic-nanometer of photoresist to improve the contrast between exposed and non-exposed regions in the areal image. To avoid escalating cost and complexity of multi-patterning with 193i, the industry needs Extreme Ultra-Violet Lithography (EUVL) technology.

Figure 1 shows Dr. Britt Turkot, who has been leading Intel’s integration of EUVL since 1996, reassuring a standing-room-only crowd during a 2017 SPIE Advanced Lithography (http://spie.org/conferences-and-exhibitions/advanced-lithography) keynote address that the availability for manufacturing of EUVL steppers has been steadily improving. The new tools are close to 80% available for manufacturing, but they may need to process fewer wafers per hour to ensure high yielding final chips.

Figure 1. Britt Turkot (Intel Corp.) gave a keynote presentation on "EUVL Readiness for High-Volume Manufacturing” during the 2017 SPIE Advanced Lithography conference. (Source: SPIE)

The KLA-Tencor Lithography Users Forum was held in San Jose on February 26 before the start of SPIE-AL; there, Turcot also provided a keynote address that mentioned the inherent stochastic issues associated with patterning 7nm-node device features. We must ensure zero defects within the 10 billion contacts needed in the most advanced ICs. Given 10 billion contacts it is statistically certain that some will be subject to 7-sigma fluctuations, and this leads to problems in controlling the limited number of EUV photons reaching the target area of a resist feature. The volume of resist material available to absorb EUV in a given area is reduced by the need to avoid pattern-collapse when aspect-ratios increase over 2:1; so 15nm half-pitch lines will generally be limited to just 30nm thick resist. “The current state of materials will not gate EUV,” said Turkot, “but we need better stochastics and control of shot-noise so that photoresist will not be a long-term limiter.”

TABLE:  EUVL stochastics due to scaled contact hole size. (Source: Intel Corp.)

CONTACT HOLE DIAMETER 24nm 16nm
INCIDENT EUV PHOTONS 4610 2050
# ABSORBED IN AREAL IMAGE 700 215

From the LithoGuru blog of gentleman scientist Chris Mack (http://www.lithoguru.com/scientist/essays/Tennants_Law.html):

One reason why smaller pixels are harder to control is the stochastic effects of exposure:  as you decrease the number of electrons (or photons) per pixel, the statistical uncertainty in the number of electrons or photons actually used goes up. The uncertainty produces line-width errors, most readily observed as line-width roughness (LWR). To combat the growing uncertainty in smaller pixels, a higher dose is required.

We define a “stochastic” or random process as a collection of random variables (https://en.wikipedia.org/wiki/Stochastic_process), and a Wiener process (https://en.wikipedia.org/wiki/Wiener_process) as a continuous-time stochastic process in honor of Norbert Wiener. Brownian motion and the thermally-driven diffusion of molecules exhibit such “random-walk” behavior. Stochastic phenomena in lithography include the following:

  • Photon count,
  • Photo-acid generator positions,
  • Photon absorption,
  • Photo-acid generation,
  • Polymer position and chain length,
  • Diffusion during post-exposure bake,
  • Dissolution/neutralization, and
  • Etching hard-mask.

Figure 2 shows the stochastics within EUVL start with direct photolysis and include ionization and scattering within a given discrete photoresist volume, as reported by Solid State Technology in 2010.

Figure 2. Discrete acid generation in an EUV resist is based on photolysis as well as ionization and electron scattering; stochastic variations of each must be considered in minimally scaled areal images. (Source: Solid State Technology)

Resist R&D

During SPIE-AL this year, ASML provided an overview of the state of the craft in EUV resist R&D. There has been steady resolution improvement over 10 years with Photo-sensitive Chemically-Amplified Resists (PCAR) from 45nm to 13nm HP; however, 13nm HP needed 58 mJ/cm2, and provided DoF of 99nm with 4.4nm LWR. The recent non-PCAR Metal-Oxide Resist (MOR) from Inpria has been shown to resolve 12nm HP with  4.7 LWR using 38 mJ/cm2, and increasing exposure to 70 mJ/cm2 has produced 10nm HP L/S patterns.

In the EUVL tool with variable pupil control, reducing the pupil fill increases the contrast such that 20nm diameter contact holes with 3nm Local Critical-Dimension Uniformity (LCDU) can be done. The challenge is to get LCDU to <2nm to meet the specification for future chips. ASML’s announced next-generation N.A. >0.5 EUVL stepper will use anamorphic mirrors and masks which will double the illumination intensity per cm2 compared to today’s 0.33 N.A. tools. This will inherently improve the stochastics, when eventually ready after 2020.

The newest generation EUVL steppers use a membrane between the wafer and the optics so that any resist out-gassing cannot contaminate the mirrors, and this allow a much wider range of materials to be used as resists. Regarding MOR, there are 3.5 times more absorbed photons and 8 times more electrons generated per photon compared to PCAR. Metal hard-masks (HM) and other under-layers create reflections that have a significant effect on the LWR, requiring tuning of the materials in resist stacks.

Default R&D hub of the world imec has been testing EUV resists from five different suppliers, targeting 20 mJ/cm2 sensitivity with 30nm thickness for PCAR and 18nm thickness for MOR. All suppliers were able to deliver the requested resolution of 16nm HP line/space (L/S) patterns, yet all resists showed LWR >5nm. In another experiment, the dose to size for imec’s “7nm-node” metal-2 (M2) vias with nominal pitch of 53nm was ~60mJ/cm2. All else equal, three times slower lithography costs three times as much per wafer pass.

—E.K.

High-NA EUV Lithography Investment

Monday, November 28th, 2016

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By Ed Korczynski, Sr. Technical Editor

As covered in a recent press release, leading lithography OEM ASML invested EUR 1 billion in cash to buy 24.9% of ZEISS subsidiary Carl Zeiss SMT, and committed to spend EUR ~760 million over the next 6 years on capital expenditures and R&D of an entirely new high numerical aperture (NA) extreme ultra-violet (EUV) lithography tool. Targeting NA >0.5 to be able to print 8 nm half-pitch features, the planned tool will use anamorphic mirrors to reduce shadowing effects from nanometer-scale mask patterns. Clever design and engineering of the mirrors could allow this new NA >0.5 tool to be able to achieve wafer throughputs similar to ASML’s current generation of 0.33 NA tools for the same source power and resist speed.

The Numerical Aperture (NA) of an optical system is a dimensionless number that characterizes the range of angles over which the system can accept or emit light. Higher NA systems can resolve finer features by condensing light from a wider range of angles. Mirror surfaces to reflect EUV “light” are made from over 50 atomic-scale bi-layers of molybdenum (Mo) and silicon (Si), and increasing the width of mirrors to reach higher NA increases the angular spread of the light which results in shadows within patterns.

In the proceedings of last year’s European Mask and Lithography Conference, Zeiss researchers reported on  “Anamorphic high NA optics enabling EUV lithography with sub 8 nm resolution” (doi:10.1117/12.2196393). The abstract summarizes the inherent challenges of establishing high NA EUVL technology:

For such a high-NA optics a configuration of 4x magnification, full field size of 26 x 33 mm² and 6’’ mask is not feasible anymore. The increased chief ray angle and higher NA at reticle lead to non-acceptable mask shadowing effects. These shadowing effects can only be controlled by increasing the magnification, hence reducing the system productivity or demanding larger mask sizes. We demonstrate that the best compromise in imaging, productivity and field split is a so-called anamorphic magnification and a half field of 26 x 16.5 mm² but utilizing existing 6’’ mask infrastructure.

Figure 1 shows that ASML plans to introduce such a system after the year 2020, with a throughput of 185 wafers-per-hour (wph) and with overlay of <2 nm. Hans Meiling, ASML vice president of product management EUV, in an exclusive interview with Solid State Technology explained why >0.5 NA capability will not be upgradable on 0.33 NA tools, “the >0.5NA optical path is larger and will require a new platform. The anamorphic imaging will also require stage architectural changes.”

Fig.1: EUVL stepper product plans for wafers per hour (WPH) and overlay accuracy include change from 0.33 NA to a new >0.5 NA platform. (Source: ASML)

Overlay of <2 nm will be critical when patterning 8nm half-pitch features, particularly when stitching lines together between half-fields patterned by single-exposures of EUV. Minimal overlay is also needed for EUV to be used to cut grid lines that are initially formed by pitch-splitting ArFi. In addition to the high NA set of mirrors, engineers will have to improve many parts of the stepper to be able to improve on the 3 nm overlay capability promised for the NXE:3400B 0.33 NA tool ASML plans to ship next year.

“Achieving better overlay requires improvements in wafer and reticle stages regardless of NA,” explained Meiling. “The optics are one of the many components that contribute to overlay. Compare to ArF immersion lithography, where the optics NA has been at 1.35 for several generations but platform improvements have provided significant overlay improvements.”

Manufacturing Capability Plans

Figure 2 shows that anamorphic systems require anamorphic masks, so moving from 0.33 to >0.5 NA requires re-designed masks. For relatively large chips, two adjacent exposures with two different anamorphic masks will be needed to pattern the same field area which could be imaged with lower resolution by a single 0.33 NA exposure. Obviously, such adjacent exposures of one layer must be properly “stitched” together by design, which is another constraint on electronic design automation (EDA) software.

Fig.2: Anamorphic >0.5 NA EUVL system planned by ASML and Zeiss will magnify mask images by 4x in the x-direction and 8x in the y-direction. (Source: Carl Zeiss SMT)

Though large chips will require twice as many half-field masks, use of anamorphic imaging somewhat reduces the challenges of mask-making. Meiling reminds us that, “With the anamorphic imaging, the 8X direction conditions will actually relax, while the 4X direction will require incremental improvements such as have always been required node-on-node.”

ASML and Zeiss report that ideal holes which “obscure” the centers of mirrors can surprisingly allow for increased transmission of EUV by each mirror, up to twice that of the “unobscured” mirrors in the 0.33 NA tool. The holes allow the mirrors to reflect through each-other, so they all line up and reflect better. Theoretically then each >0.5 NA half-field can be exposed twice as fast as a 0.33 NA full-field, though it seems that some system throughput loss will be inevitable. Twice the number of steps across the wafer will have to slow down throughput by some percent.

White two stitched side-by-side >0.5 NA EUVL exposures will be challenging, the generally known alternatives seem likely to provide only lower throughputs and lower yields:

*   Double-exposure of full-field using 0.33 NA EUVL,

*   Octuple-exposure of full-field using ArFi, or

*   Quadruple-exposure of full-field using ArFi complemented by e-beam direct-writing (EbDW) or by directed self-assembly (DSA).

One ASML EUVL system for HVM is expected to cost ~US$100 million. As presented at the company’s October 31st Investor Day this year, ASML’s modeling indicates that a leading-edge logic fab running ~45k wafer starts per month (WSPM) would need to purchase 7-12 EUV systems to handle an anticipated 6-10 EUV layers within “7nm-node” designs. Assuming that each tool will cost >US$100 million, a leading logic fab would have to invest ~US$1 billion to be able to use EUV for critical lithography layers.

With near US$1 billion in capital investments needed to begin using EUVL, HVM fabs want to be able to get productive value out of the tools over more than a single IC product generation. If a logic fab invests US$1 billion to use 0.33 NA EUVL for the “7nm-node” there is risk that those tools will be unproductive for “5nm-node” designs expected a few years later. Some fabs may choose to push ArFi multi-patterning complemented by another lithography technology for a few years, and delay investment in EUVL until >0.5 NA tools become available.

—E.K.

EUV Resists and Stochastic Processes

Friday, March 4th, 2016

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By Ed Korczynski, Sr. Technical Editor

In an exclusive interview with Solid State Technology during SPIE-AL this year, imec Advanced Patterning Department Director Greg McIntyre said, “The big encouraging thing at the conference is the progress on EUV.” The event included a plenary presentation by TSMC Nanopatterning Technology Infrastructure Division Director and SPIE Fellow Anthony Yen on “EUV Lithography: From the Very Beginning to the Eve of Manufacturing.” TSMC is currently learning about EUVL using 10nm- and 7nm-node device test structures, with plans to deploy it for high volume manufacturing (HVM) of contact holes at the 5nm node. Intel researchers confirm that they plan to use EUVL in HVM for the 7nm node.

Recent improvements in EUV source technology— 80W source power had been shown by the end of 2014, 185W by the end of 2015, and 200W has now been shown by ASML—have been enabled by multiple laser pulses tuned to the best produce plasma from tin droplets. TSMC reports that 518 wafers per day were processed by their ASML EUV stepper, and the tool was available ~70% of the time. TSMC shows that a single EUVL process can create 46nm pitch lines/spaces using a complex 2D mask, as is needed for patterning the metal2 layer within multilevel on-chip interconnects.

To improve throughput in HVM, the resist sensitivity to the 13.54nm wavelength radiation of EUV needs to be improved, while the line-width roughness (LWR) specification must be held to low single-digit nm. With a 250W source and 25 mJ/cm2 resist sensitivity an EUV stepper should be able to process ~100 wafer-per-hour (wph), which should allow for affordable use when matched with other lithography technologies.

Researchers from Inpria—the company working on metal-oxide-based EUVL resists—looked at the absorption efficiencies of different resists, and found that the absorption of the metal oxide based resists was ≈ 4 to 5 times higher than that of the Chemically-Amplified Resist (CAR). The Figure shows that higher absorption allows for the use of proportionally thinner resist, which mitigates the issue of line collapse. Resist as thin as 18nm has been patterned over a 70nm thin Spin-On Carbon (SOC) layer without the need for another Bottom Anti-Reflective Coating (BARC). Inpria today can supply 26 mJ/cm2 resist that creates 4.6nm LWR over 140nm Depth of Focus (DoF).

To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum half-pitch (HP) of lines/spaces. (Source: JSR Micro)

JEIDEC researchers presented their summary of the trade-off between sensitivity and LWR for metal-oxide-based EUV resists:  ultra high sensitivity of 7 mJ/cm2 to pattern 17nm lines with 5.6nm LWR, or low sensitivity of 33 mJ/cm2 to pattern 23nm lines with 3.8nm LWR.

In a keynote presentation, Seong-Sue Kim of Samsung Electronics stated that, “Resist pattern defectivity remains the biggest issue. Metal-oxide resist development needs to be expedited.” The challenge is that defectivity at the nanometer-scale derives from “stochastics,” which means random processes that are not fully predictable.

Stochastics of Nanopatterning

Anna Lio, from Intel’s Portland Technology Development group, stated that the challenges of controlling resist stochastics, “could be the deal breaker.” Intel ran a 7-month test of vias made using EUVL, and found that via critical dimensions (CD), edge-placement-error (EPE), and chain resistances all showed good results compared to 193i. However, there are inherent control issues due to the random nature of phenomena involved in resist patterning:  incident “photons”, absorption, freed electrons, acid generation, acid quenching, protection groups, development processes, etc.

Stochastics for novel chemistries can only be controlled by understanding in detail the sources of variability. From first-principles, EUV resist reactions are not photon-chemistry, but are really radiation-chemistry with many different radiation paths and electrons which can be generated. If every via in an advanced logic IC must work then the failure rate must be on the order of 1 part-per-trillion (ppt), and stochastic variability from non-homogeneous chemistries must be eliminated.

Consider that for a CAR designed for 15mJ/cm2 sensitivity, there will be just:

145 photons/nm2 for 193, and

10 photons/nm2 for EUV.

To improve sensitivity and suppress failures from photon shot-noise, we need to increase resist absorption, and also re-consider chemical amplification mechanisms. “The requirements will be the same for any resist and any chemistry,” reminded Lio. “We need to evaluate all resists at the same exposure levels and at the same rules, and look at different features to show stochastics like in the tails of distributions. Resolution is important but stochastics will rule our world at the dimensions we’re dealing with.”

—E.K.

Many Mixes to Match Litho Apps

Thursday, March 3rd, 2016

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By Ed Korczynski, Sr. Technical Editor

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in HVM by at least one leading memory fab.

Fig.1: Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs:  Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues. “In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran. “We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology:  ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers. “Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor, in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints. Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm., while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

Fig.2: Relative estimated costs to pattern 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high-volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

—E.K.

ASML Details Advances in DUV, Metrology, EUV

Thursday, February 25th, 2016

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By Jeff Dorsch, Contributing Editor

ASML Holding is glad to talk about its continuing progress in extreme-ultraviolet lithography technology. But first, the company has some information about its deep-ultraviolet scanners, as well.

ASML continues to ship its TWINSCAN NXT: 1980Di immersion lithography systems, which are capable of processing 275 wafers per hour, according to Michael Lercel, ASML’s director of strategic marketing.

Since shipments began last year, the 1980Di is exhibiting overlay numbers that are “slightly better than expected,” Lercel said Wednesday at the SPIE Advanced Lithography conference in San Jose, Calif. ASML aimed to make the 193i litho system “ a little bit more robust” than its predecessor, the TWINSCAN NXT: 1970Ci, he added. The 1970Ci can be upgraded in the field to the 1980Di’s capabilities, according to the company.

The 1980Di can be utilized in a combination of lithography techniques, including single exposure, lithography-etch-lithography-etch, sidewall spacers, and self-aligned double patterning, Lercel said. It offers the kind of variability control needed for self-aligned quadruple patterning, he added.

The ASML executive also addressed the company’s new YieldStar 350E metrology system, which he said can “correct for overlay errors” and “apply corrections to upstream and downstream problems,” using “a lot of overlay data.”

On the EUV front, Lercel said ASML has made “a lot of progress in the last 12 to 18 months.” At its facilities in Veldhoven, the Netherlands, the company has been able to operate a power source for its EUV systems at 200 watts “for one hour, with full dose control,” he noted.

That’s approaching its high-volume manufacturing target of 250W, according to Lercel. ASML continues to predict its EUV scanners will move into volume production applications in the 2018-19 timeframe, he said.

Intel and Samsung Electronics this week reported running their EUV power sources at 80W over extended periods.

The new TWINSCAN NXE:3350B scanners are now being shipped with 125W power sources, Lercel noted. ASML has demonstrated 80 percent availability in the field, including scheduled downturns, bringing EUV close to matching immersion lithography, Lercel said. Regarding availability, “we need to do better in consistency,” he acknowledged.

ASML has “multiple EUV systems at multiple customers,” Lercel said. In addition to Intel and Samsung, the company’s EUV scanners are also being used at GlobalFoundries, SK Hynix, and Taiwan Semiconductor Manufacturing, among others not yet identified by the equipment vendor.

ASML this week reported reaching a deal with Nippon Control System on integrating optical proximity correction to mask data preparation on a common platform.

Laser Suppliers Move Past the Neon Gas Crisis

Wednesday, February 24th, 2016

By Jeff Dorsch, Contributing Editor

That neon gas shortage? So 2015.

The supply issue continues, as armed conflict heats up in eastern Ukraine, site of a plant that supplies a majority of the neon gas used in the world. Cymer and Gigaphoton, the big suppliers of excimer lasers for lithography that use neon as a buffer gas, have worked around the shortage, including the recycling of gas exhaust from their lasers.

“Prices have somewhat stabilized,” said Joe Ganeshan, sales manager for Gigaphoton USA. “We’re still in a crisis.”

Pricing for neon gas last year rose by 10 to 20 times, according to Ted Cacouris, product marketing director at the Cymer subsidiary of ASML Holding. One gas supplier in Ukraine was behind more than half of the world’s supply, and transporting the gas out of the conflict zone became haphazard, he noted.

The spike in neon gas prices peaked in 2015’s late summer and early fall, Cacouris said. As semiconductor manufacturers adjusted to the shortage, “prices started rolling over,” he added.

Cymer and Gigaphoton both implemented recycling programs in response to the supply situation, dramatically reducing neon gas consumption for their customers. Ganeshan estimated his company’s customers saved around $90 million a year as a result, while Cacouris put the figure at about $200 million.

In addition to reducing neon-gas consumption, Gigaphoton is moving to eliminate the use of helium in chipmaking, citing the U.S. government’s plans to cut off supply of the unrenewable gas in the near future. Used as a purging gas in argon fluoride 193i immersion lithography scanners, helium will be replaced with nitrogen, Ganeshan said.

Putting the neon-gas crisis in the rearview mirror, Cymer and Gigaphoton are turning to other pressing issues as suppliers of the light sources used in immersion and extreme-ultraviolet lithography systems.

Gigaphoton claimed to have improved its market share in excimer lasers for semiconductor manufacturing to 60 percent or more in 2015.

Cymer’s Cacouris cast doubt on that figure, without disclosing his company’s market share last year. Japan-based Gigaphoton greatly benefited from the exchange rate on the yen, gaining a 20 percent pricing advantage as a result, he asserted.

He described Gigaphoton’s claim as “a bit optimistic,” adding, “They’ve had some progress; they’ve had a few wins.” Cacouris vowed, “We’re going to do a lot better this year.”

Before the SPIE Advanced Lithography conference in San Jose, Calif., Gigaphoton announced that it is establishing new support bases in Dalian and Xiamen, China. The company also said it has received supplier awards from United Microelectronics and Taiwan Semiconductor Manufacturing.

Canon, Toshiba Join eBeam Initiative Group

Wednesday, February 24th, 2016

By Jeff Dorsch, Contributing Editor

The eBeam Initiative announced that Canon and Toshiba are new members of the industry organization, which seeks to promote the use of electron-beam technology in semiconductor manufacturing and design.

Canon Nanotechnologies and Toshiba are closely collaborating on the development of nanoimprint lithography technology. Both companies presented papers on Tuesday morning at the SPIE Advanced Lithography conference in the session devoted to “Nanoimprint Lithography Production Readiness.”

The eBeam Initiative additionally announced that it will expand its education efforts in 2016 to support the development of extreme-ultraviolet lithography, multi-beam mask writing, and nanoimprint lithography, all of which employ e-beam techniques in producing photomasks, or master templates in the case of NIL.

“People believe multi-beam is going to happen,” said Aki Fujimura, chief executive officer of D2S, the managing company sponsor of the e-beam group. He cited the group’s annual survey of industry figures, who last year predicted multi-beam mask-writing tools would be used in high-volume manufacturing for critical-layer photomasks by the end of 2018. This industry acknowledgement of advances in multi-beam mask writing “gives confidence,” Fujimura said at the eBeam Initiative’s annual luncheon at the SPIE Advanced Lithography symposium.

More than 100 luncheon attendees heard presentations by representatives of Dai Nippon Printing, the photomask manufacturer; imec, the research and development organization based in Belgium; and NuFlare Technology, a supplier of e-beam mask writers, mask inspection systems, and epitaxial reactors.

Naoya Hayoshi of DNP reported on the basics of NIL, which he said faces “some challenges, as in mask making.”

Praveen Raghavan of imec spoke about the organization’s development of test chips with 5-nanometer features. One was made with self-aligned quadruple patterning, using a 193i immersion scanner, while the other was fabricated with an EUV scanner.

The EUV technology offers “significant wafer cost benefit and enables 2D BEOL,” Raghavan said.

NuFlare’s Hiroshi Matsumoto spoke about the company’s forthcoming MBM-1000 multi-beam mask-writing system, an alpha version of which is currently in operation at the NuFlare facilities in Yokohama, Japan. NuFlare plans to offer a HVM version of the MBM-1000 by the end of this year, he said, with delivery in the fourth quarter of 2017.

The MBM-1000 is targeted at production of 5nm chips, while its successor, the MBM-2000, will address fabrication of 3nm ICs, according to Matsumoto. The MBM-2000 will be released in 2019, he said.

Optimism Reigns at SPIE Lithography Conference, Despite Challenges

Tuesday, February 23rd, 2016

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By Jeff Dorsch, Contributing Editor

Semiconductor manufacturing and design is growing increasingly complicated and just plain hard. Everyone knows that. The bad news is it’s only going to get worse.

Relax, there are many smart people gathered in San Jose, Calif., this week for the SPIE Advanced Lithography Symposium to discuss the challenges and figure out how to surmount them.

The changes required in lithography and related technologies to continue IC scaling promise to be painful and costly. Mitigating the pain and the cost is a common theme at the SPIE conference.

The annual SPIE Advanced Lithography conference is often dominated by discussions on the state of extreme-ultraviolet lithography (EUVL). In presentations on Sunday and Monday, the theme was generally the same as 2015 – EUV is making progress, yet it’s still not ready for high-volume semiconductor manufacturing.

Intel Fellow Mark Phillips said the technology has seen “two years of solid progress,” speaking Sunday at Nikon’s LithoVision 2016 event. He added, “There’s no change in Intel’s position: We’ll use EUV only when it’s ready.”

Anthony Yen of Taiwan Semiconductor Manufacturing covered the 30-year history of EUV development in his Monday morning presentation at the SPIE conference. Asked during the question-and-answer session following the presentation on when the world’s largest silicon foundry will use EUV, Yen stuck to the official company line of implementing EUV in production for the 7-nanometer process node, after some involvement at 10nm.

Seong-Sam Kim of Samsung Electronics also sees EUV realizing its long-aborning potential at 7nm, a node at which “argon fluoride multipatterning will hit the wall.” He touted the 80-watt power source Samsung has achieved with its NXE-3300 scanner from ASML Holding, saying it had maintained that level over more than eight months.

Intel’s Britt Turkot reported 200W source power “has been achieved recently,” and said the tin droplet generator in its ASML scanner has been significantly improved, increasing its typical lifetime by three times. EUV has demonstrated “solid progress,” she said, including ASML’s development of a membrane pellicle for EUV reticles.

While work with the ASML scanner on Intel’s 14nm pilot fab line has been “encouraging,” Turkot said, she added, “We do need to keep the momentum going.” Intel sees EUV entering into volume production with 7nm chips, according to Turkot. “It will be used when it’s ready,” she said.

EUV technology has shown “good progress” in productivity, while its availability and cost considerations have “a long way to go,” Turkot concluded, adding, “We need an actinic solution for the long term.”

An industry consensus has emerged that EUV will be used with ArF 193i immersion lithography in the near future, and this trend is likely to continue for some time, according to executives at the SPIE conference. There may also be wider adoption of directed self-assembly (DSA) and nanoimprint lithography technology, among other alternative lithography technologies.

Mark Phillips of Intel pointed to complementary implementation of EUV and 193i. “We must use EUV carefully,” he said. “We need to replace three-plus 193i masks.” Phillips added, “EUV can’t be applied everywhere affordably. 193i will continue to be used whenever possible.”

Nikon executives touted the capabilities of their new NSR-S631E ArF immersion scanner, introduced just before the SPIE conference. The new scanner can turn out 250 wafers per hour, and can be pushed to 270 wph with certain options, according to Nikon’s Ryoichi Kawaguchi.

Yuichi Shibazaki of Nikon said the company will next year introduce the S63xE scanner, improving on S631E.

For all the challenges of transitioning to 7nm and beyond, executives at SPIE remain optimistic about solving the issues of 193i multipatterning, DSA, and EUV. Harry Levinson of GlobalFoundries said in response to a question, “The ultimate resource is the human mind.”

Blog review March 9, 2015

Monday, March 9th, 2015

Pete Singer is delighted to announce the keynotes and other speakers for The ConFab 2015, to be held May 19-22 at The Encore at The Wynn in Las Vegas. The line-up includes Ali Sebt, President and CEO of Renesas America, Paolo Gargini, Chairman of the ITRS and Subramani Kengeri, Vice President, Global Design Solutions at GLOBALFOUNDRIES.

Mark Simmons, Product Marketing Manager, Calibre Manufacturing Group, Mentor Graphics writes about cutting fab costs and turn-around time with smart, automated resource management. He notes that the competition for market share is brutal for both the pure-play and independent device manufacturer (IDM) foundries. Success involves tuning a lot of knobs and dials. One of the important knobs is the ability to continually meet or exceed aggressive time-to-market schedules.

Paul Stockman, Commercialization Manager, Linde Electronics blogs that there is an increasing demand for and focus on sustainable manufacturing that will contribute to a greening of semiconductors. This greening must be robust and responsive to change and cannot constrain the individual processes or operation of a fab.

Applied Materials’ Max McDaniel writes on the quest for more durable displays. He says the same innovators who created such amazingly thin, light and highly functional smartphones (with the help of Applied Materials display technology) are already developing durability improvements that may eliminate the need for protective covers.

Batteries? We don’t need no stinking batteries, says Ed Korczynski. We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources.

With the 2015 SPIE Advanced Lithography (AL) conference around the corner, some people have asked me what remaining EUVL challenges need to be addressed to ensure it will be ready for mass production later this year or next.  Vivek Bakshi of EUV Litho, Inc. provides thoughts on this topic and what he expects to hear at the conference.

Phil Garrou continues his look at presentations from the Grenoble SEMI 3D Summit which took place in January, focusing on an interesting presentation by ATREG consultants on the future of Assembly & Test.

On Tuesday, January 20, President Obama once again stood before a joint session of Congress to deliver a State of the Union Address.  With the newly seated Republican-controlled Congress and his Cabinet present, the President discussed topics ranging from the current state of the economy to foreign affairs and his ideas on how to move the nation forward.  Jamie Girard of SEMI was pleased to hear that the President supported multiple policy goals including expansion of free trade, corporate tax reform, support for basic science research and development and others.