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Posts Tagged ‘EUV lithography’

Defect-Free Mask Blanks Next EUV Challenge

Monday, September 16th, 2013

By Pete Singer

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

Figure 1 shows an EUV mask, which is considerably more complicated than conventional photomasks. The EUV mask begins with a substrate. On the back of the substrate you have some material that’s used for chucking (an electrostatic chuck is used to hold the mask to a stage in the ASML tool and in the Veeco ion beam deposition tool). On top of the substrate is a multilayer sandwich made up of 40-50 moly silicon pairs that creates a mirror. A ruthenium capping layer helps protect the mask. The top layer is an absorber, and that’s what gets patterned.

The photo at the bottom right of Fig. 1 shows a small pit on the substrate. “As the multilayer gets deposited on top of it, you take what in the beginning might have been a small pit and at the top it becomes 1.5X or so larger,” Pratt said. “This a common problem with EUV. These very small pits and bumps on the substrate, because of the deposition angles, the way that the multilayer is put down, as small non-killer defect on the substrate suddenly becomes a killer after deposition.”

The left photo is a larger particle that fell on the blank during deposition. Pratt said that even if you could mill that down and make it level, you would just never get the reflectivity out of the section that you need.

Where is EUV today? Billions have already been invested to build the EUV infrastructure with particular emphasis on the light source. Chipmakers have invested in ASML, and ASML acquired light-source provider Cymer. There has also been a very large Industry investment in Zeiss to build the AIMS tool, which is a defect detection and repair system at EUV wavelengths.

In July, ASML said NXE:3300 scanner imaging and overlay performance reached levels where they are engaging with customers on a strategy for the 10nm logic node insertion (23nm half pitch). Good imaging performance was shown down to 13nm half pitch, and overlay between the NXE:3300 and NXT systems, had been demonstrated at less than 3.5nm. Good performance, stability and reliability of the pre-pulse source concept was demonstrated with a rate of around 40 wafers per hour, and ASML expressed confidence in reaching the goal of 70 wafers per hour productivity in 2014.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production. Number one on that list is the mask defects. Mask defects can come from all different sources during the entire process, from the substrate all the way through to usage in the fab,” Pratt said. “The most dangerous (un-repairable) defects come from the ML (multilayer) coating process during mask blank manufacturing. You can’t clean them and you can’t repair them and if you have more than some very small amount, there’s really nothing you can do about it. You just have to throw that mask blank away and try again, which creates a very large selling price for the mask blanks. Not just because they are difficult to make but you’re throwing away a substantial amount of what you’re trying to sell,” Pratt said.

Click to view full screen.

Figure 2 illustrates the process flow for a EUV mask blank. After a substrate polishing process, the substrates goes from the substrate supplier to the mask blank supplier. At the mask blank supplier, they will deposit the multilayer, the fiducial mark and the deposition. The blank gets sold to the mask shop, which could be either captive or a merchant. That blank, which is basically a mirror at the point, gets patterned and inspected and sent off to the fab. Pratt said that once the mask hits the mask shop, there is a little more leeway in terms of the defects because the defects that occur in the mask show are usually on top. “It’s usually absorber type defects or patterning type defects and those are a lot more easily repairable,” he said.

Click to view full screen.

Figure 3 shows the timeline of Veeco’s system developed, starting with a research system developed in 1996 that went to Lawrence Berkeley. The was optimized in the 2003-2010 timeframe, which included work with SEMATECH in a joint development program. That basically turned it into what Pratt describes as an R&D system. “We have a system that is being used for all the mask blanks in the world. But those mask blanks are really R&D blanks that people use for print checks and reflectivity checking, but certainly nothing they would use in a fab yet, or expect to get yield off of,” he said. “A lot of the time, you don’t know if it’s yielding or not until the very end of the process.”

Pratt said they have seen some improvements when it comes to defects. “We’re not yet where we need to be for logic high volume manufacturing, but we’re getting close to where we need to be for memory.” The real issue is the low yield. “At the current yields, that mask blank makers would need to spend a whole lot of money, probably on the order of $3 billion or so, on capital to meet what the mask blank demand would be over the next five years. That’s just not feasible. EUV clearly can’t ramp in that scenario,” Pratt said.

Veeco is addressing the defect challenge in two ways. The short-term solution is an Odyssey upgrade. The longterm solution is a new platform. “The Odyssey upgrade improves the yield of the tool. But then longer term we think the next gen is needed, especially as you get out to years 4 and 5 where high volume manufacturing starts to occur,” Pratt said.

The ion beam deposition system in shown in Figure 4. The target assembly rotates, so the process might start off with silicon, the assembly is then rotated to deposit molybdenum and rotated again to deposit ruthenium. The problem is that the ion beam doesn’t always direct hit the target. “You might have some of these high energy ion missing the target and hitting the chamber. The chamber has shields on it, but that ion can bounce around and when it hits the shields, there’s a chance that it can knock off particles,” Pratt said.

The Odyssey upgrade will: reduce source to target ion overspray and reduce high energy reflected neutrals. New ion source optics are planned as well as a larger target size. Lower beam energy operation and lower pressure operation are also planned. Those should have two benefits.

Longer term, the next generation EUV ML system will focus on particles and CWL (center wavelength) process repeatability (CWL is a measure of how reflective the mask is). The new platform will minimize particle proximity, and accommodate new source technology. A larger chamber, out-of-plane deposition geometry, low-defect clamping and integrated endpoint control are also planned. Figure 5 shows progress in defect reduction from 2004 to 2012.

If you have some news to share, send me an e-mail at psinger@extensionmedia.com.

IEDM Preview: 20nm and Below

Sunday, November 11th, 2012

By Pete Singer

As the industry works to perfect 28nm devices in volume manufacturing and early 20nm processes, attention is focusing on next-generation 14nm and below technologies.

There have been three primary drivers in the semiconductor industry for the last four decades: Area, power/performance and cost. The well-known push to cram more functionality onto a single chip through continued scaling — or into a single package through 3D integration and other advanced packaging techniques — has been well documented. Today, with the exception of Intel, the industry’s leading edge devices in high volume manufacturing have critical dimensions of 28nm. Intel, racing ahead, introduced the 22nm IvyBridge chip in 2011 and has announced plans to have 14nm by the end of 2013. How long this kind of scaling can continue is the subject of some debate, with most recognizing the EUV lithography will be required at some point, most likely for the 10nm generation (Intel has said it doesn’t need it for 14nm).

It’s clear, though, that continued scaling is running out of steam, and that the industry most look for other means by which to say on the path defined by the proverbial “Moore’s Law.” Those advances are one of the primary focal points of the upcoming 58th annual IEEE International Electron Devices Meeting (IEDM), which will take place December 10-12, 2012 at the San Francisco Hilton Union Square. The conference will be preceded by a day of short courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.
As reported in last month’s issue, highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to ever smaller sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

Following, we’ve assembled a list of the “be sure not to miss” papers and sessions slated for IEDM 2012.

Invited papers

In the plenary session, imec’s Luc Van den hove, will describe how ultimate transistor and memory technologies are the core of a sustainable society. He says that several key societal challenges in domains such as healthcare, energy, urbanization and mobility call for sustainable solutions that can be enabled by combining various technologies. These solutions will be backboned by wireless sensor systems, smart mobile devices and huge data centers and servers, the key constituents of a new information universe. They will require extreme computation and storage capabilities, bound by (ultra)low-power or heat dissipation constraints, depending on the application. This drives the need, he says, to keep on scaling transistor technologies by tuning the three technology knobs: power/performance, area and cost. To get to ultra-small dimensions, advanced patterning integration, new materials such as high-mobility Ge and III-V materials, and new device architectures such as fully depleted devices are being introduced. This comes along with an increasing need for process complexity reduction and variability control. Equally important are the continued R&D efforts in scaling memory technologies. NAND Flash, DRAM and SRAM memories are now approaching the point where new scaling constraints force exploration of new materials, cell architectures and even new memory concepts. This opens opportunities for resistance based memories such as resistive RAM, phase-change RAM or spin-torque transfer magneto resistive RAM.

In another invited paper, in the regular sessions, researchers from Micron and Intel will discuss scaling directions for 2D and 3D NAND Cells. They note that many 2D NAND scaling challenges are addressed by a planar floating gate (FG) cell, which has a smaller aspect ratio and less cell to cell interference. Figure 1 compares a wrap FG cell (left) and a planar FG cell (right). The wrap cell is limited by a required aspect ratio of >10 for both the wordline and the bitline direction in a sub-20nm cell. The planar cell eliminates this limitation.

Of course, not all IEDM presentations are focused on leading-edge logic and memory. In the plenary session, John Rogers from the University of Illinois at Urbana-Champaign, will talk on bio-integrated electronics. He notes that biology is curved, soft and elastic, while silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. He plans to cover ideas for electronics, sensors and actuators that offer the performance of state-of-the-art, wafer-based systems but with the “mechanical properties of a rubber band.” He’ll explains the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ’tissue-like’ devices with unique diagnostic and therapeutic capabilities, when conformally laminated onto the heart, brain or skin.In the third plenary talk, Joo-Tae Moon of Samsung Display will give a talk titled “State of the Art and Future Prospects in Display Technologies.” There are two parts which satisfy this vision, he notes. One is the picture quality and the other is design of the display. From picture quality point of view, bigger screen size and higher pixel density are the main factors. The need for a bigger screen size requires expediting technologies with lower RC delay and higher transistor performance. Higher pixel density mandates a smaller unit pixel area and each unit pixel has the dead space for the transistor and metal line which is protected from the light by the black matrix. Clearly, the design factor is the one of the main driving forces for the changes from CRT era to flat panel display era, he says.

Notable papers

imec, in a paper titled “Ultra Thin Hybrid Floating Gate and High-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology,” will describe — for the first time — a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. Figure 2 is a TEM image of a polysilicon/TiN HFG cell. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al2O3) and an n-type polysilicon CG.

In a paper jointly authored by GLOBALFOUNDRIES and Samsung, titled “Stress Simulations for Optimal Mobility Group IV p- and n-MOS FinFETs for the 14 nm Node and Beyond,” researchers provide calculations of stress enhanced mobilities for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond. Results indicate that both for nFETs and pFETs, Ge is “very interesting,” provided the correct stressors are used to boost mobility. Figure 3 is a XTEM of a Ge-channel FET with SiGe source/drain. They conclude that strained channels grown on a strain relaxed buffer is effective for 14nm nodes and scalable to future nodes. TCAD simulation trends are experimentally confirmed by nano-beam diffraction (NBD).

Luncheon presentation

Ajit Manocha, CEO, GLOBALFOUNDRIES, Inc. is sure to provide an interesting luncheon talk on Tuesday, December 11th, addressing some recent jabs from Intel’s Mark Bohr. The title of Manocha’s talk: “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!”

Manocha says that industry experts and observers have predicted for a long time that the fabless model has some cracks in it, and may in fact be headed for extinction at some point. “We in the foundry industry dismissed such chatter as we continue to enjoy growth rates that outpace the overall semiconductor industry,” he notes in his pre-conference abstract. “But it wasn’t until an executive from — surprise — Intel officially declared the fabless model is collapsing recently that many of us really got our feathers ruffled. We firmly believe that the rumors of its death are greatly exaggerated. Evidence would seem to support that it is actually the IDM model which is dead, survived only by a very small number of anomalies that have either the financial wherewithal or stubbornness to continue down this path.”

The foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together, says Manocha. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy. Recent talks of fabless companies investing in their own fabs, and of foundries developing single company fabs’ underscore the sense of urgency. “Clearly, we must change – Call it Foundry 2.0,” he says.

Unprecedented technical and business challenges have driven semiconductor manufacturing to this new fork in the road. On the one side is the option to ‘go it alone’, an option available to less than a handful of companies. The temptation here is to circle the wagons, dig deep into the bank and develop an optimized, but relatively closed, solution that will hopefully work for most every need. Manocha said a second option, ironically, is a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies. “With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration ‘early, often and deep’ is really the only practical approach given the cost and complexities involved,” he said.

Evening panel

One of the two evening panels on Tuesday at 8pm is titled “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” The moderator will be Suresh Venkatesan of GLOBALFOUNDRIES. He notes that the 22nm node spelled the dawn of the fullly-depleted device architecture with the implementation of FinFETs as the workhorse of the technology. However, projecting out to the 10nm node and beyond the scalability of the FinFET architecture, the materials systems used to create it, and the fundamental electrostatics and parasitic components associated with the transistor once again loom large as significant challenges that need to be overcome.

A New Era for Equipment Suppliers

Saturday, September 1st, 2012

By Pete Singer

The semiconductor equipment industry received quite a jolt recently. In July, lithography equipment supplier ASML announced a customer co-investment program that enabled minority equity investments in ASML (up to 25% total) by its largest customers. Customers could also make commitments to fund ASML’s research and development (R&D) spending for future programs.

Intel was the first investor, acquiring 15% equity ownership interest in ASML. R&D funding and equity investment agreements totaled approximately $4.1 billion. Part of the deal was a contractual commitment from Intel for advance purchase orders for 450 mm and EUV development and production tools from ASML. ASML has said the results of the technology investments will be available to every semiconductor manufacturer with no restrictions.

In August, TSMC joined in, taking a 5% stake in ASML, worth about $1.04 billion. TSMC also committed about $341 million, spread over 5 years, to ASML’s R&D programs.

The Intel announcement made instant believers out of many that both EUV and 450mm would actually happen. Both technologies have been significantly delayed beyond initial target dates, and the thinking was that some massive investment would be required to get them production-ready in a reasonable timeframe (i.e,. 2015-2020). $5+ billion is a pretty good start!

Not only does it seem to ensure that EUV will succeed, but it removed one of the most significant barriers to 450mm development. Even if 450mm solutions were developed for all the other types of process equipment — deposition, etch, ion implant, CMP, cleaning, etc. — it would be going nowhere without EUV. Now, seemingly overnight, 450mm seems inevitable.

It is a new era for semiconductor manufacturing equipment suppliers, for they must now seriously tackle the 450mm challenge, but don’t expect a blossoming new model based on customer co-investments anytime soon. There are at least two competitors in other markets, and developments will likely be funded the way they always have been — though good old-fashioned capitalism.


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