By Mark LaPedus

A group of 19 European companies and academic institutions have launched a three-year, 360 million euro ($464.5 million) pilot-line project to support the industrialization of fully-depleted silicon-on-insulator (FD-SOI) technology.

The project, dubbed Places2Be, is led by one of the biggest proponents of FD-SOI–STMicroelectronics. In addition, STMicroelectronics and GlobalFoundries will provide the manufacturing capabilities for the program. Separately, GlobalFoundries is also joining Imec’s advanced MRAM project.

Meanwhile, Places2Be, which stands for “Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe,” is aimed to support the deployment of FD-SOI pilot lines at 28nm and beyond.  It will also drive the creation of a European microelectronics design ecosystem using this FD-SOI platform and explore the path towards the next step for this technology at 14nm and 10nm.

The FD-SOI manufacturing sources for the project are located in two fabs. The first is the pilot line in STMicroelectronics’ Crolles fab, near Grenoble, France. The dual-source is in GlobalFoundries’ fab 1 in Dresden, Germany. STMicroelectronics and IBM are the biggest proponents for FD-SOI. Not long ago, STMicroelectronics signed an FD-SOI foundry deal with GlobalFoundries.

FD-SOI is a low-power, high-performance alternative to conventional bulk silicon and finFET technologies. The first FD-SOI systems-on-chips are expected to be used in consumer electronics, high-performance computing and networking.

The project includes participation of 19 partners from 7 countries, and the planned involvement of about 500 engineers over three years across Europe. Places2Be is the largest ENIAC Joint Undertaking project to date and is supported as well by the National Public Authorities in the participating countries. The ENIAC JU was set up in 2008 and will allocate grants throughout 2013. The projects selected for funding shall be executed till December of 2017. The total value of the R&D activities generated through ENIAC JU is estimated at 3 billion euros ($3.8 billion).

“The Places2Be project will reinforce the ecosystems of both Grenoble and Dresden clusters, while also positively impacting the whole value chain of microelectronics in Europe–large companies, SMEs, start-ups and research organizations–beyond the direct impact induced by the material and IP investments,” said François Finck, director of ST’s R&D cooperative programs and project coordinator, in a statement.

The Places2Be members include ACREO Swedish ICT AB,  Adixen Vacuum Products,  Axiom IC, Bruco Integrated Circuits, Commissariat à l’énergie atomique et aux énergies alternatives, Dolphin Integration,  Ericsson AB, eSilicon Romania S.r.l., Forschungzentrum Jülich Gmbh, GlobalFoundries Dresden, Grenoble INP, IMEC,  Ion Beam Services, Mentor Graphics France Sarl, Soitec, ST-Ericsson, STMicroelectronics, Université Catholique de Louvain, and the University of Twente.

In a separate move, GlobalFoundries is joining Imec and others to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology. The first IC manufacturer to join Imec’s R&D program on emerging memory technologies, GlobalFoundries completes the value chain of Imec’s research platform.

GlobalFoundries is joining a team with Qualcomm and several worldwide equipment suppliers providing the complete infrastructure necessary for R&D on STT-MRAM. In January, Qualcomm joined Imec’s STT-MRAM program.

STT-MRAM technology is a promising high-density alternative to existing memory technologies, like SRAM and DRAM. Together, imec and the program members aim to explore the potential of STT-MRAM, including performance below 1ns and scalability beyond 10nm for embedded and standalone applications.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: Are we starting to blur the lines between what’s a packaging house and what’s a fab with stacked die?
Woychik: Yes, and the blending of the IC fab and the packaging house is absolutely necessary to pull this off. The major fabs are bringing the two together. The foundries are bringing in the packaging guys because they need the packaging discipline to do assembly. How do you assemble it with other materials to make sure you get high yield? That’s going to drive cost. At the same time, you have to make sure the reliability requirements are met.
Movva: That’s not a novel concept. It’s been done in the industry, and it gives flexibility to the fabless companies where you can mix and match different suppliers and different applications. What’s interesting about 2.5D is that it takes it to the next level. Now the foundries and SATs (semiconductor assembly and test companies) are working more closely together. Characterization needs to be done up front. Standards need to be developed so both entities understand what the outputs and inputs are. One a conceptual level this exists. It just needs to be elevated to the next level.

SMD: As we start bridging what were previous silos, we will also need to start bridging the tools used by each. How far along are we?
Movva: It depends on the business model and where the partnering is happening. If there are certain processes done by the fabs, they can do the same process for 2.5D and 3D, like micropillar bumping and stacking. That isn’t new. But if there are certain aspects used specifically by the fabs, then those technologies will need to be developed by the OSATs. It depends on the business model and where the handover happens.
Woychik: The design tool guys already are working with the packaging house. This is where the packaging guys develops test vehicles, and that information is used in the next generation of EDA tools, which is then used in the fab. That’s a classic case of the need for integration. We’re doing the packaging, but that has a key driver on these design guidelines, and it has an effect on EDA tools used by the fabs to develop 3D solutions.
DeLaCruz: The EDA tools are close to where they need to be, but they can’t quite handle it as they currently exist. For example, if you’re doing physical design you generally can only load in one design rule set. If you’re going to design in 40G, you also can’t bring in a 130nm design rule set at the same time for a different chip. If they’re all the same technology, the tools can work with some minor modifications. If you bring in different technologies, they choke. That’s one problem. For simulation, there are no good models available for a TSV. There are so many different flavors of TSVs—you have small tungsten-filled ones, long copper-filled ones, conformal-coded ones where they’re not fully filled with copper—and they all have different electrical properties. Once we have a standard, these tools vendors will modify their tools to include that. We’re not there, and they’re waiting for someone to emerge as a clear leader so they can figure out where to best spend their time.
Baldwin: Today if you have a 40 million-gate device, which could be a processor or some sort of complex ASIC device, you’re going to get a 1,000-page or 2,000-page data sheet. People are going to come through and say, ‘Here’s the product and here’s the data sheet, go implement this device.’ And you have three months. You can’t even read it. And you have to go through and integrate it. And you have board work around it, and you have to model it and simulate it. With 3D we have the potential to bring in processors and memory and analog. Does that bring in an era where we can get rid of these data sheets and build completely integrated systems that can be integrated into a larger system in a useful amount of time? There are issues with integration of cost and power, but the big one is schedule.

SMD: Are the test tools integrated with other tools?
Pateras: They’re separate worlds, other than for things like Verilog netlists and RTL and constraints. Aside from those, they’re really separate flows. The issue with test is you need to have control of all the various parts. If you don’t, that’s where standards come in because we don’t have a solution.

SMD: How do we deal with proximity effects like leakage, noise, electrostatic discharge and electromigration?
Movva: 3D proximity effects could be mechanical, electrical and thermal. There are areas where you could characterize and create tools. It’s not possible to characterize all combinations and features, so you’ll have to use simulation to create certain rules based on what is permissible.
DeLaCruz: From an ESD standpoint, the interconnects that are designed to be solely from chip to chip don’t need ESD interconnects. But that assumes you know how that chip will be used in every possible situation. That makes it very difficult. If there is an interconnect that goes chip to chip in one format, it might be lead system in another version. So now you need to raise it above the core voltage and put ESD protection on it. This is all going to waste power and you will lose a lot of the benefit of the 3D architecture. As long as you know well ahead of time that these banks of I/O are not going to do anything but talk to another chip in my 3D and 2.5D architecture then they don’t need higher voltage, buffers or ESD protection. From an electromigration standpoint in the TSV, that’s really going to come down to the reliability of the oxide or whatever else is put into the via layer. Right now most papers are related to a certain thickness of oxide, but we all know it’s pretty brittle and it could give us leakage problems. It’s not well understood this point, and that’s part of the risk.

SMD: How about in test? Is there any focus on physical effects yet?
Pateras: We’re right now addressing it as if the defects we will have to deal with will be the same as in 2D. We’re just looking at accessibility and observability of the various components such as TSVs. Whether or not there are defect mechanisms that we would see with general interconnects is unknown.

SMD: And from a packaging side, the goal has always been the cheapest package. Will that change?
Woychik: When anyone hears packaging they still require low cost. That will still be the case with stacked die. That’s also why it’s so important to address these packaging issues right now. A lot of people have focused at the fab level. There needs to be more focus on the packaging level to address assembly and yield and also reliability. There are no showstoppers. It’s just a refinement of the technology. This is an extension of the work we’re already doing in packaging to drive a lot of these models. When you start building these structures and do the detailed metric measurements, this produces good information for EDA tools.

SMD: How about an exchange of data between vendors in other areas?
DeLaCruz: Outside of memory, there is very little activity going on with die-to-die information standards. There’s no reason to have multiplex signals raise the voltage as you go from chip to chip. But there’s no I/O interface standard for chip-to-chip.
Woychik: But there are cases where it’s working and other cases where it’s not working. What you’re seeing is OEM drivers helping to develop the infrastructure. For example, Xilinx got together with TSMC, Ibiden and Amkor to pull off this solution. These OEMs are driving it, and you’ll see more and more of that happening. That’s the early stage of larger-scale integration that will have to happen to make this a reality.
Pateras: We definitely need some information to be provided if the various die are coming from multiple sources. If you look at a memory stack on logic, if you’re going to test that memory die with self-test on the logic die, you need to know the memory’s address space, its physical scrambling, redundancy and how it’s architected. In 2D, that kind of information is being provided by the memory vendors. In a 3D world, these frequently are different vendors. They’re not involved in that kind of information exchange right now. That will have to change.

SMD: Will the supply chain get bigger because of stacking or will it shrink?
Movva: There won’t be a change in the supply base. What will change is the partition between the different players, where one takes over from the other.
DeLaCruz: I disagree. No matter what, you have at least one more link in the supply chain—someone stepping in to provide tiles. If you’re vertically integrated, that’s not a big deal. But if you’re trying to source a PLL, voltage regulator or SerDes from all these different players, who’s is in charge of taping out these tiles? Who’s going to inventory them and make sure they’re all test-compatible with each other? That’s a link in the supply chain that doesn’t exist today. Right now no one is the world leader in that role.
Woychik: There’s a battle brewing between who’s going to take ownership for these parts, and it’s not clearly defined. The packaging house will certainly take on a bigger responsibility than it has in the past.
DeLaCruz: I’m not so sure the packaging houses will have the appetite for taking on ownership and inventory. They’re going to want to see it come ready for assembly. What they will grow into is more assembly practices.
Woychik: The classic case is the PoP module, which is well-defined with the logic on the bottom and the memory on the top. With a 3D TSV, who takes this on? There’s a business risk.
Baldwin: If you think about PCB design and then you take this concept forward into 3D design, maybe you’ll have a die that’s a PLL or a SerDes or a logic block or memory block. You can imagine a Lego build in 3D. But if there’s too much complexity in packaging, assembly and test, what we will need are larger constructs. So what is the optimal process for any function? With 3D there will be an analog wafer, and that analog wafer will probably be 0.13 (microns). There will be a digital die at a lower geometry for integration. And then you can think about how these functions will be pushed up and down through this die stack. The conclusion is that you will have vertical-specific subsystems. You’ll have to. If someone is providing analog subystems, they’ll have to say, ‘This is the analog subsystem of a cell phone or a tablet or a WiFi system.’ And they’re going to have to provide these. Only after they’ve been integrated can we start dealing with the inefficiencies of aligning TSVs and making sure the modeling is correct so you can integrate it into a 3D stack. That’s going to force aggregation around function.
Woychik: That’s where 2.5D can play a very nice role, and why it will play an important role. That’s a likely interim solution. Then way when you go to 3D, you’ll be more prepared to deal with the business issues of who does what.
Movva: The business model is one of the biggest issues. Who owns the logic and who owns the memory? Those are the kinds of questions the industry has to address. That may be the biggest hurdle for the adoption of 3D.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: What’s driving the push toward 3D stacking?
Baldwin: The customers have a function they need to get to market. They’re integrating for power. They’re integrating for area. They’re also integrating for cost. They come to us with a problem and say, ‘Help us get this solution to market.’ Part of our solution is going to be standard design services. Part of it could be in the form of a die library, which is a menu of tiles. Die libraries have a lot of promise. You have building block functions that are captured at the die level with industry-standard TSV spacing, test methodologies—all the things that allow us to make a Lego building-block stack out of disparately sourced devices. This is a good idea. It’s difficult with today’s technology.

SMD: That brings up an interesting point, which is exactly what we mean when we refer to stacking. We have memory, memory on logic, and 2.5D stacks in a package. For each the problems are different. Where do we start?
DeLaCruz: Those are different solutions to different problems. A 3D stack is going to be very small and compact. Putting lots of large die together in a 3D stack is not going to make a lot of sense. There will be a lot of reasons for 2.5D, though. If you do the math, it may be less expensive to do a 2.5D solution than to make one large monolithic solution. From an NRE risk standpoint, re-using tiles that are proven and well-known will reduce the risk. The only reason that people go to 28nm or 22nm is they have one or two IP blocks on there that require going to that smaller node, whether it’s memory or the processor. Once it’s done and proven out, it’s likely that everything else can be done at a lower-cost node. Being able to put things together in a larger area space is where 2.5D will have its sweet spot. It will be a lot less expensive. But the 3D arena is more of a space-constrained environment. Having very high-powered devices in a 3D environment is not going to work out too well. It works very well in the mobile market where space is important and low power is the key.
Movva: From a technical aspect, 2.5D addresses the mechanical reliability and thermal aspects. You don’t have to directly characterize the effects of the vias on the node due to the interposer.
Baldwin: The idea of an interposer sounds very evolutionary from today. Just like we’re using package substrates for multichip modules, we can use an interposer inside the package and gain greater density. But now your tools can’t fully model the electromagnetic effects of a through-silicon via. How you’re going to handle that is to space off at first so there’s a do-not-use zone around each via. But you have an interposer, which doesn’t have a ground plane, so now you need coaxial-type TSV structures going down into the interposer and asserting some sort of electrical level. And now you have a large area that’s do-not-use, and you ask all your providers of these die libraries who is willing to make their die less optimal so it gains this potential of use in a 2.5D or 3D package? Who will increase their unit cost to support this potential function?
Woychik: Talking with the users, everyone agrees 3D is the way this is going to go. But getting there will be non-trivial. It’s a big job because you have to look at ‘keep off’ zones. How do you come up with a design tool to lay out the TSV. This is where the 2.5D silicon interposer plays a good role because it provides a useful means to get there and it’s a good learning tool. The classic case we’ve all been hearing about is the Xilinx Virtex 7. The main driver for that is how you get a large die that yields sufficiently. They’re able to yield smaller pieces that integrate on silicon substrate. That gave them about 95% of the performance. That was a major enabler. At the same time, it helped drive the interposer technology. To do that in a 2.5D device is non-trivial. You take baby steps before you take the big one, and that will help drive the total 3D solution. Meanwhile, we see 2.5D won’t go away.

SMD: Is there any standardized way for testing 2.5D chips?
Pateras: You can apply some of the 3D approaches. Typically you don’t need them in 2.5D. With 3D, Imec has developed a test elevator concept because there’s no accessibility to the die that are stacked. You have access to the bottom and top die, but there’s no access anywhere else. So you have to use TSVs to get from one die to the next. With 2.5D, very often the die you’re placing on an interposer have access to the outside world. There’s less of a need to create a complex infrastructure for access test resources like built-in self-test and scan chains.

SMD: This industry has had mixed results with standards. The dueling power formats are a case in point. Will we able to move with standards in a stacked die world and have we really learned any lessons.
Movva: There is a lot of momentum that started several years ago in standards for design, manufacturing and even handling. The handling is going to be critical when there are multiple companies involved. But all of that is needed to enable the 3D supply chain. We would like to see that momentum continue.
Pateris: I’m optimistic, particularly in test. If you look at history, we’ve tended to narrow in on some well-adopted standards for test. Going back 20 years, we combined various chips at a board level and developed IEEE 1149.1 and the JTAG (Joint Test Action Group) standards. There are only a couple standards being developed for 3D and there are contributions from all the major players. My feeling is they will be successful.

SMD: How good or bad will the effect of disaggregation be on stacking?
DeLaCruz: The various different standards for test and wafer handling are moving. But there is nothing dealing with the interconnects. You didn’t really have to worry about those before because everyone could handle their own stuff as long as they could fit it into a package. But to design one of these tiles to go into a 3D tile is not the same as you would design the interconnect to go into a 2.5D structure. In 2.5D you don’t have your signals on all four sides because it would require using too many layers of an interposer to route them all over. Dropping the cost of the interposer by reducing the number of layers is very important. The number of layers in an interposer is a big cost savings. Planning out these tiles ahead of time is important. But will the design of a tile be for the 3D space, where interconnects are over the entire area, or with 2.5D where the interconnects are mostly on one or two adjacent edges. That’s where I don’t see any standards.
Baldwin: If you look at the foundries and their business model, 3D is a clear inflection point. They have to maintain enablement. People that want to bring them business have to be able to do that. We can’t ask all the customers to take on 3D chip design. It’s something where people will need a concrete definition of what the chip needs to do and then a way to get it developed. That exists today in the digital realm. They can go to partners and get that implemented. Those two worlds are going to meet. We’re going to have companies whose role is to take the solution from the customers and take the enablement models that come out of the foundries and put the two together. So there will be a huge push from the ecosystem to make that happen. That will require standards and modeling. Currently they’re all working on drilling and filling, but there’s a lot more to come.
Woychik: This gets into the integration. It can’t work in a disaggregated environment. It has to be fully integrated. That’s where the packaging house can play a very important role. That’s where it can all come together. You’ll get into standards for design, test, how to lay out the die. And who’s going to make it? The packaging house. The package will drive the solution to get to the end customer. That’s why you’re seeing a close alliance between the packaging house and the IC fabs today. They both need each other.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: What are the big challenges in 2.5D and 3D?
Pateras: From a test perspective, what we need are more standards. How do you get data from one device to the next? How do you create tests that span more than one device? That means these devices have to be compatible in how they communicate test information and how they deal with embedded test capabilities. The EDA players need to get together and support similar test capabilities.
DeLaCruz: The challenge that was covered first was the technology. Where there hasn’t been a lot of attention is on the supply chain. Everyone has nice solutions, but the interconnect technologies are all different. So if you want to source a memory from one provider, a PLL from someone else, a voltage regulator from someone else, when you connect these things together they may all be different because everyone has their preferred solution. You need standards in test, but you also need them in interconnect technology to assemble it in the same location. The assembly guys are reluctant to give out design rules because they want to see what the prevailing trends are. If there are too many different styles of interconnect, it may be too difficult to handle—at least for the general ASIC market. On the other hand, you may have companies that are more vertically integrated and which have a hand in each of the chips that is in there. They can more easily put them together and design them the same way. But when they come from multiple locations, compatibility is going to be a major obstacle.
Woychik: What’s going to be very important with 2.5D and 3D is coming up with a fully integrated solution. What’s happening is there is a lot of expertise in one area, such as TSV formation at the wafer level. There’s a lot of work in test. But how do you bring all of these elements together to come up with a fully functional 3D IC device? When you look at it generically, 2.5D and 3D are very similar. The difference is that 3D is a functional device while 2.5D is a passive device. At the same time, you’re going to have to bring all these elements together to provide a total solution. In the industry we’ve become very fragmented over the last 10 to 20 years. This is going to really drive a blending of the IC fab with the packaging house to provide this solution. Once this happens, there ares going to be a lot of people who say they need it.
Baldwin: It starts with nomenclature. There are new terms that need to be created—things like test elevators and what you call the ball that sits on top of the through-silicon via. Is that different from a bump? We talk about tools issues. One of them is 3D extraction. We already have 3D extraction, but now we’re talking about to another die in the stack. Is that 3.5D? In thermal issues, if you’re looking at a thermal gradient that goes vertically through a die stack as opposed to a horizontal one, there are no words to describe these new issues and to work through with the customer how we’re going to solve these problems. A packaging house put together a presentation for a 10-die vertical stack for us, and they had all identical-sized die with perfectly aligned through-silicon vias. It was clear we don’t have the technology to build that today.
Movva: The technology is not ready. The standards are still to be decided. But the industry has come a long way in the past couple of years. There have been prototype lines set up by the foundries and at OSATs. Test methods have been developed and reliability has been improved. These are no longer the obstacles for 2.5D and 3D. The challenges we see are twofold. One is the cost. The other involves the business models. With any new technology there is a learning curve, so costs are higher. But what concerns us is that some of the risk elements of the new technology are being added as a premium to the price. Those come from the technical uncertainty and risk, and also the business model uncertainty and risk in terms of who owns the different processes. That is a major concern.

SMD: And what has to change with the business models?
Movva: When flip-chip was introduced there was a new technology called bumping. That technology got resolved. But with 2.5D and 3D, who owns the new process fabs? Is it a foundry process? Or is it an OSAT process? Where does the handoff happen? Those are big challenges, and they need to be resolved for this technology to take off.

SMD: One of the great advantages of this model, at least in theory, is time to market with customized solutions. But is it going to happen smoothly and will all the pieces go together?
Woychik: What’s really driving this is a fundamental need to address Wide I/O. At the same time, with Wide I/O, you have memory and logic. It’s going to have to drive the standards, and the right now standards are immature. They need to be developed. There will be standards for design, TSVs, packaging and thermal issues. And how is this going to get manufactured from the fab to the packaging house? If you look at packaging, it has a history of being an afterthought. The fabs would hand it over the fence to the packaging group and the two never talked. About 10 years ago, with the introduction of copper and low k, the foundries began to work with the packaging houses. 3D IC will be much more intensive. There will be a blending of the fab and the packaging house. And as we get into 3D standards and protocols, the blending of the two worlds will be necessary to pull this off.

SMD: How will the industry need to change to deal with this?
Woychik: I started my career at IBM, which was a fully integrated company. The industry disaggregated after that. 3D IC will drive re-integration, but it’s going to be in a new form.
Pateras: We’re viewing 3D very much as an extension of what we do in 2D. We’ve been combining IP from different vendors in 2D and putting them onto the same chip. With 3D, instead of putting this all on the same chip you’re putting it on separate die. What adds more complexity is whether you put memory on the same die vs. on a separate die, but from a test perspective it’s very similar. That’s not the same if you take two logic cores and combine them into the same design. You still need to test the same things using the same techniques—scan chains, isolation. But when you do that on two different die all bets are off because you may not have access to one of the die from an automation point of view.

SMD: But what do you do with two known good die that don’t work together right? Pateras: When it comes to memory on logic we can deal with the interface because we understand what memory interfaces look like, no matter who is creating the memory. But if you look at logic on logic, these interfaces are completely arbitrary. If you don’t have control of those interfaces, testing becomes much more difficult.

SMD: What changes in terms of responsibility?
DeLaCruz: Right now there’s a very big hole in the industry. We refer to individual die as tiles. The IP vendors are in the business of selling IP. They’re not in the business of supporting die sales or taking care of test or test methodology. People doing package devices now also are not set up for die sales. It’s a completely different business in terms of test, test infrastructure and yield management. On the other side are the wafer foundries. Will they step in and provide these tiles? It’s not their business. Nor is it for the assembly houses. There’s a gap right now, and that’s where we’re focusing our efforts. We plan to provide of menu of these tiles. By doing this, we’ll be able to provide a standard by default because we’ve done all of these devices by ourselves. It will make things fall into place and make sure that these devices will be interoperable. Even from a test standpoint, you’re going to have one common device with a certain amount of test compression, but you have to pin out the other devices to be able to accept that level of test compression from that first die. If you’re sourcing these die from multiple sources, the chances of them being set up right to make this work is almost non-existent. It’s like dropping a coin and expecting it to land on its side.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: So have we learned anything over the years from standards?
Radojcic: I do think we’re smarter than we were. It’s easier for tools guys to look at standards and subscribe to them than in the past. There isn’t as much ‘Mine is better than yours.’
Gianfagna: There’s a lot of work to create the standards. There’s a lot of work on the EDA side and there’s a lot of work on the process side. And then we talk about all that work being front-loaded. But the uptake is really slow. With 3D we talk about memory and processors and then go to something else. There’s a tremendous investment that has to be made over the next 18 months, and then we may not get it back for seven years.
Hogan: Xilinx has been shipping its prototype in limited production. What it always takes to get everything going is the killer app. Who would have thought about a full-finger touch-screen for your phone until Apple showed us we needed it. Now everyone has it and Apple is fighting with Samsung for displays. So what’s the killer app? I was not interested in touch displays. They have low margins and it’s a bad business. But suddenly touch displays are hot. What will it take for 3D to kick off?
Subramaniam: You don’t have to have a killer app. In the Xilinx case it’s pure economics. What they have done is create a tile structure for the FPGA. Rather than have a big FPGA die they have taken slices and hooked them together. The yield is inversely proportional to the area of the chip. If they went to a traditional FPGA model their yield would be extremely low. By going to a tile model they will have many more good tiles and their overall cost will be significantly better. Where you are talking about arrays or repeatable structures there will be benefits. In multicore designs, why build a 16-core chip? You can build four-core chips and put them together.
Hogan: I don’t disagree with that. But I do say it’s the system appetite that drives all of this stuff.
Wingard: That’s what makes Wide I/O so interesting. There is a system appetite in smart phones right now for a massive increase in acceptable bandwidth that we don’t know how to get to without doing this. That’s why so many people are aligning around Wide I/O.
Radojcic: Yes, and even though we doubted that phones would do this, we hurt in one area even more. Look at all the things you’re putting in a phone. It has to have a small footprint, so many gigabits per second of bandwidth and low power. It’s painful and 3D can help. Phones will probably be the killer app and most people are now saying it will happen in 2013.
Hogan: Video, too.
Wingard: Yes, video content with minimal power.
White: For mobile applications, does 2.5D suffice or do you really need to go to full 3D?
Radojcic: We are pursuing full 3D and so are most of the people in the phone business, primarily because of the form factor and cost. If you think about an interposer, you’re adding another die to the cost. Conceptually an interposer is an elegant solution and it works fine for someone who sells a product for $100. If you throw in a $1 interposer it’s no big deal. But if you’re making a $5 die and you throw in an interposer, it is a big deal

SMD: How about the thermal issues in 3D? Are they worse?
Radojcic: Thermal is an issue in 2D or 3D. It’s always an issue. 3D gives you some opportunities to help with the thermal. You can drive the power down. It can work as a heat spreader. It’s harder, but you can engineer it correctly. Do we have the infrastructure for dealing with thermal? Some of it. You can do thermal analysis. But can you take thermal information from a memory producer? No. You need to do a custom job to interface with the memory guy to see where he anticipates thermal issues. What we need are exchange formats. The tools are there. We need a methodology.
Gianfagna: There’s an analogy with timing-driven design. It used to be that you’d do timing analysis on the outer loop, then you’d do place and route and it would become part of the inner loop when you couldn’t get timing closure. The same thing is happening here. There are standalone tools that will do thermal analysis at the outer loop. That’s not going to work for a long period of time. You’ll need them in the inner loop as part of your iterative placement and partitioning. That’s not an unsolvable problem, but it is another hurdle across.
Wingard: And in a phone it’s mode-specific. The thermal patterns for an SoC are different, depending upon the use case. If someone uses their phone to watch a video it’s different than using it for a phone call.
Radojcic: And it’s different if you’re doing it in a hot car in Arizona.
Wingard: Some of this happens as a result of PoP. What used to be a package now becomes a heat source. With TSVs the granularity is finer, but if you’re looking at the hot spots on a chip that someone else gave you it’s going to be really difficult to work with.
White: You have to work with a transistor-by-transistor power model, and you use that to drive your decision-making.
Wingard: But it’s so use-case dependent.
Subramaniam: It’s not that bad. You’re not talking about different materials. It’s all silicon, so it’s easier to model. You can do the modeling and the analysis.
Wingard: And it’s more important to model.
Hogan: It will follow the arc. There will be details of transistors, then someone builds the lump model, and the lump model won’t give you enough degrees of freedom so someone will build a better model with more granularity—but not too detailed because you don’t want to slow it down in simulation.
Gianfagna: If you want to do this analysis, is it enough to do it structurally or even from a vector input point of view? You need to start running software scenarios. Bringing software into a hardware architectural design is interesting today, but it will be critical in the future.
Radojcic: This is all true and scary, but thermal is a good conductor. So do I need granularity for every transistor? Probably not. One transistor may not be quite as hot as its neighbor, but it will be pretty close. And do I need to run all these different use cases? Probably not all of them. You can say you’re going to burn most of your power here. Everything needs to be use-case and software-specific, but a lot of it we can do now. We can do thermal that’s plus or minus ‘x’ percent.

SMD: Does 3D change who makes money and where they make money?
Gianfagna: One of the Holy Grails for EDA is whether they can be a cost-enabler instead of a cost of doing business. And can they partner with customers to open new markets? Beyond that, who’s the general contractor? You’ve got a 3D stack that consists of multiple die that are known good quantities with a silicon interposer put together for an end customer. There are yield risks, assembly risks, inventory risks and design risks.
White: The foundry is also going to work very hard to get a cut of that.
Subramaniam: For us it’s just another piece of silicon and another way of packaging silicon. We don’t see it as any different from what we’re doing today.
Gianfagna: The supply chain is more complex.
Subramaniam: That’s true. And there are some issues with test. But by and large it’s very traditional.
Radojcic: It is different. Today you don’t go and buy memory and own the memory inventory.
Subramaniam: There are some differences, but they’re all manageable. We do multi-chip modules and PoP. We do all the different packaging technologies that are out there. This isn’t just a packaging solution, but it’s not all that different.
Hogan: Embedded in that is a question of where the value flows. The SoC guys still get the majority of the value. The question is who picks up value down below? Is it EDA or the enabler or the functional equivalent.
Gianfagna: The system guy gets most of it because that’s who defines the software and the delivery vehicle.
Hogan: So the rich get richer.
White: I don’t like that answer but it is the answer.
Hogan: Joe Costello described EDA as five dogs and one dog bowl. Below the system that’s what it’s going to be like. The value will flow differently, though. EDA will get some. I don’t think the foundries will get it all. [Value-chain producers] will get more.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: How important will standards be in 3D?
Radojcic: We definitely need standards. But before the world invents standards we have to have a pretty good image of what we’re doing. With Wide I/O memory that was easy. JEDEC was developing the standard so it was all good. If you open the door for logic on logic, it’s not going to be seamless. You really need to think about what kind of partitioning makes sense. You’re not going to want to split your clocks. We first need to do that as an industrial community.
Wingard: In the logic-on-logic space it’s going to be a closed shop model first. It’s going to be the same people designing the chip above and below.
Subramaniam: Yes, they will have control of the area and the design. The other place I see logic working is in re-use. A company could build the building blocks and then use those building blocks for different applications. Again, that will be a closed-shop approach.
Wingard: Then you need standards. Everytime you mention re-use you will need a standard.
Subramaniam: At least you will need an internal standard.
Wingard: One thing that’s different about the way we’ve done packaging before is that we had a layer of the package in between that had the same protocols and signaling levels even though our bond patterns didn’t match exactly. We relied on PCBs to make things match. With TSVs we don’t have that anymore. You have to agree on everything, from pad pitch to signaling all the way up that stack.
Radojcic: And it’s all interdependent. Figuring it out is a big problem.
Wingard: That’s what makes interposers so interesting. They’re the bridge for things like logic on logic. I think 2.5D logic on logic will happen well before 3D logic on logic for exactly these reasons.
Radojcic: For companies that can tolerate the form factor.
Wingard: Yes.

SMD: Isn’t one of the big issues focused on responsibility? You may have two perfectly good chips, but when they’re put together they don’t work properly.
Radojcic: There are things before that we need to figure out. We need information from the memory guys for stacking memory on logic so you can manage your hotspots and mechanical interaction. We need to agree how we exchange information between us and what that information includes. Then, when it comes to the building side, we need to create a supply chain business model for who owns what.
Hogan: This isn’t trivial. It’s a lot of work and we will solve it. But why bother? Let’s back out for a moment. The SoC is the way everyone delivers system value today. That’s dominated by the ARM processor. Everyone uses something that looks like an interconnect. On that interconnect people differentiate themselves with two things. One is a peripheral device. Texas Instruments is a great example of that. Someone else might add memories. The second thing is software. What 3D allows you to do is consider other things and other arrangements. We can spend a lot of time talking about the margins on SoCs, but they’re 50% or 60%. That’s why everyone does SoCs instead of discretes. There’s more value in the system. There will be a lot more integration of peripheral devices and software. That’s what’s exciting about this. It’s not to trivialize all the EDA work and the supply chain, because there’s a lot of work, but that’s what’s really interesting for me. This will allow more democratization of a design.
Gianfagna: You were talking about how the ecosystem would evolve. First it would be monolithic and internal by one company. Then you try to figure out how you do re-use, and then there will be third parties. That’s exactly how the existing 2D ecosystem evolved. That’s depressing. It says we didn’t really learn anything from 2D. You don’t think we’re any smarter?
Wingard: We’re starting with the standard interface stuff. Logic on memory is the early example. It’s not a closed shop today.
Subramaniam: It is a closed shop. Samsung owns the processor and the memory. They already do this Wide I/O design. They’re not going to wait for the standard. There will be a standard eventually, but they’re going to drive it.
Wingard: My guess is that’s not the volume driver. It’s a technology-proving vehicle. But independently, it will be standard interface first, then logic-on-logic in a closed environment, then we’ll figure out what else we can standardize on. To think that we’re going to get standardization ahead of where people know how to use it is very scary.
Gianfagna: So we’re stuck with standards driving the ecosystem and not the other way around?
Hogan: Anytime you have standards in place you lower the barrier to entry. That accelerates the ability of the ecosystem to grow. But there will be companies like Samsung that can’t wait, so they’re going to do their own version. And they have enough volume to do it. For the rest of the world they’ll have to wait for this chip-to-chip and logic-to-logic capability. But it will happen.
Subramaniam: On the logic-to-logic, I’m still not convinced a standard will evolve. The reason why a Wide I/O standard evolved was that you need a third party. Nobody is going to be designing their own memory. A third party is necessary. But with logic on logic, people may view it as a competitive advantage not to have a standard. There’s no reason, if I develop my own logic-on-logic, that it should hook up with a third-party logic design. I’m not agreeing with logic on logic becoming a standard.
Gianfagna: At one level that’s true. People don’t want to be homogenized.
Hogan: At CES Microsoft said it was going to use an ARM-based SoC with an Nvidia block. An Nvidia block? If you think about Xbox development they started out doing everything themselves, then they gave up and went to ARM. They’re not even doing their own graphics processor anymore.
Wingard: PoP (package-on-package) has been about memory on logic. One common version is baseband on application processor. Right now that business is done partly because some of the companies don’t have their own baseband assets. I would expect that to be logic-on-logic in the future. The more advanced basebands need more access to memory than they did before. There’s going to have to be some reasonable baseband connectivity in the future. Even if there aren’t any industry standards, with logic on logic if you want to get any re-use you’re at least going to need company standards.
Gianfagna: You guys are debating whether you integrate IP blocks on one die or two. You’re going to start with a certain number of building blocks. But if you have one at 22nm and one at 65nm, how do you connect them?
Wingard: I don’t think the model for a long time will be, ‘I’ve got this system to go build and I’m going to partition it across a set of dies the way I partition it across a set of FPGAs.
Gianfagna: Why?
Wingard: Because of legacy and because it’s too expensive. With legacy I’ve got something that’s been proven. But I’ve got something else I want to change, so this other die is the one with the new stuff on it. It’s that kind of re-use and how systems evolve and not having the assets because this thing comes from somebody else. All the logic doesn’t have to end up on one die.
Radojcic: There are many new constraints, both physical and architectural. The idea is that you take one die and slap it together with another die. But when you start thinking about it more and more it makes your head hurts. There are all these degrees of freedom that are interdependent.
Hogan: If I’m Cisco, I’ve got 35 million lines of legacy code I have to run in my router. How do I upgrade? It would be great to have an interposer because I can leave all that old code. Routers, servers and base stations are going to be loving this. The mil/aero guys are going to love this, too.
Subramaniam: If you have a 28nm chip, your upgrade could be done with an older chip geometry, and then you can use an interposer to slap the two together. Your equipment and design costs are going to be much lower with this approach.

SMD: There are two trends here. One is to build more and more on the SoC. The other is to set up all these separate processors. Does 3D move it all into one device and does it become more of a logical partitioning problem?
Gianfagna: Yes, but it’s going to happen slowly. You’ve taken what used to be on a printed circuit board and integrated it into a device. The more planes you add, the opportunities to mess up go up exponentially around thermal, stress, mechanical, heat dissipation, TSVs that don’t have anything to do with an interconnect. You can think about integrating multiple pieces of the system in the same package, but it’s going to take a while to get there.
Hogan: If you’re talking about integrating silicon, try getting TSMC to add two more mask layers or two more stops as the wafer travels around the fab. You need an enormous amount of volume because they like to minimize risk. Otherwise you’d need your own fab.
Subramaniam: If you put a TSV on a chip you’re effectively creating three or four layers on top of your 10 layers of metal. That’s going to happen sooner or later. The question is how many more layers will you get. There will be a limit.
Hogan: When we did studies on SiP (system in package), the yield is a linear function with the number of layers. Every time you add another layer it’s worse yield.
Subramaniam: But these layers are very coarse.
Hogan: I understand, but what should your yield be? How do you even test these things. The system is only functional when you have both die together.
Subramaniam: And you cannot use wirebond.
Gianfagna: You might also get a really fancy boundary scan and isolation logic.
Radojcic: We’re having a discussion the 3D industry already went through. The first discussion was, ‘This is really cool.’ The next discussion was, ‘How am I going to do this? How am I going to test this?’ The classic hype curve has been followed. There is a trough of disillusionment. But some of these things are already solved or solvable. It’s good to focus on, ‘We can do this. We can do memory on logic. So let’s focus on the work to be done.’ The work that’s left to be done is design exchange formats so you can model thermal or stress behavior from die A to die B, and you need feed power from tier two to tier one. We just need to get our act together and create standards.
Hogan: If you have standards in place you can get things done. If you have to integrate this stuff, no one lets the standards out and you have to fight for them—or you get competing standards.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SemiMD: 3D stacking means different things to different people. The type of 3D stacking talked about by companies such as IBM and Freescale is different from putting older generations of analog IP on top of new technology. What’s likely to really take off and when?
Gianfagna: The stock configurations will be first. What I’ve seen is processor on one layer, memory on another, and the sexy thing is ‘wide I/O, narrow I/O, silicon interposer.’ How do you really optimize memory and processor?
Radojcic: It is a memory and logic combination and there are two solutions. One is side by side with an interposer for guys that can tolerate a big footprint. There is wide I/O and logic. There also is the version without an interposer that some companies are pursuing. There is a consensus in the industry that all these types of technology have traction and will hit product with 3D.
Wingard: It’s important to look at why that’s so compelling. It boils down to the fact that in the last 30 years of computer architecture the processor speeds have been increasing while fundamental memory bandwidth has not. There is a chokepoint in the system where we have this large number of data requests being funneled through a single interface to external memory. Then you get onto the DRAMs themselves and they have a lot of bankable parallelism. We went to multi-bank DRAM a long time ago. What TSVs (through-silicon vias) in particular give us is a cheap way of greatly increasing the bandwidth between the logic chip and the memory. We can’t do it with bond wires. We have to do it with something where the cost of the connection becomes orders of magnitude cheaper. That’s what makes it compelling.
Radojcic: The value proposition is wide I/O. TSVs are the enabler.
Hogan: I’d back up even further. It’s always performance, power and cost or area. You get the opportunity for less latency. You don’t have a memory controller that’s chewing up a bunch of power. And you can integrate different process nodes to get the cost down. Xilinx is shipping a transposer rather than an interposer. They can drop four FPGAs onto that. It’s like a reference board on silicon.
Subramaniam: What we’ve been talking about with an interposer is 2.5D. It’s two pieces of silicon sitting on another substrate. It’s a packaging technology. There are several advantages to this. In a plastic substrate you are constrained by the design rules of plastic, which are hundreds of microns. If you go to silicon you are constrained by silicon design rules, which are tens of microns. What happens is that you are able to have significantly higher interconnect between chips, which you did not have in the past with plastic substrates. The reason you’re getting high bandwidth is because you’re about to have a 512-bit I/O instead of the standard 64-bit I/O. You can do that because you have the luxury of these smaller pitches on silicon. The second thing wide I/O does is improve power because you don’t have to have your typical DDR interface with an I/O buffer running at a higher voltage. With wide I/O you don’t need an I/O buffer, because with two pieces of silicon sitting so close to one another you can drive it with core voltage. That’s where you get the significant improvement in power.
Wingard: Actually, you don’t even have a PHY. There are no DLLs or PLLs.
Hogan: It’s a scheduler.
Subramaniam: So you can put in a baseband and an RF, or any other chips, and you can increase the speed at which these two chips can talk to one another. You can have more I/Os between the two of them and incorporate that. That’s the biggest advantage of silicon interposer technology. With 3D you’re going further. The devices will have active transistors in them and a TSV. But that will require significant changes in design methodology, CAD tools and design rules. The whole ecosystem needs to evolve significantly for that to happen.
Hogan: This is really what we used to refer to as hybrid technology. This idea has been around forever. We’re just introducing more technology with TSVs. It’s a 2.5D solution.

SemiMD: Is it really just packaging?
Radojcic: We spend a lot of time thinking about this. To call it packaging technology is misleading. You are going to use TSVs and TSS (through-silicon stacking) only if you are going to architect for it. You can’t just take two existing chips and slap them together. TSVs will cost more. The way you get the value out of it is by including it in the architecture. Wide I/O is an excellent example. You can do wide I/O only with TSS. You can’t do it with wires. It’s more than just packaging. It’s an integration technology.
Subramaniam: I agree. Things you can do in a multi-chip module today you can do with TSVs. But that doesn’t mean it’s the only thing you can do with TSVs.
Radojcic: But if you are trying to do multichip modules with TSVs you’re just creating a more expensive solution. You’re only going to do things with TSVs that you cannot do with multichip modules.

SemiMD: Are the design tools there?
White: The EDA industry, in general, is mindful that it needs to solve today’s problems at 28nm and 20nm outside of 3D ICs. At the same time, we also need to be investing in technologies to support 3D ICs. We need to balance our investments between both of those. Most of our efforts have 3D components. The Calibre division is working on solutions for 3D ICs and trying to judge the investment level versus the time when customers will need physical verification models. The EDA tools will come. They may not be out as quickly as some would want, but they will be available to the general market as they are needed. Our plan is to have physical verification tools in place this year.
Hogan: You’ve got to have that. And if you look at Sonics’ technology, the network on chip architecture gives you even more degrees of freedom to do high-level integration and go after performance. I think performance will drive everything.
Radojcic: The value proposition is either performance or power or form factor. But in terms of tools you have to step back and look at the application. If the first application is memory and logic you really don’t need many new tools. You need some standardization in terms of how you move design information from one tool to another. But you don’t need new tools because I’m designing one thing at a time. At some future date will be designing logic-to-logic integration, and then we will truly need new tools. People have been saying for 3D you will have to throw away all your tools. It’s not at all like that. I can design the kind of products people are talking about with a few tweaks. You may need new flows, but not new tools.
White: I agree with that. The approach we’re trying to take is to build upon the existing tools and extend them to deal with the interfaces in a more seamless way to deal with the memory and the logic underneath. You’re currently using scripts to try and deal with those interfaces. We want to connect up the memory physically and electrically with the logic underneath. Over time that will evolve to something more sophisticated where you have logic on logic so you have finer granularity.
Gianfagna: That is the good news. You don’t need to swap out the whole design perspective. A lot of our tools can be extended in a rather straightforward way to 3D design. It’s not trivial, but it is an extension of the existing methodology. It’s not tool retraining. But down the road as you start looking at thermal and mechanical stress, that’s different. You’re looking at placing TSVs that have nothing to do with connectivity. They have to do with heat dissipation. That’s weird, and it gets more difficult as we proceed. But you don’t have to bite it off all at once.
Radojcic: You don’t need new tools in the RTL to GDS II flow. But you do need new tools for exploring the value proposition. We can’t rely on past experience that came from 2D scaling to define a winning vision in 3D. We call that pathfinding. Somewhere at the tail end we will need methodologies and tools to manage the interaction of die for thermal. How do you incorporate that into corners or stress?
Hogan: I think the opportunity is at the architectural level. If I have a wide memory, it gives me more options in terms of implementation. And because we have more degrees of freedom, it gives us more options at the software level.
Subramaniam: You can’t trivialize the tools. You will need significant enhancements in terms of extraction and planning analysis—especially if you are going to do logic on logic. How do you figure out the partitioning, and then how do you model the interconnect between block A and block B? That whole area needs to be studied. And with TSVs in your ASIC you’re going to have islands and blockages that you will have to work around. This will need a lot of R&D.
Wingard: Another problem is how we’re going to share known good die between companies, which is something we’ve been trying to do for years and years. How do people deal with these very thin wafers? For me the big risk is in that area. The second big risk is in the architectural area. When we try to think about partitioning systems, where we have standard interfaces I’m not worried. It’s all the places where we don’t have standard interfaces. Will we have to come up with a new class of standard interfaces or will the way we partition a system across multiple FPGAs be one in which we don’t worry about the I/O because it’s just the I/O? Is that the model we’re going to use? I really don’t think so. How many people can afford to build four logic die and four mask sets instead of one? We’re going to need some standard interfaces.
Radojcic: I agree. You need the architecture first. Then you can worry about physical problems.

Semiconductor Manufacturing & Design examines the myth and reality of 3D stacking–and the hurdles that still need to be solved. In the hot seat: VC Jim Hogan; eSilicon’s Prasad Subramanian; Sonics’ Drew Wingard; Atrenta’s Mike Gianfagna, and Mentor Graphics’ Michael White.