Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘ESD’

Mentor Graphics U2U Meeting April 26 in Santa Clara

Monday, April 11th, 2016

thumbnail

Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.

Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high.  What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.

He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.

After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth?  What types of designs will be staffed and funded? Is it IoT?  Wearables?  Automotive?  Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.

Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.

These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.

A few of the highlights:

  • Oracle’s use of advanced fill techniques for improving manufacturing yield
  • How Xilinx built a custom ESD verification methodology on the Calibre platform
  • Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
  • Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
  • Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
  • Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
  • A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
  • How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
  • Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements

Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.

The day winds up with a closing session and networking reception from 5:00-6:00pm.

Registration is from 8:00-9:00am in the morning.

Blog review October 27, 2014

Monday, October 27th, 2014

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

Phil Garrou blogs that most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers. NANIUM also has extensive volume manufacturing experience in WB multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

Gabe Moretti says it is always a pleasure to talk to Dr. Lucio Lanza and I took the opportunity of being in Silicon Valley to interview Lucio since he has just been awarded the 2014 Phil Kaufman award. Dr. Lanza poses this challenge: “The capability of EDA tools will grow in relation to design complexity so that cost of design will remain constant relative to the number of transistors on a die.”

Are we at an inflection point with silicon scaling and homogeneous ICs? Bill Martin, President and VP of Engineering, E-System Design thinks so. I lays out the case for considering Moore’s Law 2.0 where 3D integration becomes the key to continued scaling.

Congratulations to Applied Materials Executive Chairman Mike Splinter on receiving the Silicon Valley Education Foundation’s (SVEF) Pioneer Business Leader Award for driving change in business and education philanthropy by using his passion and influence to make a positive impact on people’s lives.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. As Adele Hars reports, speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM.

IP interoperability in SoCs: Mix and match doesn’t always work

Wednesday, March 26th, 2014

By Matt Hogan, product marketing manager for Calibre Design Solutions at Mentor Graphics.

Design re-spins, shorter time to market schedules, and the continued productivity pressures on engineers within the integrated circuit (IC) design community have all contributed to the widespread re-use of intellectual property (IP), which is seen as a quick way to incorporate proven technology in a new design. The thing is, more often than not, a design re-spin isn’t just a simple re-spin with a tweak here and a tweak there. The new design will probably have to comply with modified specifications that inevitably raise the bar for performance and power usage, and it will probably contain new IP that must be integrated. At the same time, the design team will be told to leverage as much of the silicon-proven IP already in production as possible. The verification from the previous design must be re-done, using as many automated tools and processes as possible to minimize timelines. With multiple power domains, complex power management schemes, and high signal counts, reliability concerns for today’s low power designs are at the forefront of priorities.

In 2011, the ESD Association published a technical report on ESD Electronic Design Automation Checks (ESD TR18.0-01-11) that outlined a number of recommended reliability checks. Not content to stop there, they continued work on a revised version of this report (publication forthcoming). Contained within this report are a number of recommended cell-level electrostatic discharge (ESD) checks. Rule 6.1.1 is titled, “Verify that Correct Version of the Device/Design Kit/Cell/Library is being used when using Standard Library Cells or Parameterized Cells (PCELLs)”. The focus of this check from the ESD community is to ensure that the cell has been “screened” to ensure it is acceptable for use within the design.

While the ESD focus for checking cell names is valid, there are broader reasons to validate the interoperability of cells being used together within the same design. Most of these focus on controlling and understanding the isolation of power and signals within the design. Imagine, if you will, a SERDES buffer contained in one cell, while supporting circuitry is contained in other cells. If an optimization is made to the SERDES buffer that also requires tweaks to the circuitry in the other cells, we now have a situation where the versions of all of these cells are now interdependent. How do we capture this interdependence in the design? More importantly, how do we control the situation so that other designers using these cells use the correct versions?

Figure 1. Re-spins of production designs may implement new cell versions that affect interoperability.

Figure 1 shows a case where five blocks were used successfully in a previous design. The version numbers of these blocks are proven to be compatible with each other. However, since the production of that design, the libraries containing these cells have been revised, and newer versions of these cells are now available. Unfortunately, simply accepting the latest versions from the design library may not yield optimum results. The new design on the right uses the latest versions of these cells, but who has validated that these new versions are compatible with each other, and with the older versions of the unchanged cells?

Internal design rule manuals provide a central location to store a vast array of different design rules. It would not be too much of a leap to include version numbers of cells and interoperability information. Alas, updating the design rule manual is a manual process, subject to the usual human error and forgetfulness. In addition, even if provided, the information could be easily overlooked, particularly for designs with large numbers of IPs and a significant number of dependent cells. Should you accept the latest version of a cell? Some very desirable optimizations may be implemented with new cell versions, but so, too, may be a dependence on a library cell of which you’re completely unaware.

Design flows, IP library conventions, even project requirements, all point to the need for a flexible solution. IP interoperability is an important but often overlooked aspect of SoC design that can be validated early and often in the design and chip assembly stages of the design. Many CAD groups write their own scripts to try to validate these conditions, but development and maintenance of custom code is time-consuming and costly. An automated method that can evaluate the cells in a design (including version numbers) in conjunction with any interoperability rules that may exist and report conflicts back to the user would seem an obvious choice. Tools such as Calibre® PERC™ are giving designers the power to quickly and effectively validate this reliability aspect of their designs early in the design flow. Final verification of cross-domain issues and other reliability issues can be found with final sign-off decks.

Early identification of potential interoperability issues in your designs helps keep your projects on track in a repeatable and controlled manner. Being aware of the issues is the first step. Adding automated interoperability verification to your design flow to uncover dependencies and resolve interoperability conflicts helps you keep designs on schedule while ensuring the designs take advantage of optimizations that can improve design performance and reliability.

Author:

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.