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Posts Tagged ‘emulation’

Mentor Graphics Veloce Emulation Platform Used by Starblaze for Verification of SSD Enterprise Storage Design

Wednesday, September 21st, 2016

Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Veloce® emulation platform was successfully used by Starblaze Technology for a specialized high-speed, enterprise-based Solid State Drive (SSD) storage design.

Starblaze performed a detailed and lengthy analysis of the available solutions in the emulation market.  The Veloce emulation platform was selected and deployed because of its superior virtualization technology and memory protocol support, rich software debug capabilities and proven track record delivering innovative emulation technology.

“The enterprise SSD market is evolving rapidly, so the SoC (System on a Chip) verification technology we use has to be perfectly aligned with our needs, especially in terms of flexibility and high-performance protocol support,” said Sky Shen, CEO of Starblaze Technology. “After using the Veloce emulation platform on our latest high-performance, enterprise SSD controller project, we are convinced that a virtual solution with extensive software debug capability is the trend for the future of emulation technology.”

In the SSD storage space, it is extremely important for design teams to study the architecture and tune the performance while finding deep hardware bugs in the pre-silicon stage. Starblaze used VirtuaLAB PCIe to provide the host connection to their design on the Veloce emulation platform. The VirtuaLAB PCIe delivers very high debug productivity, and Starblaze was able to use its Software Design Kit “as is” without any modification or adaption.  In addition to using Veloce VirtuaLAB, Starblaze used Mentor’s Codelink® software debug capability to support the requirements of their embedded core software debug. In the flash interface side, the Veloce platform provides both HW and SW sparse memory solutions, which permits the necessary tradeoffs in the storage application.

ICE and Virtual:  Complementary Technologies

With the Veloce Emulation platform, verification teams have access to the best of both worlds, whether using an ICE-based or virtual emulation environment.  In-circuit emulation (ICE), a foundational emulation use model, remains a ‘must have’ for SoC designs that need to connect to real devices or custom hosts where physical hardware is required. The Veloce iSolve™ library offers a full complement of hardware components to build a robust ICE-based flow.

As more verification teams move from an ICE-based flow to a virtual flow, the Veloce emulation platform provides a smooth transition.  The Veloce Deterministic ICE App complements ICE by eliminating the non-deterministic nature of ICE and enabling advanced verification techniques: debug, power analysis, coverage closure, and software debug.

Full virtualization is achieved with the Veloce VirtuaLAB environment, which delivers virtual ICE-equivalent, high-speed host protocols and memory devices, allowing for greater flexibility for hardware/software system-level debug, power analysis, and system performance analysis.

“The Veloce emulation platform continues to deliver a comprehensive and robust emulation platform to a broad set of markets that all have unique challenges,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “With Starblaze’s expertise in Flash Controller and SoC design, they quickly recognized the benefits of our VirtuaLAB solution.  Our success in working with them is attributed to our in-depth knowledge of the power of a virtual solution, and our timely support in deploying the Veloce emulation platform to meet their specific needs.”

About the Veloce Emulation platform

The Veloce emulation platform uses innovative software, running on powerful, qualified hardware and an extensible operating system, to target design risks faster than hardware-centric strategies. Now considered among the most versatile and powerful of verification tools, emulation greatly expands the ability of project teams to do hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization.

The Veloce emulation platform is a core technology in the Mentor® Enterprise Verification Platform™ (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform. The Mentor EVP combines Questa® advanced verification solutions, the Veloce emulation platform, and the Visualizer™ debug environment into a globally accessible, high-performance datacenter resource. The Mentor EVP features global resource management that supports project teams around the world, maximizing both user productivity and total verification return on investment.

Veloce2 Emulator

Veloce2 Emulator is a high capacity, high-speed, multi-application powerhouse for simulation and emulation of SoC designs Learn More

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of approximately $1.18 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. http://www.mentor.com.

Mentor Graphics Veloce VirtuaLAB Adds Next-Generation Protocols for Leading-edge Networking Designs

Monday, October 19th, 2015

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Mentor Graphics Corp. today announced the Veloce® VirtuaLAB Ethernet environment with support for  25G, 50G and 100G Ethernet. This support enables highly efficient, emulation-based verification for the massive Ethernet-based designs being created today.

The huge surge in demand for connectivity has had a profound effect on the size of switch and router designs, making them among the largest IC designs developed today. The sheer size of the designs, the pressure for early release, and the need to verify all paths are creating a methodology shift that moves verification from simulation- to emulation-based flows.

“Providing a highly scalable, high-density network foundation for our customers’ demanding environments is a top priority as we design Juniper Networks’ advanced switches and routers,” said Debashis Basu, senior vice president of Silicon and Systems Engineering at Juniper Networks. “The cutting-edge features in our ASICs make Veloce VirtuaLAB Ethernet and emulation capabilities a key component for achieving verification convergence, helping ensure that we deliver versatile, high-performance switching and routing technology to keep pace with evolving network requirements.”

VirtuaLAB Ethernet transforms emulation for networking chips by replacing the traditional physical devices used in In-circuit Emulation (ICE) with virtual devices. This virtualization moves emulation from the engineering lab to the computing data center for maximum emulation resource utilization. “It’s a solution to Ethernet lab virtualization. That’s a very big pain point for our networking customers. We’re addressing it very efficiently with the VirtualLAB Ethernet,” said Jean-Marie Brunet, Marketing Director for the Emulation Division at Mentor Graphics Corp.

VirtuaLAB components provide a complete software-driven Ethernet stack that runs at up to 15,000 times the speed of traditional simulation. This lets VirtuaLab Ethernet users tackle the complex challenges of Ethernet-based designs with improved throughput, advanced debug, power analysis and performance analysis.

VirtuaLAB is part of Veloce emulation solutions.

“The rapid development and deployment of high-end Ethernet products for the networking market requires access to high quality IP and complete verification solutions,” said Daniel Kohler, CTO of MoreThanIP. “We have collaborated with Mentor over several years to enable the deployment of robust, fully featured Ethernet verification encapsulated in the Ethernet VirtuaLAB product. Most recently we have collaborated to enable forward error correction (FEC) verification for high-speed 25G, 50G, 100G designs.”

According to the 2015 Ethernet Roadmap developed by the Ethernet Alliance Organization, Ethernet could have 12 speeds before 2020 with 6 new speeds introduced in the next 5 years. The progression of speeds is not in chronological order because 40G and 100G were primarily based on multiple lanes of 10Gb/s technology that was available before 25Gb/s serial technology enabled 25G. Lanes running at 25Gb/s are becoming impractical in 2015 and will be used in 25G SFP+ and 4x25Gb/s 100G QSFP28. The next serial lane is expected to be 50 Gb/s and enable 50G SFP28, 200G QSFP28 (4x50G) and 400G CFP2 (8x50G).

“It’s starting to be a little bit all over the place,” said Brunet. “That’s the reason why we had to expand our portfolio and support different protocols of Ethernet speed.”

Ethernet protocols are evolving in a non-chronological way, driven by the different needs of various applications, such as cloud computing, video and even IoT and automotive. Source Data: EthernetAlliance.Org

The need for bandwidth is driven in different ways by data centers, cloud computing, metro area networks, storage area networks, social networking and video applications. “Video (for example) is driving the need for high bandwidth, fast computation (or the exchange of packets of information),” said Brunet.

The accelerated deployment of VirtuaLab solutions in the networking market is the result of significant and repeatable improvements in throughput. For example, in simulation it’s not uncommon to run 1,000 packets of data per day. When compared to emulation, the difference is staggering. Here customers report they are running 11,000,000 packets of data per day.

“We collaborate with leading-edge networking companies to provide solutions that address their verification challenges. The rapid growth of these designs and the need to verify every path creates a huge verification space resulting in a major shift from simulation to emulation,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “We developed VirtuaLAB Ethernet and other solutions that transform emulation, enabling our Veloce customers to meet their complex verification goals.”

The Veloce emulation platform is a core technology in the Mentor® Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform. The Veloce emulation platform’s success is a result of several factors: high design capacity, speed of execution, and exceptional functionality. Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation, and performance characterization.

Breaking Down Power Management Verification

Monday, June 22nd, 2015

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By Vijay Chobisa, Mentor Graphics Corporation

For system-level power management verification, it is important to understand how software applications running on the targeted SoC effect power use.  During system-level verification, it is imperative to verify that the software power control applications properly initialize power states and power domains. In addition, that signals are stable during the transition from one application to another or between tests and level shifters, and that isolation cells are inserted correctly.

Companies that design complex SoCs implement several power domains in their designs to meet power budgets while maintaining the required operating performance. Several low power management techniques are employed including isolation cells, level shifters, state retention cells, power aware memories, and power control logic. As some memories are power aware, memory behavior must also be validated at the system level. The power control logic resides in hardware and the actual controls come from software, making verification too complex and lengthy for traditional digital simulators.

An advanced emulation platform supports complete power management verification at the system level, where software and hardware operate together where real-world stimulus is applied to the design under test. The speed of emulation allows designers and verification teams to boot the operating system and quickly stress test the design over an extremely large number of power sequences.

Power management verification flows

A power management structure allows designers to divide designs into several power domains. Each domain can be operated with a unique voltage level and can be powered on and off without interfering with the functionality of other domains. This requires isolation between power ON domains and power OFF domains. When an OFF domain needs to wake up, it requires some basic information to return to ON correctly.  Designers use retention techniques to preserve this information while the domain is switched off. The more information retained, the more real estate consumed; but the domain wakes up faster. Designers must be aware that states in the power OFF domain that lack a retention infrastructure can go to unknown values. Level shifters are used to operate domains at different voltages.

Memories can switch to three different states: power ON (allows normal memory operations), power OFF (memory operations are disabled and memory contents are corrupted), and standby (memory operations are disabled but memory contents are kept intact).

In this system, the always ON block implements the isolation interfaces and schemes. Features of the UPF standard are used to accomplish this functionality: an always ON supply and an ON/OFF supply. The Veloce operating system (OS3) supports the UPF supply functions — supply_off/supply_on — to natively handle this behavior.

Together, the four stages described below create a scalable, progressive flow that allows users to begin system-level low power verification early in the design and verification flow, using high-level models, adding detail and accuracy as the design matures. The stage used depends on how far along the design and its corresponding UPF description is in overall development. Each stage has specific goals and actions that build toward full verification of the final netlist.

Stage 1: Verifying UPF accuracy and implementation

Semiconductor companies want to start low power verification as early as possible to shorten production schedules. To make this happen, it is critical that the UPF file accurately captures the design intent as the design blocks are coming together at an early stage (Figure 1).

Figure 1. UPF file accurately captures the design intent.

At this stage, the design is in RTL, and the entire power intent is defined using top level UPF file. Typically it is carried over from a previous design and must be modified to suit the new one. The RTL is still in an early stage of development. There are no Liberty files and no gate-level components at this stage. The testbench is also in an early stage of development. Appropriately, verification takes place at a high level of abstraction, where speed is more important than accuracy.

First, engineers verify that the UPF file is correct, and then verify that the DUT and UPF file are working together—that the syntax matches. After that has been validated, the emulator reads the design RTL plus the UPF file, generates the power hierarchy along with the design netlist, and maps everything to emulation primitives. This step is used to verify the structure from the top level point of view to make sure that the emulator takes this UPF file and creates the proper power infrastructure in the DUT; including power switches, connectivity, and isolation cells. If anything is not implemented correctly or is missing in the UPF file, it is corrected both in the UPF file and the backend implementation.

Stage 2: Adding multiple blocks and corresponding block-level UPF files

In this stage, the design has several RTL blocks — each having its own UPF file. As in Stage 1, there are no gate-level netlists or Liberty files at this point.

The chip is verified with the top-level (power intent) UPF file and the UPF files for each block, which are usually supplied by the IP/block developers. Because each block-level UPF file has been implemented, they are more accurate at representing the power control inside each block. The top-level UPF file verified in Stage 1 is used at this stage, so the block-level and top-level UPF files are used together to thoroughly verify the whole design (Figure 2).

Figure 2. The chip is verified with the top-level (power intent) UPF file and the UPF files for each block.

The verification runs are similar to those in Stage 1. The main difference is that the power control is more detailed and the main goal is to make sure that the internal block controls are working correctly in the whole chip environment. Because each power pin control is more complicated in this context, compared to Stage 1, a finer level of resolution is required to control different sequences and cover all the corner cases. It is essential to test the handshaking between these blocks in the system context, because although these blocks and their respective UPF files have been verified in isolation, it is important to verify that they interact correctly with other blocks at the system level.

Designs often have many power sequences coming from different voltage regulators, and these can be powered on and off at any time. Further, there is not a single source that is controlling all of this activity. These are the real- world behaviors, which engineers want to mimic in emulation. The emulator generates random power sequences that can randomly power the different blocks on and off, which mimics the random nature of real-world scenarios.

Stage 3: Mix of RTL and gate-level netlist

In stage 3, some components of the design are fully ready and are available as a gate-level netlist. For RTL blocks, power intent comes from a UPF file, and for gate level block power infrastructure, is part of the netlist. This requires support of a liberty file. These gate level block or IP could be reused from previous SoC (Figure 3).

Figure 3. Designers test functionality in the hardware/software context.

At this point in the design cycle, the software is maturing and the CPU is used to control power down and power up functionality. So designers need to test this functionality in the hardware/software context.

The emulator must be capable of reading UPF files and liberty files to enable this mix of RTL and gate level netlist verification.  This is very critical at this stage.

As before, the accuracy of the UPF file matching the real chip is the primary goal. Toward that end, the emulator needs to provide power structure visual checking and the ability to report any mismatches. Again, only emulation can provide the required runtime performance to handle these complex operations on a very large chip, especially with gate level components.

Stage 4: Verifying gate-level netlists

In this stage, the power management infrastructure is part of the gate-level netlist and includes the final power hierarchy and reads the power strategy from Liberty files. This enables the final SoC netlist to be verified before chip tape out, ensuring that the final netlist has accurate low power behavior and avoiding translation issues from one design stage to another. Veloce identifies the power hierarchy and provides a debug flow in the event of incorrect or expected behavior (Figure 4).

Figure 4. Final SoC netlist is verified before chip tape out.

Advance low power debug console

Power aware bugs can be hard to debug thus a comprehensive GUI to debug power aware issues is needed. The Visualizer Debug Environment from Mentor offers a comprehensive power aware debug environments to enable debugging power aware issues, connectivity and sequences in an intuitive way.

Some examples:

  • PA domains
  • PA crossings capturing various aspects of isolation/level shifter being missed/incorrect
  • PA SimChecks
  • Power hierarchy schematic

Conclusion

Companies start power aware verification at a very early stage in the design flow and add details and granularities as the design progresses. The successive refinement at each stage allows customers to break down a complex problem into smaller, targeted verification jobs and establish a feedback loop to and from the backend team.

The Veloce Emulation platform from Mentor allows users to approach power management verification at the system level, where both software and hardware operate together with real-world stimulus applied to the design under test. The speed of emulation lets designers and verification teams boot the operating system and run application stress tests on the design through a very large number of power sequences extremely quickly. The Veloce Emulation platform is fully aligned with the Questa® simulator from Mentor, enabling customers to use the same UPF files and UPF constructs for both simulation and emulation.

The emulation team at Mentor has worked with customers to create a system-level power management verification methodology that achieves thorough verification of the interactions between software and hardware and confirms that system resources are powered appropriately in each functional mode. This makes the Veloce Emulation Platform a logical choice for power management verification for companies who see advantages in using standards and avoiding non-standard methodologies. The Veloce Emulation Platform complies with the IEEE 1801 Unified Power Format (UPF 2.0 and 2.1) standards; including comprehensive constructs support and debug capabilities.