By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.

To download this white paper, click here.

By Mark LaPedus

Extreme ultraviolet (EUV) lithography is late for the 10nm node and could possibly miss the window for that insertion point, according to a lithographer at a panel discussion at last week’s SPIE/BACUS Photomask Technology conference in Monterey, Calif.

The IC industry has various EDA, lithographic, photomask and other solutions in place If EUV remains delayed, but the challenges will continue to mount in the multi-patterning era, according to panelists at the event. The panel was entitled “Will optical patterning solutions be ready if EUV lithography continues to be delayed?”

During the panel and the SPIE/BACAS event in general, there were rumblings that EUV is delayed — again. Analysts believe that EUV may be too late for the 14nm node, but now there are growing fears that the technology is in danger of missing the 10nm window.

“It’s clear that EUV will be late for our 10nm node,” said Allen Gabor, senior patterning program manager in advanced lithography at IBM, during the panel.

In a brief interview after the panel, Gabor said IBM has not totally dismissed or counted out using EUV for the 10nm node. “If it is ready, we will use it,” he said, without elaborating.

During the panel, he presented a slide of what appeared to be IBM’s lithography roadmap. At 10nm, EUV and 193nm immersion are still in the mix. Other leading-edge chipmakers, including GlobalFoundries, Intel, Micron, TSMC, Samsung, SK Hynix, Toshiba and others, have not publically indicated that EUV will be late for 14nm or 10nm.

The sole EUV tool supplier, ASML Holding, is expected to ship its NXE:3300B, a full-blown, 13.5nm EUV production tool, later this year. In January, ASML promised an acceptable throughput of 69 wafers an hour for the tool.

Amid ongoing delays for the EUV light source from Cymer, ASML in July lowered its targets and promised a throughput in the “30ish” range in terms of wafers per hour this year. It’s possible that ASML may not deliver 70 wafers per hour for the machine until 2014, according to C.J. Muse, an analyst with Barclays Capital, in a recent research note.

Intel’s recent decision to invest as much as $4.1 billion in ASML has raised overall confidence levels in EUV lithography. TSMC and Samsung have also invested in the Dutch-based lithography giant. ASML has said it needs to reach 250 Watts of average source power to achieve the 125 wph throughputs sought by its early customers—roughly 10x today’s situation.

The IC industry hopes that EUV will be ready at 14nm. But if EUV misses 14nm, and is inserted at 10nm, it still could be an expensive solution. Since EUV has a wavelength of 13.5nm, EUV will require some form of a double-patterning scheme at 10nm, IBM’s Gabor said.

In any case, leading-edge chipmakers may be forced to extend 193nm immersion much further than previously expected. Chip makers will also utilize a double-patterning scheme, such as sidewall image transfer or self-aligned double patterning, litho-etch-litho-etch (LELE), or self-aligned vias, he said.

“Without EUV, scaling beyond the 10nm node will require frequency multiplication,” he said. In that scenario, vendors may have to resort to self-aligned quadruple pattering or directed self-assembly (DSA), he said.

Impact on mask makers

The shift towards the multi-patterning era has some major ramifications for the EDA, photomask and other industries. EDA houses, for example, are readying their multi-patterning tools. But verification costs and optical proximity correction (OPC) run times are expected to soar at the 10nm and 7nm nodes.

“The total run times scales in accordance with the number of patterning steps,” said Yuri Granik, chief scientist within the Design to Silicon Division at Mentor Graphics. “Double patterning alone and SRAFs will increase OPC run times.”

There’s good and bad news for photomask makers and associated tool vendors. In traditional single exposure processing, an IC maker uses one mask. In doubling patterning, an IC maker uses two separate masks to design a device, which boosts production costs. Triple-pattering will require three masks and so on.

In double patterning (two separate mask sets), photomask makers could write the layers in sequential steps with one e-beam tool. In a more likely scenario, a mask maker would simultaneously utilize two e-beams to process each mask to speed up the process.

In multiple patterning, mask makers could see their capital costs soar, as they may end up buying twice as many e-beam tools than before. On a positive note, e-beam makers are seeing robust demand, said Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks.

The trouble is that e-beams are not keeping up with Moore’s Law.  From 2001 to 2005, write times were constant, averaging some 8 hours per mask set, Kalk said. But from 2007 to 2012, the average write times rose to about 10 hours per mask set, he said. “The write times will increase dramatically over the decade,” he said during the panel.

Aki Fujimura, chairman and chief executive of D2S, also painted a sobering picture. E-beam throughputs are increasing by a factor of only one-half, but data volumes are increasing by a factor of two, and mask complexity is jumping by 2x to 5x, he said during the panel.

This week, D2S rolled out one solution to the problem. It introduced TrueMask MDP, a model‐based mask data preparation (MB‐MDP) technology. Developed to address mask designs at 20nm and beyond, TrueMask MDP reduces e-beam shot count to cut mask write times by 20% to 30%.

Still, there is a crying need for multi-beam mask writers to boost write times. One vendor, Austria-based IMS, has been developing a so-called electron multibeam Mask Exposure Tool (eMET) for the fabrication of leading-edge masks and templates. The company has completed a concept 50keV eMET. Through a programmable aperture plate, the eMET would provide 264,144 programmable beams with 20nm and 10nm beam sizes.

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has joined IMS’ multibeam mask writer development collaboration. Earlier this year, IMS said Dai Nippon Printing Co. Ltd. (DNP) joined a collaborative effort, backed by Intel and Photronics, to advance IMS’s electron multibeam mask writer tool.

Advantest and Vistec are also developing similar multi-beam tools. It’s unlikely that the multi-beam tools will be ready at 10nm. “They should be ready for 7nm,” Toppan’s Kalk said.

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: Are the tools that are available today sufficient to deal with the challenges at hand in terms of manufacturing and packaging?
Geronimi: It’s time to move from a custom solution to an engineered solution.
Aitken: If you look at double patterning, there’s a routing challenge, especially on metal-one. You go through so much effort on standard cell design and you design something that’s decomposable using the various coloring rules that there’s no way you’re going to let the router touch it. Routers don’t understand enough about design rules to be allowed anywhere near it. That is an inherent inefficiency. You lose a fair amount of density by not letting routers onto metal-one. There are similar tool gaps for what metal corners look like. There’s another one in terms of electromigration and IR drop. There are a lot of tool gaps and designers are working around them, but the inefficiencies are there. Better tools could help eliminate some of those inefficiencies.
Capodieci: With respect to multiple levels of patterning, although we’re doing a lot of joint work there I haven’t seen a robust solution being deployed. We need to attack the problem of multi-patterning to realize that problem will be solved by solving another problem—from decomposing things into manufacturable blocks. For directed self assembly or direct-write, some other form of non-patterning approach will be used. Multiple patterning is a useful exercise. I don’t think it’s going to lead us toward an industrial solution because triple and quadruple exposures and all the processes associated with that have technical and financial problems.

SMD: The design industry looks at what can be created, while the manufacturing side looks at it from the standpoint of whether it can be produced with reasonable yield. As business considerations begin creeping into both sides, how does that affect this relationship and the decisions being made?
Liebmann: There’s an increasing reluctance, at least from the tooling side, to bite off more than is digestible. We’ve talked about construct-based design. That extends into construct-based routing. I haven’t found any takers for a router that can deal with 100 legal configurations and nothing else. That’s a very long and expensive development project that the EDA industry won’t take. So we’ve had good luck making improvements to the existing design base. But to really make revolutionary changes on the design side is just as hard as making evolutionary changes on the manufacturing side.
Geronimi: There are things we need to consider now. If we don’t get the tools to work we will have much more difficulty later on.
Liebmann: A lot of this comes back to the lack of a clear roadmap. The ITRS roadmap has become something of a useless document at this point because it extrapolates to zero without taking into account these very disruptive things that are happening, such as double patterning, maybe the switch to EUV, and the introduction of self-assembly. Without a clear road map it’s difficult to ask the EDA industry to invest in a six-year project to develop a new routing technology.
White: It is challenging, with finite resources, to invest a huge chunk in a product development team that can go off and do something that will take multiple years to create a solution. What you find within the industry is that it’s easier or more straightforward to improve on the infrastructure that we know and extend it. That’s the general strategy you’ve seen from all of us.
Lin: Right now most of the burden of double patterning is on the foundry and EDA. I would like to encourage the fabless design houses to look at the different options, not just to rely on EDA and the foundries.
Aitken: What we found with double patterning is that there are two kinds of foundries in the world. There are those that want to see colors and separation in the layout and those that do not. We find it’s actually harder to do the ones that don’t separate because what we do is add the colors, to prove that it can be separated, and then we erase the colors and hope they can find the same decomposition that we did. I’m not convinced that’s the optimal way to do something. Decomposition is a major challenge. Double patterning is at least solvable in normal terms. Triple patterning will require heuristics.
Liebmann: Sometimes marketing gets in the way. There is a fear of inconveniencing the customer, which in this case is the fabless design house. There is no way around it. If you do double patterning, the designers have to get engaged and understand the fundamental problem. This whole idea of coloring is just one way where you need to convince the customer there is a problem, but once they understand that I think it’s a very solvable problem.
White: As we work with customers doing these kinds of designs we are seeing a convergence. Industry-wide, there’s a growing tolerance of coloring. In many instances it’s important information that otherwise is being lost.
Capodieci: We cannot be color-blind. We must see in color.

SMD: Who’s responsible as things go wrong with a more complicated design?
Capodieci: The collaborative model that many of us have been putting in place even at 28nm, where there is very limited usage of double patterning, will be the only way forward. Part of the color awareness is that. It’s not just exchanging operational information about the coloring. It’s also understanding what the corner cases are with the IP and with the routing. Rather than taking the responsibility for blame, we all have a shared responsibility for success. That also means we have a shared responsibility for failure.
Lin: It helps that we have more pieces internally and are working with our external customers. Our early learnings will help us to work with customers earlier.
Capodieci: The golden rule is, ‘When in doubt, blame the vendor.’ If you are an IDM, you blame whoever is external. If you are in a more complex ecosystem, whoever is holding the vendor badge that day gets the blame. Triple patterning brings to the surface a very complex interaction. There are EDA, the foundry, the design customers, and a very stratified group of IP vendors. So maybe there is not a single solution.
Aitken: It’s a very important question. When you look at it historically, we’ve evolved a number of different handoff points. The DRC deck is a classic one. It’s either legal or it’s not. If it fails and it was legal, it’s the foundry’s problem. If it fails and it was illegal, it’s your problem as a layout person. There’s growing recognition that’s not adequate. We want it to be DRC-legal, but we also want sufficient yields, so we check and make sure the things we think are DRC-legal will yield even if the DRC says they will. That level of collaboration will be necessary going forward. The business arrangements haven’t quite figured out how to track it yet, but they’re going to have to. The ‘blame the vendor’ approach is one way to do it, but if it’s your part that isn’t shipping then you’re the one getting fired and that doesn’t matter. So it’s everyone’s responsibility.
Capodieci: That’s exactly right, and that’s why we need to talk about shared responsibility. Regarding the example about DRC and additional yield assurances, many problems today make DFM verification decks mandatory. You must achieve a certain score. There is an open pass/fail, based on the fact that you’d like to have an 85% score on your recommended rules. How you achieve that score depends on which geometries you want to push and which ones you want to relax. This can be seen as an additional level of complexity, but it’s also an additional level of freedom. You can play around with your physical design and still get to tapeout.
Lin: You have to define a very thick interface and define things very clearly. Within the same company you can resolve the problem over lunch. Here you need a very clear explanation.
Geronimi: Unfortunately with double patterning, if you cannot get to signoff you cannot manufacture it.
Aitken: I disagree. When you have some very complicated structure you can sign off and say it passes, and you have no real assurances that it works. That’s where the challenge is.
Geronomi: From a double patterning standpoint, when you look at whether you can decompose it or not, you go to manufacturing with colors expecting the rules to work correctly. At least with single patterning you know that even with very complex rules, you can manufacture the design.
Liebmann: That, to a large extent, is why double patterning is in better shape than DFM. DFM is very vague. Who owns it? Is it really required? Is it optional? With double patterning, it comes down to a double patterning-enhanced rule set. You either pass DRC or not. It’s very clear.
Aitken: but there are some challenges there, too. If you create decomposition and send it to a fab, suppose they recolor it and it fails. Who’s problem is it?
Capodieci: That’s why we have been expanding the safety net of DFM to include additional checks for double patterning. We had to add scores for double patterning. Plus, we are finding that a lot of patterns are derived from decomposition. DFM will have an enhanced role to catch everything to catch the holes left by double patterning. At the end of the day, double patterning needs to come together to create a single mask for future processing. That’s the key. It’s easy to break. The question is, when you put it back together will it yield?

By Mark LaPedus

H.S. Phillip Wong, professor of electrical engineering at Stanford University and one of the leading experts on directed self-assembly (DSA) technology, sat down to discuss the future of this approach with Semiconductor Manufacturing & Design. With funding from the Semiconductor Research Corp. (SRC), Stanford is exploring contact-hole patterning and the design infrastructure using DSA. The research is also funded by the National Science Foundation (NSF).

SMD: What is DSA and how does it work?
Wong: Let me take a simple but appropriate analogy. If you have a cup of water and drop some oil in it, the oil will form droplets by itself. It’s self-assembled that way. The physical driving force for self-assembly is that the surface forces for the oil and water are different. They have different surface tensions. So therefore, they separate out by themselves.
Another example is if you had a tray of marbles. When you tilt the tray, the marbles will fall down. If you shake it a little bit, they will closely pack into a hexagonal type of arrangement. If they end up in the wrong place, they can get out of the wrong place and find a lower energy state. DSA is the same thing. Block copolymers have a natural driving force for them to come together or separate because of surface energy. We provide some shaking, or high-temperature annealing at 100 degrees C or 180 degrees C, to allow polymers to find their low energy spot. These different blocks have different surface energies that drive them to be what we call phase separated.

SMD: The DSA flow is rather simple, but is it an expensive process?
Wong: It’s not that expensive from a tool or materials point of view. This is what a DSA process is like. Basically, you pattern a template using conventional lithography. You mix the co-polymer in a solvent. You spin coat them. And then you heat them a little bit to allow the solvent to move or go away, while at the same time providing some energy for the polymer to find its lowest energy position. That’s when the self-assembly occurs.

SMD: What are the physical limits for DSA and what is the insertion point for IC production?
Wong: DSA enables people to build devices at smaller features sizes and tighter pitches. It continues density scaling. The industry has a way to see it at 14nm or further. Material science people have shown 6nm half-pitch. But academics are very poor predictors of technology insertion points. So I am not going to make any predictions about that.

SMD: What is the status of DSA in the IC industry right now?
Wong: I think we’re in the pre-development stage. Companies are looking at whether to put a development effort in it. But a lot of interesting things are happening in both academic research as well as in various companies. Companies, including the device manufacturers, materials suppliers, resist companies and the tool vendors, are keeping an eye on it. We won’t know the real status until we get to the point where people actually put in a development effort to do it. That’s when the hot problems come up.

SMD: Has anyone made a commitment to go into production?
Wong: I am not aware of it right now. Like I said, it’s in the pre-development stage. When you say commitment, that means companies are putting in a development effort. I don’t think that’s happening yet. I think it will eventually happen.

SMD: Is DSA a next-generation lithography (NGL) technology that will replace current litho tools?
Wong: This is more of a complementary technology than a dislocating technology. I don’t think it will replace anything. Just like when double patterning came along, it didn’t replace anything. DSA allows you to go further with tools you already have. I view this as analogous to the arrival of double patterning. It’s a technology that allows you to extend your tools a little bit longer.

SMD: Can you use DSA with EUV?
Wong: We have EUV-based printed guiding templates. The templates are kind of small; they are 60nm or so. To me, EUV is just a way to print the guiding templates. DSA doesn’t replace EUV. You can’t junk litho tools in DSA. You still need them.

SMD: What will DSA enable in IC production?
Wong: Different people are looking at different things. I am working on the contact holes. For lines, you may have other options like double patterning. For holes, you don’t have other options. They are becoming harder to print. The pitch is too small. In optical lithography, sometimes you have two holes and a little bridge that bridges the two. That becomes a defect. DSA is going to help with the pitch problem. DSA can also heal some of the printing defects, because the polymers are kind of soft and malleable. For example, you have a printing defect, say two holes merged together. After DSA, your two holes will become separated. The stuff in the bridge area will be filled in with DSA material. They heal the defects that way.

SMD: What are the major challenges to put DSA in IC production?
Wong: Defectivity and design. Defectivity requirements are very high. For example, in the SPIE paper that Chris Bencher (of Applied Materials) gave a couple of months ago, he showed that defectivity was about one in maybe several million or tens of millions for contact holes. But there are billions of contact holes in a chip. So right now, we are several orders of magnitude off. I don’t think it’s an insurmountable problem, because when most things were introduced in the beginning, defects were high. We just have to learn how to get the defects out of there.

SMD: What have you demonstrated in R&D?
Wong: In the experimental work we have done, we’re using a kind of block copolymer that give us holes of the order of 15nm or 20nm in size, with a pitch of anywhere from 20nm to 40nm full-pitch. We’re not really focusing on pushing the sizes and pitches. We’re focusing on understanding the design requirements. All of these things have to be transparent to the circuit designers.

SMD: You have talked about a DSA design environment using an alphabet soup of characters. How does that work?
Wong: You have these DSA patterns, which are guided by guiding templates. The guiding templates are printed by conventional lithography. From the circuit designer point of view, all they care about is where the contact holes are eventually. So, for example, you would have a guiding template that surrounds a group of contact holes. (A given template would denote) an L-shape, T-shape, a pair or a triplet. So, this is the DSA alphabet I’m referring to. In other words, you would look at a design and say: ‘This design is composed of a pair, triplet, L-shape, T-shape or whatever.’ You basically classify your layout into these groups just like having 26 letters of the alphabet.

SMD: How many letters do you envision in a DSA design environment?
Wong: This is an interesting research question. How big is the alphabet set? Do you need 26 letters of the alphabet or will five be adequate? Maybe two. Maybe 100. We are only looking at a handful right now. We’ve used it to compose SRAM cells and various random logic circuits in standard cell libraries. We’ve demonstrated a standard cell library and shrunk it down to 22nm.

SMD: Will this force designers to use restrictive design rules?
Wong: You probably would them—not very restrictive design rules, but somewhat restricted. People are used to that these days.

SMD: What’s the next milestone?
Wong: To look at more of the letters of the alphabet and see how many more are required. Of course, the smaller number the better. Otherwise, you will have a tough time characterizing them. Try and learn a language with 100 letters of the alphabet. It’s hard to do.

SMD: How do you make this into commercial EDA tools?
Wong: Eventually, various pieces of the industry will come together. Even if they don’t come together, they will have their own way of doing the DSA alphabets. And then, you will have Synopsys telling their customers: ‘We have a better alphabet than Cadence. So come use our tools. Cadence will do the same thing.’

SMD: Are the EDA companies behind the curve in DSA?
Wong: I don’t know what’s going on behind closed doors. Right now, I think they realize this could be a business opportunity. This could also spawn some new EDA companies, which eventually may get acquired by the bigger ones.

By Mark LaPedus, SemiMD senior editor

Chip design and process technology costs continue to escalate at an alarming rate for each node.

The combined cost for a new chip design and a “mask set” at the 32nm node is nearly $90 million, more than three times the price tag at 65nm, according to Gartner Inc. Process R&D costs range from $600 million to $900 million for the 45nm and 32nm nodes, up from $310 million to $400 million for the 90nm and 65nm nodes, according to GlobalFoundries Inc., a silicon foundry vendor.

These costs are expected to soar at the 20nm and beyond. Amid the cost trends, there is also pressure among chip makers to develop more robust designs — and ensure they can be manufactured in a timely fashion. To meet these challenges, IC vendors have recently embraced — and put more emphasis — on a key enabler: design-for-manufacturing (DFM).

As part of the DFM equation, chips yields — and the yield enhancement process — have become even more critical. “The yield ramp has been an issue forever,” said Luigi Capodieci, director of DFM/CAD and R&D Fellow at GlobalFoundries. “It has become even more dramatic now. Chip design costs are so expensive. So, you need your chip to yield immediately or you are not going to recoup your investment.”

Seeking to stay ahead of the curve, GlobalFoundries and others have taken various steps to address the issue. For example, at the Design, Automation & Test in Europe (DATE) conference in Dresden, Germany on March 12, GlobalFoundries and Mentor Graphics Corp. are expected to announce a major DFM alliance. Mentor and GlobalFoundries will also present a joint seminar on yield optimization at DATE on March 14.

As part of the DFM and yield enhancement partnership, Mentor’s Consulting Division (MCD) has developed a new flow for GlobalFoundries and its customers, which has demonstrated the ability to improve incoming design yields. MCD is a standalone unit that provides customized EDA solutions and consulting services.

Available for GlobalFoundries’ customers at the 45/40nm and 32/28nm process nodes, the new flow addresses a key part of the systematic yield process. The flow makes use of Mentor’s EDA tools to automatically perform metal widening, via doubling, and via enclosure, including support for rectangular vias, according to the companies.

The flow features rapid turnaround time for chip designs and helps “improve layouts,” said Jim Jordan, manager of worldwide yield enhancement services within MCD. The flow also ensures that the results are DRC clean by immediately verifying all of the changes during the modification process, Jordan said.

With the flow, GlobalFoundries has seen a 20 percent to 90 percent — and even 100 percent — improvement in overall “systematic yields,” Capodieci said. “It also improves the reliability of a chip,” he said. “We also like that the flow is highly modular and scalable, which allows us to easily move it to new processes and to extend it to address additional DFM issues as we uncover new design-based yield limiters.”

He was quick to point out that the new flow does not affect overall chip yields, but it is limited to the systematic yields in a physical design. Overall yields also depend on “how good your design is,” he said. There are other factors that can impact yields, such as random defects, tiny particles and manufacturing glitches in the fab production process.

The tools involved in the new flow include Mentor’s EDA yield enhancement lines, such as the Calibre nmDRC, Calibre YieldAnalyzer, and Calibre YieldEnhancer. Results were validated with Mentor test and yield analysis tools, including Tessent TestKompress, Tessent Diagnosis and Tessent YieldInsight.

Beyond the 32/28nm node, GlobalFoundries is also developing its 20nm and 14nm processes. The company is expected to move into risk production for the 20nm node in the second half of 2012, followed by volume production in 2013.

GlobalFoundries plans to extend its yield enhancement efforts with Mentor and other EDA houses to 20nm, Capodieci said. At that node, GlobalFoundries and its EDA partners are working on adding “double-patterning-aware” technologies to the yield enhancement mix, he said.

With the ongoing delays of extreme ultraviolet (EUV) lithography, leading-edge chip makers face the dreaded double-pattering era at 20nm and beyond. “It’s becoming more complicated at every node,” said Jean-Marie Brunet, director of product marketing for model-based DFM and place and route integration at Mentor Graphics. The industry must “look at double patterning, triple patterning and quadruple patterning. The costs for these solutions are very high.”

Other leading-edge foundries, including Samsung, TSMC and UMC, are also racing each other to develop 20nm technology — all based on a planar process. Intel is already in 20nm production — built around a new finFET transistor technology. The leading-edge silicon foundries want to put finFET transistors into production at the 14nm node.

The shift towards multi-pattering, finFETs and other technologies will require more DFM, resolution enhancement techniques (RETS) and other technologies, said Mentor’s Jordan. “The challenges are getting more complicated,” he added.

For its fiscal fourth quarter ended Jan. 31, 2012, Mentor Graphics Corp. reported revenues of $320.4 million, compared to $307.3 million in the like period a year ago.

The EDA house reported a net of $57.3 million, or $0.52 per share, during the quarter, compared to a net of $50.6 million, or $0.45 per share, a year ago.

For the full fiscal year, revenues were $1.014 billion, compared to $914.8 million last year. For the full fiscal year, profits were $83.4 million, or $0.74 a share, compared to $28.6 million, or $0.26 per share, a year ago.

“It was a quarter and a year of records for the company, including the significant milestone of crossing one billion dollars in revenues,” said Walden Rhines, chairman and CEO of Mentor Graphics. “Additionally, the growing complexity of chips and the challenges of the 28nm and 20nm process nodes have generated substantial demand for both our functional verification and our design-to-silicon products.”

For the full fiscal year 2013, the company expects revenues of about $1.1 billion, non-GAAP earnings per share of about $1.32, and GAAP earnings per share of approximately $1.13. For the first quarter of fiscal 2013, the company expects revenues of about $255 million, non-GAAP earnings per share of about $0.25, and GAAP earnings per share of approximately $0.19.

The company’s board has increased the share repurchase authorization to $200 million from the original $150 million. During fiscal year 2012 the company repurchased 6.8 million shares for $90 million at an average cost of $13.22 per share. Under this increased authorization, $110 million is available for share repurchase over the next two years.

By Mark LaPedus, SemiMD senior editor

Two EDA and IP standards organizations — Accellera and the Open SystemC Initiative (OSCI) — have merged in an effort to accelerate the development of system-level standards in the IC industry.

The move was expected. In June, Accellera and OSCI signed a memorandum of understanding to form a single organization. Now, the boards of the two groups have approved the merger.

The combined organization is called the Accellera Systems Initiative. The new organization leverages the complementary efforts of both Accellera and OSCI. Known for SystemC technology, OSCI develops standards for system-level modeling, design and verification.

Accellera is best known for developing standards around design and verification languages, with extensions into IP. Last year, Accellera moved into the IP deployment and reuse standards world with the merger of The Spirit Consortium.

The merged organization — Accellera Systems Initiative — will enable and accelerate comprehensive system-level, semiconductor and IP design standards in the industry, said Stan Krolikoski, secretary for the group.
By combining the two organizations, the idea is to “get the standards out faster,” Krolikoski told SemiMD. “The notion of working in silos is no longer business as usual.”

Krolikoski was previously the secretary for Accellera and the treasurer for OSCI. He is currently the group director of standards for Cadence Design Systems Inc.

The increasing challenges of creating complex system-on-chips (SoCs) has brought the need for a single organization like Accellera Systems Initiative to create new IP and EDA standards, he added. The focus of Accellera Systems Initiative will continue to be on the standards activities that are under development by both Accelera and OSCI in three areas: systems-level verification, mixed-signal design and verification; and systems-level IP integration.

In systems-level verification, for example, there is some synergy between the TLM-2.0 SystemC Transaction Level Modeling standard from OSCI and Universal Verification Methodology (UVM) from Accellera. Under the Accellera Systems Initiative umbrella, the two standard bodies will “extend their work together,” Krolikoski said.

The same idea will also take place for mixed-signal design and verification, where the group has Verilog-AMS from Accellera and SystemC AMS from OSCI. It will also take place for systems-level IP, where the group has IP-XACT from Accellera and SystemC from OSCI.

“Our new organization is chartered to address the growing and complex needs of the semiconductor and electronics industries by developing electronic design standards that allow them to create and manufacture products quickly in our rapidly changing market place,” said Shishpal Rawat, Accellera Systems Initiative chair. “With our newly combined organization, we can efficiently accelerate the development of system-level and IP standards across multiple design environments, to increase electronic design productivity and lower the cost of designing ICs and embedded systems.”

Mentor Graphics Corp. reported revenues of $250.5 million in its fiscal third quarter ended Oct. 31, compared to $238.9 million in the like period a year ago.

Mentor reported a net of $24.1 million, or $0.22 a share, in the period, compared to $15.3 million, or $0.14 a share, a year ago.

Walden Rhines, chairman and CEO of Mentor Graphics, attributed the growth to the push towards 28nm and 20nm designs, which require EDA tools for reticle enhancement techniques (RETs). Automotive and embedded design tool sales were also strong in the quarter, he said during a conference call.

“Bookings were again a record, up over 20 percent from the previous third quarter record, and for the second consecutive year our book-to-bill through the third quarter is positive,” he said. ”This quarter saw the beginning of the strength we predicted in our Design to Silicon category for the second half, with bookings in the third quarter up year-on-year by over 55 percent, and by about 15 percent year to date.”

Going forward, Mentor is bucking the trend. “We see no weakening” despite the current IC or economic slowdown, he said.

Gregory Hinckley, president of Mentor Graphics, said: “Leading indicators for the business continued to be strong, with third quarter support declines down and consulting and training bookings doubling. Annual fees for renewing contracts in the top ten transactions were up 40 percent over their prior annual fees. Base business, contracts below $1 million in value that booked and billed in the quarter, grew 15 percent over last year.”

For the fourth quarter, the company expects revenues of about $316 million, non-GAAP earnings per share of approximately $0.50, and GAAP earnings per share of $0.46.

For the full fiscal year, ending Jan. 31, 2012, the company expects revenues of $1.01 billion, non-GAAP earnings per share of $1.05, and GAAP earnings per share of $0.69.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: How good is the information exchange across the supply chain these days?
Capodieci: We need to push a lot of design information onto the manufacturing floor. This is a huge area. The EDA industry really needs to wake up and create a new set of flows. This is one of the most advanced industries in the world. We fabricate sophisticated devices without actually knowing what we’re fabricating. We ask for less-than-optimal information about where the critical issues are. New flows and new interfaces can be added to the manufacturing floor, respecting the IP and the proprietary nature of the design. But the information can be passed on to the manufacturing floor so it can be monitored and acted upon.

SMD: We’re not just creating hardware anymore. How does software affect yield, and is it even considered part of yield?
Michaels: If you look at the fabless sector, they’re hiring multiple software engineers per design engineer. It’s where a great deal of effort is going. But for our purposes, once you get past test and packaging and yield we tend to view it as the fabless problem. It’s not our market.
Mason: At TI we’re investing enormous resources in software and compilers that our customers use. It’s something we have to deliver to the ecosystem to use our products. We’re not using software to fix a yield problem. We’re typically not coupling the software with the fab yield problem right now. It’s more of a design enablement activity.

SMD: Will that change?
Mason: There’s more and more integration across the entire design space, and that includes software. Software is a critical part of what we do on the product side.
Capodieci: In the foundry space, we are still very active in doing esoteric R&D with universities. This is a little futuristic, but we have seen interesting research out of UCSD (University of California San Diego) on dark silicon, which is the silicon that does not get activated. We make it fully functional, but it is hardly used because of power issues. So there are software techniques and architectural techniques that go into making the best use and creating opportunistic cores. This is beyond our traditional field, but in the future we need to keep an eye on how the architectures will evolve with a focus on what needs to yield with a certain variability level and what needs to yield with a different variability level. This is an approach I call managed variability. Not all of the physical components react equally to the process. We need to be able to distribute this, but we need to know which components we’re building. This will be beyond 20nm.
Ramaswami: Most of our investments in software have been in three areas. One, of course, is process design. When you have very deep vias, you have diffusion of materials from the very top to the very bottom. A lot of the modeling has to be done in terms of concentration of gradients as well as mechanical agitation. The second area is around chamber control. When you have a multichip system, how do you measure the parameters? The feedback to the system becomes critical. An example is CMP, where you look to measure in real time the thickness of the materials and you control the polish rate. These get very critical with 10nm or 15nm films at the gate level. The third area is for inspection, where inspection and analysis are becoming a big deal at the wafer and at the mask level.

SMD: What happens with stacking of die and we have to drill holes in the silicon? Where are we now and where will be in a couple years?
Ramaswami: Most of these vias are made in the via-middle process, which is basically a blind via and done right after contact. You have the contact formation to do the blind via, you etch it, line it, and it’s all done. Or you assume it’s done, because you have no way of really knowing. Of course we can do some X-ray analysis at the full wafer level, but we only get ghost images of gray and white. It’s like looking at an ultrasound. You have to be a trained radiologist to figure out what it is. You’re sending the wafer on and putting faith in the rest of the logic line, which may be 10 or 20 layers, each one going through a heat cycle. You’re just hoping the via is in good shape at the very end, and you really don’t know until you do backside testing. In terms of mechanical yield and cross sections, we believe today that filling the via is not an issue as far as structural analysis is concerned. How well it is done electrically, with heat cycles, we just don’t know because data is limited. And often a different side of the fab—the packaging side—finds the data. That feedback loop takes a long time.
Capodieci: In terms of 3D, we’re a little bit behind—particularly with extraction. The problem becomes bigger, of course. But the process side is ahead of the curve. Still, it’s something that needs to be brought to fruition if we are going to bring 3D architectures to market.
Michaels: From the foundry standpoint you can’t completely test at the single-chip or wafer level. That will require the foundries to use more equipment data, more characterization, to find a probability to finding out how close they are to being in the center of the process. You may not be able to test exactly but you can clearly determine when should you scrap, etc. These new techniques of leveraging more data out of the fab than traditional metrology will become more important.
Smayling: In stacking, one of the opportunities for yield improvement stems from the fact that fab inspection traditionally has been on a surface. We’re going to have to think about how to inspect these stacked structures. It’s something we don’t have technology for today, but it’s going to be needed to drive these activities. For EDA, whether they’re stacked or not they’re going to be designed piece by piece. One of the biggest problems for EDA is that each of the pieces is done potentially at a different technology node. Now you’ve got a PDK that works with one version of verification software, a different PDK that works with a different version of verification software. And so when you stack these things together there’s no consistent environment for even doing verification. There is a big opportunity for verification to take on these kinds of issues.
Mason: There are lots of challenges with 3D. TI is right in the middle of those kinds of technologies because that’s the way the industry is heading. One issue that’s important in all of this is DFM. There are all kinds of mechanical stresses in this process, and these mechanical stresses have electrical implications. Where these TSVs are on the wafer relative to transistors and whether those are timing-critical circuits that are impacted by mechanical stresses has to be considered. There is research in this area now. We haven’t worried about these DFM issues in the past, but we will have to.

SMD: What kinds of mechanical stresses?
Mason: Where you physically change the silicon and that has an electrical effect. If you take a chip and macroscopically bend it, that affects the speed of transistors because of the electrical impact of that strain. When you’re doing that locally, you can change the timing of that circuit and break the circuit. That can happen because you’re putting a through-silicon via there that you didn’t simulate.

SMD: Stacking in 2.5D seems much more straightforward compared to full 3D stacking. Which one will come out first and why?
Ramaswami: I think 2.5D is much simpler. But we see the end market today driven by mobile devices, which requires a DRAM stack on top of a logic chip. That clearly does not lend itself to 2.5D or interposer technology. So we need to get that working, no matter what. The questions we’re getting now on 2.5D is how to make the interposer more active rather than just having a piece of silicon with lines through it. Putting more capacitors and inductors on them is an area we’re beginning to pursue with a couple of universities.