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Big sell: IP Trends and Strategies

Monday, March 10th, 2014

By Sara Ver-Bruggen, SemiMD Editor

Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.

SemiMD: How are existing SIP strategies adapting for the transition to 20 nm generation of system- on-chips (SoCs)?

Roddy: The move to 22/16 nm process nodes has accelerated the trend towards the adoption of commercial Interface and physical IP. The massive learning curve in dealing with new transistor structures (FinFET, fully depleted SOI, high-k) raised the price of building in-house physical IP for internal consumption, thus compelling yet another wave of larger semiconductor IDMs and fabless semi vendors to leverage external IP for a greater share of their overall portfolio of physical IP needs.

Pierce: With 20 nm processes, the number of SIP cores and the size of memory accessed by those cores is seeing double digit growth. This growth translates into tremendous complexity that requires a solution for abstracting away the sheer volume of data generated by chip designs. The 20 nm processes will drive the need for SoC subsystems that abstract away the detailed interaction of step-by-step processing. For example, raising the abstraction of a video stream up to the level of a video subsystem; the collection of the various pieces of video processing into a single unit.
In this scenario, the big challenge becomes integration of subsystem units to create the final SoC. Meeting this challenge places a premium value on SIP that facilitates the efficient management of memory bandwidth to feed the growing number of SoC subsystems in the designs. Furthermore, 20 nm SoC designs will also place higher value on SIP that helps manage and control power in the context of applications running across these subsystems.

Smith: We are seeing many of the larger systems companies bypassing 20 nm entirely and moving from 28nm process technologies to the upcoming generation of 16 nm/14 nm FinFET technologies. FinFET offers the benefits of much lower power at equivalent performance or much higher performance at similar power to existing technologies. While 20 nm offers some gains, there are compelling competitive reasons to move quickly beyond 28/20 nm.
The demand for FinFET processes will naturally push the demand for the critical SIP blocks needed to support SoC designs at this node. SIP providers will need to migrate SIP blocks to the new technology and, for the most critical, will need to prove them out in silicon. The foundries will need to encourage this activity as SIP will typically make up more than 60-70% of the designs that will be slated for the new FinFET processes.

SemiMD: Within the semiconductor intellectual property (SIP) SoC subsystems market, which subsystem categories are likely to see most growth and how is the market evolving in the near term?

Pierce: Internet of Things (IoT) is causing an explosion in the number of sensors per device that are collecting huge amounts of data to be used locally or in the cloud. However, many of these sensors will need to operate at very low power levels, off of tiny batteries or scavenged energy. Sensor subsystems will need to carefully integrate the required processing and memory resources without support from the host processor. Some of the most interesting and challenging sensor subsystems will be imaging-related, where the processing loads can be highly dynamic, but the power requirements can be particularly challenging. Additionally, MEMS subsystems will grow in importance because this technology will often be used for power harvesting in IoT endpoint devices.

Smith: High-speed interfaces will see the most growth. DDR is at the top with DDR typically being the highest performance interface in the system and also the most critical. The DDR interface is at the heart of system operation and, if it does not operate reliably, the system won’t function. Other high-speed interfaces especially for video will also see tremendous growth, particularly in the mobile area.

Roddy: The emergence of a ‘subsystems’ IP market is to date over-hyped. That’s not to say that customers of IP are content with the status quo of 2008 where many IP blocks were purchased in isolation from a multitude of vendors. Customers do want a large portfolio of IP blocks that they can quickly stitch together, with known interoperability, provided with useful and usable verification IP. For that reason, we’ve seen a consolidation in the semiconductor IP business within the past five years, accelerating even further in 2012 and 2013. Larger providers such as Cadence can deliver a broad portfolio of IP while ensuring consistency, common support infrastructure, consistent best-in-class verification, and lowered transaction costs. But what customers don’t want is a pre-baked black-box that locks down system design issues that are best answered by the SOC designer in the context of the specific chip architecture. For that reason we expect to see slow growth in the class of ready-made, fully-integrated subsystems where the cost of development for the IP vendor far outweighs the added value delivered.

SemiMD: How will third party SIP outsourcing models become more important as the industry embarks 20 nm generation SoCs and what are IP vendors doing to enable the industry’s transition to the 20 nm generation of SoCs?

Roddy: As the costs of physical IP development scale up with the increasing costs of advance process node design, more consumers of IP are increasing the percentage of IP they outsource. Buyers of IP will always analyze the make versus buy equation by weighing several factors, including the degree of differentiation that a particular piece of IP can bring to their chips. Fully commoditized IP is easy to decide to outsource. Highly proprietary IP stays in house. But the lines are never black and white – there are always shades of grey. The IP vendors that can provide rapid means to customize pre-existing IP blocks are the vendors that will capture those incrementally outsourced blocks. The Cadence IP Factory concept of using automation to assemble and configure IP cores is one way that IP vendors can offer a blend of off-the-shelf cost savings with an appropriate touch of value added differentiation.

Pierce: From a business perspective, SIP outsourcing is inevitable for all functions that are not proprietary to the end system or SoC. It will not be feasible to develop and maintain all the expertise necessary to design and build a 20 nm device. The demand to abstract up to a subsystem solution will drive a consolidation of SIP suppliers under a common method of integration, for example a platform-based approach built around on-chip networks. Platform integration will be a key requirement for SIP suppliers.

Smith: SIP vendors are looking to the foundries and/or large systems companies to become partners in the development of the critical IP blocks needed to support the move to FinFET.

SemiMD: Are there examples of the ‘perfect’ SIP strategy in the industry, in terms of leveraging internal and third party SIP?

Smith: Yes. Even the largest semiconductor companies go outside for certain SIP blocks. It is virtually impossible for any individual company to have the resources (both human and capital) to develop and support the wide variety of SIP needed in today’s most complex SoC designs.

Pierce: The perfect SIP strategy in the industry is one that readily enables use of any SIP in any chip at any time. Pliability of architecture over a broad range of applications is a winning strategy. Agile integration of SIP cores and subsystems will become a critical strategic advantage. No one company exemplifies perfect SIP strategy today, but the rewards will be great for those companies that get closest to perfection first.

Roddy: There is no one-size-fits-all IP strategy that is perfect for all SOC design teams. The teams have to carefully consider their unique business proposition before embarking on an IP procurement strategy. For example, the tier 1 market leader in a given segment is striving to define and exploit new markets. That Tier 1 vendor will need to push new standards; add new value-add software features; and innovate in hardware, software and business models. For the Tier 1, building key value-add IP in-house, or partnering with an IP vendor that can rapidly customize standards-based IP is the way to go. On the other end of the spectrum, the ‘fast follower’ company looking to exploit a rapidly expanding market will be best served by outsourcing as close to 100% as possible of the needed IP. For this type of company, speed is of the essence and critical is the need to partner with IP vendors with the broadest possible portfolio to get a chip done fast and done right.

SemiMD: What challenges and also what opportunities is China’s growing SIP subsystems market presenting for the semiconductor industry?

Roddy: China is one of the most dynamic markets today for semiconductor IP. The overall Chinese semiconductor market is growing rapidly and a growing number of Chinese system OEMs are increasing investment levels, including taking on SOC design challenges previously left to the semiconductor vendors. By partnering with the key foundries to enable a portfolio of IP in specific process technology nodes for mutual customers, the leading IP providers such as Cadence are setting the buffet table at which the Chinese SOC design teams will fill their plates with interoperable, compatible, tested and verified physical IP blocks that will ensure fast time to market success.

Pierce: China is a fast growing market for SIP solutions in general. It is also a market that highly values the time-to-market benefit that SIP delivers as the majority of China’s products are consumer-oriented with short design cycles. SIP subsystems will be the most palatable for consumption by the China market. However, because China has adopted a number of regional standards, there will be substantial pressure on subsystem providers to optimize for local standards.

Smith: We see tremendous opportunities in terms of new business for SIP from both established companies and many entrepreneurial startups. Challenges include pricing pressure and the concern over IP leakage or copying. While this has become less of an issue over the years, it is still a concern. The good news is that the market in China is very aggressive and willing to take risks to get ahead.

Safety critical devices drive fast adoption of advanced DFT

Monday, January 6th, 2014

By Ron Press, Mentor Graphics Corp

Devices used in safety critical applications need be known to work and have the ability to be regularly verified. Therefore, a very high-quality test is important, as is a method to perform a built-in self-test. Recently, there has been a strong growth in the automotive market and the number of processors within each car is steadily increasing. These devices are used for more and more functions such as braking systems, engine control, heads-up display, navigation systems, image sensors, and more. As a result, we see many companies designing devices for the automotive market or trying to enter the automotive market.

2011 saw the publication of the ISO standard 26262, which specifies standard criteria for automobile electronics. Our experience is that recently two test requirements are being adopted or at least evaluated by most companies developing safety critical devices. One requirement is to perform a very high-quality test such that there are virtually no defective parts that escape the tests. The other is to perform a built-in self-test such that the part can be tested when in the safety critical application.

There are various pattern types that help support the zero DPM (defects per million) shipped devices goal. In particular, Cell-Aware test is proven to uniquely detect defects that escape traditional tests. Cell-Aware test can find defects that would escape a 100% stuck-at, transition, and timing-aware test set.. This is because it works by first modeling the actual defects that can occur in the physical layout of standard cells. Cell-Aware pattern size was recently improved and reduced, but a complete pattern set is larger than a traditional pattern set so embedded compression is used.

At Mentor Graphics, we started seeing more and more customers implementing logic BIST and embedded compression for the same circuits. Therefore, it made sense to integrate both into common logic that can be shared, since both technologies interface to scan chains in a similar manner. The embedded compression decompressor could be configured into a linear feedback shift register (LFSR) to produce pseudo-random patterns for logic BIST. Both the logic BIST and embedded compression logic provide data to scan chains through a phase shifter so that logic is fully shared. The scan chain outputs are compacted together in embedded compression. This logic is mostly shared with logic BIST to reduce the number of scan chain outputs that enter a signature calculator.

The hybrid embedded compression/logic BIST circuit is useful for meeting the safety-critical device quality and self-test requirements. In addition, since logic is shared the controller is 20-30% smaller than implementing embedded compression and logic BIST separately. As previously mentioned, we have seen this logic being adopted or in evaluation very broadly by automotive device designers.

One side effect of using embedded compression and logic BIST is that each makes the other better. For example, embedded compression can supply an extremely high quality production test. So, fewer test points are necessary in logic BIST to make random pattern resistant logic more testable, which reduces the area of logic BIST test points. Conversely, the X-bounding and any test points that are added for logic BIST make the circuit more testable and improve the embedded compression coverage and pattern count results.

Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (design-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing, glitch-free clock switching, and patents pending on 3D DFT.

Blog Review: December 2, 2013

Monday, December 2nd, 2013

Phil Garrou completes his look at various packaging and 3D integration happenings from Semicon Taiwan, including news from Disco, Namics and Amkor. Choon Lee of Amkor, for example, predicted a silicon interposer cost of 2.7-4$/cm sq (100 sq mm) and expectations of organic interposer costs at 50% cost reduction.

Dynamic resource allocation can significantly improve turnaround time in post-tapeout flow. Mark Simmons of Mentor Graphics blogs about recent work that demonstrated 30% aggregate turnaround time improvement for a large set of jobs in conjunction with a greater than 90% average utilization across all hardware resources.

The MEMS Industry Group blog reflects on the trend toward sensor fusion and the role that hardware approaches such as FPGAs and microcontrollers will play in moving the technology forward.

44 years ago, the internet was born when two computers, one at UCLA and one at the Stanford Research Institute, connected over ARPANET (Advanced Research Projects Agency Network) to exchange the world’s first “host-to-host” message. Ricky Gradwohl of Applied Materials celebrates the “birthday” with thoughts on how far the internet has come.

A Call To Action: How 20nm Will Change IC Design

Thursday, February 21st, 2013

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.

To download this white paper, click here.