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Posts Tagged ‘E-beam’

Companies Ready Cobalt for MOL, Gate Fill

Thursday, December 21st, 2017

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By Dave Lammers

Cobalt for middle-of-the-line and trench contacts emerged at the International Electron Devices Meeting, as Intel, GlobalFoundries, and Applied Materials discussed how to best take advantage of cobalt’s properties.

For its forthcoming 10nm logic process, Intel Corp. used cobalt for several of the lower metal levels, including a cobalt fill at the trench contacts and cobalt M0 and M1 wiring levels. The result was much-improved resistivity and reliability, compared with the traditional metallization at those levels.

Cobalt was used for the local interconnects of the Intel 10nm process, improving line resistance by 60 percent. (Source: Intel)

Chris Auth, director of logic technology at Intel’s Portland Technology Center, said the contacted line resistance “provides a good indicator of the benefits of cobalt versus tungsten,” with a 60 percent reduction in line resistance and a 1.5X reduction in contact resistance.

While cobalt was used for the local interconnects, the upper 10 metal layers were copper, with a cobalt cap used for layers M2-M5 to provide a 50X improvement in electro-migration. Intel continued to use tungsten for the gate fill.

John Pellerin, a vice president at GlobalFoundries who directs global research and development, said GlobalFoundries decided that for its 7nm logic technology, ramping in mid-2018, it would replace tungsten with cobalt at the trench contact level, which is considered the first level of the middle-of-the-line (MOL).

“We are evaluating it for implementation into the next level of contact above that. Cobalt trench level contacts are process of record (POR) for the 7nm technology,” Pellerin said in an interview at the 2017 IEDM, held Dec. 2-6 in San Francisco.

High performance logic often involves four-fin logic cells to drive the maximum amount of current from the largest transistor width. “You have to get that current out of the transistor. That is where the MOL comes into play. Junction and MOL resistance optimization is key to taking advantage of a four-fin footprint, and it takes a multi-front optimization to take advantage of that equation.

Pellerin said the biggest challenge with tungsten trench contacts is that the CVD process tends to leave a seam void. “We are always fighting seam voids. With cobalt deposition we get an intrinsic resistance improvement, and don’t get seam voids by pushing tungsten down in there,” Pellerin said.

Tighter Metal Pitches

Scotten Jones, president of consultancy IC Knowledge (Boston), said semiconductor vendors will introduce cobalt when it makes sense. Because it is a new material, requiring considerable costs prior to insertion, companies will use it when they need it.

“Global has trench contacts, while Intel uses cobalt at three levels. But the reason is that Intel has a 36nm minimum metal pitch with its 10nm process, while Global is at 40nm with its 7nm process. It is only at the point where the line gets narrow enough that cobalt starts to make sense.”

Applied Cobalt Solutions

As cobalt begins to replace tungsten at the smaller-dimension interconnect layers, Applied Materials is readying process flows and E-beam inspection solutions optimized for cobalt.

Namsung Kim, senior director of engineering management at Applied Materials, said cobalt has a bulk resistivity that is similar to tungsten, but the barrier thickness required for tungsten at leading-edge transistors is swinging the advantage to cobalt as dimensions shrink.

Line resistance probability plot of cobalt versus tungsten at 12nm critical dimensions. (Source: Applied Materials)

“Compared with tungsten, cobalt has a very thin barrier thickness, so you can fill up with more material. At our Maydan Technology Center, we’ve developed a reflow process for cobalt that is unique,” Kim said. The cobalt reflow process uses an annealing step to create larger cobalt grain sizes, reducing the resistance. And because there is no source of fluorine in the cobalt deposition steps, a thin barrier layer can suffice.

At IEDM, Naomi Yoshida, a distinguished member of the technical staff at Applied, presented a paper describing Applied’s research using cobalt to fill a 5nm-logic-generation replacement metal gate (RMG). The fill is deposited above the high-k dielectric and work function metals, and at the 5nm node and beyond there is precious little room for the gap fill metal.

Yoshida said modern transistors use multiple layers of work-function metals to control threshold voltages, with high-performance logic requiring low Vt’s and IoT devices requiring relatively high Vt’s. After the different work function layers are deposited, the fill material is deposited.

At the 5nm node, Applied Materials estimates that the contacted poly pitch (CPP) will shrink to about 42nm, while the gate length (Lg) will be less than 12nm. “There is very limited space for the fill materials, so customers need a more conductive metal in a limited space. That is the major challenge,” Yoshida said in an interview at the IEDM.

Work Function Maintained

Naomi Yoshida: room for gate fill disappearing

The Applied R&D work showed that if the barrier layer for a tungsten fill is reduced too much, to a 2nm or 3nm TiN layer for example, the effective work function (eWF) degrades by as much as 500mV eWF and the total gate conductance suffers. With the CVD process used to deposit a tungsten RMG fill, there was “significant fluorine diffusion” into the work function metal layer in the case of a 2nm TiN barrier.

By contrast, the cobalt fill maintained the NMOS band-edge eWF with the same 2nm TiN barrier.

Gradually, cobalt will be adopted more widely for the contacts, interconnects, and RMG gate fill steps. “It is time to think about how to achieve more conductance in the gate material. Previously, people said there was a negligible contribution from the gate material, but now with the smaller gates at 5nm, gate fill metal makes a huge contribution to resistance, and barrier thickness reduction is important as well,” Yoshida said.

E-beam Inspection

Nicolas Breil: E-beam void inspection useful for cobalt contacts

Applied Materials also has developed an e-beam inspection solution, ProVision, first introduced in mid-2016, and has optimized it for inspecting cobalt voids. Nicolas Breil, a director in the company’s contact module division, said semiconductor R&D organizations are busy developing cobalt contact solutions, optimizing the deposition, CMP, and other steps. “For such a dense and critical level as the contact, it always needs very careful engineering. They key is to get results as fast as possible, but being fast can be very expensive.”

Amir Wachs, business development manager at Applied’s process diagnostics and control business unit in Rehovat, Israel, said the ProVision e-beam inspection system has a resolution of 1nm, at 10,000-20,000 locations per hour, taking a few hundred measurements on each field of view.

“Voids form when there are adhesion issues between the cobalt and TiN. One of the key issues is the correct engineering of the Ti nitride and PVD cobalt and CVD cobalt. To detect embedded voids requires a TEM inspection, but then customers get very limited statistics. There might be a billion contacts per chip, and with conventional TEM you might get to inspect two.”

The ProVision system speeds up the feedback loop between inspection and co-optimization. “Customers can assess the validity of the optimization. With other inspection methods, co-optimization might take five days to three weeks. With this type of analysis, using ProVision, customers can do tests early in the flow and validate their co-optimization within a few hours,” Wachs said.

Multibeam Patents Direct Deposition & Direct Etch

Monday, November 14th, 2016

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By Ed Korczynski, Sr. Technical Editor

Multibeam Corporation of Santa Clara, California recently announced that its e-beam patent portfolio—36 filed and 25 issued—now includes two innovations that leverage the precision placement of electrons on the wafer to activate chemical processes such as deposition and etch. As per the company’s name, multi-column parallel processing chambers will be used to target throughputs usable for commercial high-volume manufacturing (HVM) though the company does not yet have a released product. These new patents add to the company’s work in developing Complementary E-Beam Lithography (CEBL) to reduce litho cost, Direct Electron Writing (DEW) to enhance device security, and E-Beam Inspection (EBI) to speed defect detection and yield ramp.

The IC fab industry’s quest to miniaturize circuit features has already reached atomic scales, and the temperature and pressure ranges found on the surface of our planet make atoms want to move around. We are rapidly leaving the known era of deterministic manufacturing, and entering an era of stochastic manufacturing where nothing is completely determined because atomic placements and transistor characteristics vary within distributions. In this new era, we will not be able to guarantee that two adjacent transistors will function the same, which can lead to circuit failures. Something new is needed. Either we will have to use new circuit design approaches that require more chip area such as “self-healing” or extreme redundancy, or the world will have to inspect and repair transistors within the billions on every HVM chip.

In an exclusive interview with Solid State Technology, David K. Lam, Multibeam Chairman, said, “We provide a high-throughput platform that uses electron beams as an activation mechanism. Each electron-beam column integrates gas injectors, as well as sensors, which enable highly localized control of material removal and deposition. We can etch material in a precise location to a precise depth. Same with deposition.” Lam (Sc.D. MIT) was the founder and first CEO of Lam Research where he led development and market penetration of the IC fab industry’s first fully automated plasma etch system, and was inducted into the Silicon Valley Engineering Hall of Fame in 2013.

“Precision deposition using miniature-column charged particle beam arrays” (Patent #9,453,281) describes patterning of IC layers by either creating a pattern specified by the design layout database in its entirety or in a complementary fashion with other patterning processes. Reducing the total number of process steps and eliminating lithography steps in localized material addition has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material deposition allows for controlled variation of deposition rate and enables creation of 3D structures such as finFETs and NanoWire (NW) arrays.

Deposition can be performed using one or more multi-column charged particle beam systems using chemical vapor deposition (CVD) alone or in concert with other deposition techniques. Direct deposition can be performed either sequentially or simultaneously by multiple columns in an array, and different columns can be configured and/or optimized to perform the same or different material depositions, or other processes such as inspection and metrology.

“Precision substrate material removal using miniature-column charged particle beam arrays” (Patent #9,466,464) describes localized etch using activation electrons directed according to the design layout database so that etch masks are no longer needed. Figure 1 shows that costs are reduced and edge placement accuracy is improved by eliminating or reducing errors associated with photomasks, litho steps, and hard masks. With highly localized process control, etch depths can vary to accommodate advanced 3D device structures.

Fig.1: Comparison of (LEFT) the many steps needed to etch ICs using conventional wafer processing and (RIGHT) the two simple steps needed to do direct etching. (Source: Multibeam)

“We aren’t inventing new etch chemistries, precursors or reactants,” explained Lam. “In direct etch, we leverage developments in reactive ion etching and atomic layer etch. In direct deposition, we leverage work in atomic layer deposition. Several research groups are also developing processes specifically for e-beam assisted etch and deposition.”

The company continues to invent new hardware, and the latest critical components are “kinetic lens” which are arrangements of smooth and rigid surfaces configured to reflect gas particles. When fixed in position with respect to a gas injector outflow opening, gas particles directed at the kinetic lens are collimated or redirected (e.g., “focused”) towards a wafer surface or a gas detector. Generally, surfaces of a kinetic lens can be thought of as similar to optical mirrors, but for gas particles. A kinetic lens can be used to improve localization on a wafer surface so as to increase partial pressure of an injected gas in a target area. A kinetic lens can also be used to increase specificity and collection rate for a gas detector within a target frame.

Complementary Lithography

Complementary lithography is a cost-effective variant of multi-patterning where some other patterning technology is used with 193nm ArF immersion (ArFi) to extend the resolution limit of the latter. The company’s Pilot™ CEBL Systems work in coordination with ArFi lithography to pattern cuts (of lines in a “1D lines-and-cuts” layout) and holes (i.e., contacts and vias) with no masks. These CEBL systems can seamlessly incorporate multicolumn EBI to accelerate HVM yield ramps, using feedback and feedforward as well as die-to-database comparison.

Figure 2 shows that “1D” refers to 1D gridded design rule. In a 1D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool such as Multibeam’s array of electrostatically-controlled miniature electron beam columns. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The company claims that low pattern-density layers such as for cuts, one multi-column chamber can provide 5 wafers-per-hour (wph) throughput.

Fig.2: Complementary E-Beam Lithography (CEBL) can be used to “cut” the lines within a 1D grid array previously formed using ArF-immersion (ArFi) optical steppers. (Source: Multibeam)

Direct deposition can be used to locally interconnect 1D lines produced by optical lithography. This is similar in design principle to complementary lithography, but without using a resist layer during the charged particle beam phase, and without many of the steps required when using a resist layer. In some applications, such as restoring interconnect continuity, the activation electrons are directed to repair defects that are detected during EBI.

—E.K.

D2S Releases 4th-Gen IC Computational Design Platform

Friday, September 30th, 2016

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By Ed Korczynski, Sr. Technical Editor

D2S (www.design2silicon.com) recently released the fourth generation of its computational design platform (CDP), which enables extremely fast (400 Teraflops) and precise simulations for semiconductor design and manufacturing. The new CDP is based on NVIDIA Tesla K80 GPUs and Intel Haswell CPUs, and is architected for 24×7 cleanroom production environments. To date, 14 CDPs across four platform generations are in use by customers around the globe, including six of the latest fourth generation. In an exclusive interview with SemiMD, D2S CEO Aki Fujimura stated, “Now that GPUs and CPUs are fast-enough, they can replace other hardware and thereby free up engineering resources to focus on adding value elsewhere.”

Mask data preparation (MDP) and other aspects of IC design and manufacturing require ever-increasing levels of speed and reliability as the data sets upon which they must operate grow larger and more complex with each device generation. The Figure shows a mask needed to print arrays of sub-wavelength features includes complex curvilinear shapes which must be precisely formed even though they do not print on the wafer. Such sub-resolution assist features (SRAF) increase in complexity and density as the half-pitch decreases, so the complexity of mask data increases far more than the density of printed features.

Sub-wavelength lithography using 193nm wavelength requires ever-more complex masks to repeatably print ever smaller half-pitch (HP) features, as shown by (LEFT) a typical mask composed of complex nested curves and dots which do not print (RIGHT) in the array of 32nm HP contacts/vias represented by the small red circles. (Source: D2S)

GPUs, which were first developed as processing engines for the complex graphical content of computer games, have since emerged as an attractive option for compute-intensive scientific applications due in part to their ability to run many more computing threads (up to 500x) compared to similar-generation CPUs. “Being able to process arbitrary shapes is something that mask shops will have to do,” explained Fujimura. “The world could go 193nm or EUV at any particular node, but either way there will be more features and higher complexity within the features, and all of that points to GPU acceleration.”

The D2S CDP is engineered for high reliability inside a cleanroom manufacturing environment. A few of the fab applications where CDPs are currently being used include:

  • model-based MDP for leading-edge designs that require increasingly complex mask shapes,
  • wafer plane analysis of SEM mask images to identify mask errors that print, and
  • inline thermal-effect correction of eBeam mask writers to lower write times.

“The amount of design data required to produce photomasks for leading-edge chip designs is increasing at an exponential rate, which puts more pressure on mask writing systems to maintain reasonable write times for these advanced masks. At the same time, writing these masks requires higher exposure doses and shot counts, which can cause resist proximity heating effects that lead to mask CD errors,” stated Noriaki Nakayamada, group manager at NuFlare Technology. “D2S GPU acceleration technology significantly reduces the calculation time required to correct these resist heating effects. By employing a resist heating correction that includes the use of the D2S CDP as an OEM option on our mask writers, NuFlare estimates that it can reduce CD errors by more than 60 percent, and reduce write times by more than 20 percent.”

In the E-beam Initiative 2015 survey, the most advanced reported mask-set contained >100 masks of which ~20% could be considered ‘critical’. The just released 2016 survey disclosed that the most complex single-layer mask design written last year required 16 TB of data, however platforms like D2S’ CDP have been used to accelerate writing such that the average reported write times have decreased to a weighted average of 4 hours. Meanwhile, the longest reported mask write time decreased from 72 to 48 hours.

Applied Materials Intros High Res E-Beam Inspection System

Monday, July 11th, 2016

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Applied Materials, Inc. introduced its next-generation e-beam inspection system that offers resolution down to 1nm. This allows users to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields. Called PROVision™, the system offers 3x faster throughput over existing e-beam hotspot inspection tools.

Ram Peltinov, senior director, strategic marketing for the Process Diagnostics and Control Group at Applied Materials, said the development of the new system was driven by a number of new challenges: Structures and defects are now too small for optical resolution; multi-patterning triggers a need for massive measurements; and 3D architectures limit the ability to detect and measure.

“FinFETs are becoming increasingly complex, the multi-patterning creates multiple steps, the DRAM aspect ratios are getting very high and the VNAND is going vertical,” he said. “All these changes are happening in parallel and this creates great opportunity for metrology and inspection,” he said. According to Gartner, the market for e-beam inspection systems has tripled in the last five years, from $81M in 2010 to $241M in 2015.

The system’s high current density (beam current per sampling area) eliminates the sampling/throughput tradeoff of previous systems, allowing the fastest sampling throughput at its 1nm resolution. Imaging capabilities encompass techniques such as see-through, high aspect ratio, 360° topography, and back-scattered electron detection.

“It allows them to capture defects they couldn’t see before,” Peltinov said. The system can detect, for example, epi-overgrowth in FinFETs. “While the epi overgrowth is clearly visible on the PROVision, it’s almost impossible to see in conventional EBI. Without the resolution and the special imaging, it’s very difficult to catch that.”

“They can also increase their sampling with the faster throughput on the most challenging layers. This also helps them reveal process signatures of their most subtle process variation,”  Peltinov added. Massive sampling reveals hidden process trends and “signatures” that help identify sources of abnormalities, and shorten the time to root cause from days to minutes.


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