By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti.

SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam e-beam. Let’s start with DSA. What is CEA-Leti doing in DSA?
Pain: For DSA, we have what we call the ‘Ideal’ program. We are developing 300mm processes. We have materials development with Arkema. Other partners include TEL and Sokudo. We are working with STMicroelectronics to transfer the technology from a process point of view. We are developing this capability for lab scaling to industry production.

SMD: What have you demonstrated with DSA?
Pain: We have demonstrated resolutions down to 18nm half-pitch, which is considered the 7nm logic node. We think we can extend PS-b-PMMA down to the 7nm node. The concept is to enable 7nm to 4nm resolutions with Arkema’s materials.

SMD: The big question is when do you think DSA will move into production?
Pain: From my point of view, it should be 10nm. You will start to see some demonstrations at 14nm.
Tedesco: You can ask me that in July. I still say 2014.

SMD: What are the challenges with DSA?
Pain: There will be some challenges in terms of defectivity and process maturity.
Tiron: For contact shrinks, the processes are here. It’s stable. That means you can absorb a lot of the variations with the block copolymers. But you don’t have pitch or density. If you move to contact doubling, you have the density. But you lose the process window stability. The placement of the contacts is also less certain. But what is important is now we have materials, processes and tracks. What we really need now is some real fabrication. The applications depend on the end-user. What we need is the end-users to tell us: ‘We need this and that and then move in that direction.’ That’s what is missing today.

SMD: What have you accomplished in your DSA process flow?
Tiron: We have implemented a process flow on a 300mm track, which comes from Sokudo. We have a complete DSA process cycle in one track. The track handles the brush coat and block copolymer coating. The track also has high temperature hot plates for block copolymer cure. We also worked with Sokudo to develop a PMMA removal process. We demonstrated different exposure treatments and solvents. What we are trying to do now is address contact hole shrinks and contact multiplication. With the polymers from Arkema, we are able to do resolutions from 20nm period, which means 10nm resolution, to 60nm period, which means 35nm resolution. Contact shrink is possible using both cylindrical and lamellar morphologies.

SMD: What about yield or defects?
Tiron: We have shown good uniformities with three sigma around 2nm. After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts. By using block copolymers, we showed 99.93 % valid contacts on the wafer. This is just using PMMA.

SMD: Let’s move to multi-beam. What is CEA-Leti doing in multi-beam?
Pain: The second program is called Imagine. This program started last year. We have a partnership with (multi-beam e-beam vendor) Mapper Lithography. Other partners include Aselta, JSR, TOK, TSMC, Sokudo, Dow, STMicroelectronics, TEL and Mentor.

SMD: How far along is Mapper’s multi-beam tool?
Pain: The first machine will consist of 1,300 beams. The throughput is one wafer per hour. The tool will arrive the beginning of June. That’s targeted for the 14nm logic node. This machine will be interfaced with the Sokudo track. The first exposures will start in the last quarter of this year. Eventually, the target is to reach 16nm half-pitch. Our goal is to have 13,000 beams with the Mapper tool. We expect to scale the throughput from one wafer per hour to 10 wafers an hour. Then, we plan to push the resolutions down to 10nm half-pitch.

SMD: What is the cost-of-ownership for the Mapper tool?
Pain: The cost is 1 million euros for two wafers per hour. So in other words, that’s 5 million euros for 10 wafers per hour. Our eventual goal is to cluster 10 machines together. That’s 50 million euros for the cluster configuration.

SMD: Isn’t multi-beam taking longer than expected and behind schedule?
Pain: If you take the original roadmap, we are late. Some of the technical achievements have taken a long time.
Tedesco: One of the problems is there is a lack of support from the industry. It’s a shame that there is a lack of support, when you look at what’s being done on the EUV side. That’s one of the reasons that multi-beam is not mature yet. Of course, there is the technical aspect. TSMC, of course, is the one that is pushing this technology. But beyond TSMC, there is a lack of support. But I think the support will eventually come.

SMD: TSMC has stated it wants to do all layers with multi-beam. Is that practical or will multi-beam end up doing traditional direct-write applications like ASICs?
Tedesco: It could be a challenge to do all layers with multi-beam. But a maskless tool could be useful in terms of ASICs or prototyping. It’s ideal for the foundries. But the first applications for multi-beam will likely be contact holes and the cut layer.

SMD: How about STMicroelectronics? STMicroelectronics has been involved with direct-write for many years.
Tedesco: ST is a partner of Leti. So they are following Imagine very closely.

SMD: What about funding for multi-beam from the likes of Intel, GlobalFoundries and Samsung?
Tedesco: Good question. What we can say is that they are following us very closely. They know what we are doing. At this point, they are not part of the program.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: What does hybrid metrology accomplish in the process control flow?
Allgair: The structures are becoming so complex. You are trying to measure a particular application on a 3D device, where you have a lot of variations that already took place prior to the measurement step. Hybrid is one of the ways to address that challenge. For us, it enables us to use a lot of the information that is collected upstream for the measurement event you are actually doing. It allows us to understand, as much as we can, about the structure in terms of how it was processed and what it looks like prior to that measurement step. And then, for the variables you are trying to measure, it helps reduce some of the uncertainty of those variables you may not understand from that particular process step you are measuring. Again, that information can be thickness, compositional and CD.

SMD: Do you think directed self-assembly (DSA) will succeed? And does the industry have an inspection/metrology solution for DSA?
Allgair: As we keep driving litho, there is a decent chance that DSA will happen. We will probably try to postpone it as long as we can, and try and get through what we’re currently using. When it does happen, it may end up being a different type of solution than we thought. After SPIE, and looking at one of the papers from MIT, it looks like there might be a way to measure the structures that were used to pattern your DSA. It might be that we monitor that structure. Then, we will have some confidence that the DSA activity takes place and works. All told, if we can get a DSA system that works well, and there is a cost advantage to it, that could drive an earlier adoption for DSA. That is a big component to DSA.
Heidrich: We certainly see the promises. The cost reduction is there, but the challenges of proving low defectivity and performance still remain. Certainly, in the case of memory and related types of processes, where you have redundancy, DSA will get adopted earlier. There has been work on contact holes, where you can do reduction with DSA. When the yield is proven, and if the cost benefit is there, DSA will get adopted. But I think that is still quite a few years away.
Newcomb: DSA is just one of the options available. We have all been in the industry long enough to know there are multiple options. But DSA is the one you want to try to avoid as long as possible because there are many unique challenges. Will it happen? Maybe not. If it does, you have to put all of the pieces together to bring it into high volume production. The challenge comes down to defectivity and integration.
Shetty: DSA is exciting. DSA will most likely happen, but cost would be the biggest challenge in terms of making it production-worthy.

SMD: The industry is in need of new inspection/metrology breakthroughs and tools. Do you agree? And how does the industry fund the development of new tools when there are not enough R&D dollars?
Allgair: It is apparent that we have a need for some new techniques. The ones we’ve talked about are multi-beam e-beam inspection, CD-SAXS, helium ion and a higher resolution CD tool. These are addressing defect-inspection resolution, CD resolution, scatterometry and compositional analysis. The problem that we are trying to grasp is the people that use these new tools are the ones on the leading edge. Those are for devices at 14nm and beyond. There are not a lot of companies in that space. So, it’s not clear how many tools would get ordered at the leading edge. And the other problem is chipmakers like GlobalFoundries, Intel and others may not have provided a clear and concise message in terms of what our future tool needs are to the toolmakers. Regarding GlobalFoundries, as well as my peers at Intel, TSMC and others, we all need to get a little better organized in terms of defining our problem statement to the tool vendors. The second piece is how do you fund a new tool development program? That one is challenging. We’ve seen other funding models, where we have joined other companies and put money together to drive the development of a new tool in litho or to drive a consortium. It’s possible that chipmakers can get together and try to drive something along that line. Another possibility is that each customer could buy the first generation of new tools from vendors. That might be enough for suppliers, who can then seek funding on their own.
Heidrich: We see two things that are challenging from the R&D point of view. One is the rapid consolidation from our end-customer base. We have fewer than a dozen major customers left. In the near- or long-term, that number will likely get smaller. So you have to have fewer customers to absorb the R&D for all the products you need to develop. Secondly, we have very diverse and complex process flows that different customers are adopting. This could be a finFET flow, vertical memory flow, or a 3D device integration flow. So you have more demands on your R&D. Right now, we need to make sure the R&D dollars solve the hard problems and we leverage that learning across all the different end customers. What that means is that if someone has a unique challenge, it gets harder and harder to provide a custom solution.

SMD: What about VC-backed startups like Qcept?
Newcomb: If you go way back, the industry had lots of startups. You had tier-one customers of course, but you also had a plethora of tier-two and tier-three fabs in the world. Now, as an equipment maker, you are not going to get funding that easily, because there are maybe 12 or less major customers in the world. It also takes more money to develop products. The dynamics are also different. You have new memory and logic requirements. We are tying together the OSATs and fabs with 3D TSV integration. In addition, the industry is moving towards two major suppliers on the equipment side and a handful of customers on the device side. That dynamic makes it very difficult. The big challenge is how will the industry keep investing and address those types of needs?

SMD: What’s the solution to this problem?
Newcomb: In one possible solution, companies on the device side could pre-buy the technology rights to the first tool to help fund some of the required investment and R&D. Or maybe, we can better integrate the university work into a model that can be funded and driven into the industry to solve a problem.
Shetty: R&D is becoming expensive. The device nodes are shrinking quickly. And customers’ expectations are increasing. Across the industry, everyone is pushing to get a lower cost-of-ownership and higher productivity. That’s just a fact of life. There are maybe 12 customers out there. But between the joint ventures and consortia, there are maybe four or five R&D centers out there. Today, it is very important that you are involved with these R&D fabs very early in the process. Then, the tool evolves with the process. So when customers move into production, the tool is already mature and ready to go. On the other hand, the devices are changing so much. And in a lot of cases, the customers themselves don’t know what’s going to happen.

Frog Robot Surgeons
The University of Leeds is leaping towards an amazing discovery. Researchers are using the feet of tree frogs as a model for a tiny robot used in human surgeries.

The device is designed to move across the internal abdominal wall of a patient. The feet of a frog will provide a solution to the problem of getting the device to hold onto wet, slippery tissue in a potential surgery.

Leeds’ frog robot has four feet and weights 20 grams. Each foot is capable of holding a maximum of about 15 grams for each square centimeter in contact with a surface. On its Web site, Professor Anne Neville, Royal Academy of Engineering Chair in Emerging Technologies at the University of Leeds, said: “Tree frogs have hexagonal patterned channels on their feet that when in contact with a wet surface build capillary bridges, and hence an adhesion force. It is the same kind of idea as a beer glass sticking to a beer mat, but the patterns build a large number of adhesion points that allow our robot to move around on a very slippery surface when it is upside down.”

Brain LEDs
The University of Illinois at Urbana-Champaign and Washington University in St. Louis have devised a tiny, injectable LED for use in studying the brain.

The LEDs will help pave the way in optogenetics, which uses light to stimulate targeted neural pathways in the brain. The LED technology could have implications for treatment of Alzheimer’s, Parkinson’s, depression and other neurological disorders.

The device platform includes LEDs, temperature and light sensors, heaters and electrodes. The LEDs themselves are injected into the brain. The devices are printed onto the tip end of a thin, flexible plastic ribbon.

A thin plastic ribbon printed with advanced electronics is threaded through the eye of an ordinary sewing needle. The device, containing LEDs, electrodes and sensors, can be injected into the brain or other organs. Photo courtesy John A. Rogers/University of Illinois

The ribbon connects the devices to a wireless antenna and a rectifier circuit. These devices in turn harvest RF energy to power the devices. This module mounts on top of the head. It can be unplugged from the ribbon when not in use.

“These materials and device structures open up new ways to integrate semiconductor components directly into the brain,” said John Rogers, the Swanlund professor of materials science and engineering at the U. of I., on the university’s Web site. “More generally, the ideas establish a paradigm for delivering sophisticated forms of electronics into the body: ultra-miniaturized devices that are injected into and provide direct interaction with the depths of the tissue.”

Watching Self-Assembly In Real Time
The Center for Nanoscale Materials at the U.S. Department of Energy’s (DOE) Argonne National Laboratory claims to be the world’s first organization to see the self-assembly of nanoparticle chains take place in real time.

Using in-situ transmission electron microscopy (TEM), researchers investigated the self-assembly of gold nanoparticles coated with positively charged cetyltrimethylammonium ions (CTA+) and negatively charged citrate ions in aqueous liquid cells.

Researchers exposed the liquid cell to a beam of electrons generated with a TEM. The hydrated electrons reduced the overall positive charges of the CTA+ covered gold nanoparticles. It also decreased the repulsive electrostatic forces among the nanoparticles, according to researchers.

This, in turn, led to the assembly of individual nanoparticles into 1D structures. Meanwhile, the negatively charged gold nanoparticles coated with citrate ions are steady in liquid cell regardless of electron beam intensity, according to researchers.

All told, the nanoparticles jump around and stick together in long chains. This technique allowed researchers to observe the process as it occurred. “The moment-to-moment behavior of nanoparticles is something that’s not yet entirely understood by the scientific community,” said Argonne nanoscientist Yuzi Liu, on Argonne’s Web site. “The potential of nanoparticles in all sorts of different applications and devices–from tiny machines to harvesters of new sources of energy–requires us to bring all of our resources to bear to look at how they function on the most basic physical levels.”

—Mark LaPedus

By Mark LaPedus
Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear.

3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many chipmakers are still developing these technologies and face several process control challenges.

“In our industry, a lot of segments are metrology-limited,” said Christopher Bencher, a member of the technical staff at Applied Materials. “Overlay metrology is the number one area where we are limited. There is also a challenge with 3D devices like finFETs and 3D NAND. You have to be able to characterize them in 3D.”

As with many fab tool markets, there is a disconnect between the rhetoric from chipmakers and equipment vendors. Process control tool vendors insist they are ready for the 3D era. In contrast, chipmakers say many of the existing metrology solutions are running out of steam.

For example, some 50% of the process steps in a fab are devoted to inspection and metrology alone. About 10% of those steps use the workhorse metrology tool in the fab—the critical-dimension scanning electron microscope (CD-SEM). With finFETs, the CD-SEM is being stretched to its limits. “Three quarters of the steps can be handled by a conventional CD-SEM,” said Eric Solecky, senior manufacturing engineer at IBM. “This percentage is growing. It’s that fraction for 3D information that we don’t have a solution today for an image-based tool.”

Near term, there are other challenges in process control. “The main gaps in general are next-generation defect inspection, next-generation charge particle imaging, and next-generation scatterometry profile metrology,” said Benjamin Bunday, senior technical staff member at Sematech. Longer term, the industry also lacks a process control solution for graphene, carbon nanotubes and directed self-assembly (DSA).

Metrology madness
Several tool types—AFM, CD-SEM and OCD—can handle most requirements for today’s planar chips. Atomic force microscopy (AFM) uses a tiny probe to enable measurements. The CD-SEM is used for top-down measurements. And used for CD and overlay, optical scatterometry (OCD) measures the changes in the intensity of light.

But the process control world changed in 2011, when Intel rolled out the industry’s first finFETs. Using a transmission electron microscope (TEM), Chipworks recently discovered that the traditional one-to-one ratio between structures and transistors doesn’t apply with Intel’s tri-gate technology. In fact, one transistor can have multiple fins—six or more—while one fin can have multiple transistors, according to Chipworks.

So for finFETs, a given metrology tool must measure and characterize the separate pieces in the structure, such as the gate, fin height, sidewall angle and others. Each of those parts also requires one or more separate measurements.

The question is which single metrology tool can handle all requirements for structures such as finFETs and 3D NAND? The answer: None of them. There is no silver bullet. “We are already in a deluge of data,” said Jason Osborne, senior systems design engineer at Bruker. “We’ve got many systems making multiple measurements on the same structures and not getting the entire answer off any one system.”

In one possible finFET metrology flow, the fin is measured by the CD-SEM or AFM, and then, the results are feed to the OCD tool. Another possible metrology flow involves the CD-SEM, OCD and a TEM. The TEM, a system that shoots a beam of electrons through a tiny specimen, is used to validate the OCD model. “What you are trying to do is make your scatterometry model more robust,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries.

Intel, meanwhile, uses a combination of undisclosed tool technologies within its finFET process control flow. “We need all solutions,” said Adam Schafer, area manager of metrology and inspection at Intel. “We need to combine them.”

In process control, the biggest challenges for Intel can be summarized in three words—cost, noise and throughput. “Noise is one of our top problems. And it is really distinguishing the signal from the noise in any one of our techniques,” Schafer said.

Each tool type has its own set of issues. “If you are talking about CD-SEM, my CD measurement is traditionally top down. That’s not enough. I cannot control my processes with those CDs,” said Alok Vaid, senior member of the technical staff at GlobalFoundries. “Regarding OCD, it’s a solution, but it’s too complicated. So if you look at 14nm, 10nm and beyond, I don’t think the small dimensions are an issue for OCD. In fact, it can work in your favor. The problem is correlations.”

For AFM, the challenge is to measure finFETs in 10nm to 20nm spaces and characterize the profiles and shapes, he said. “We can’t leave optical tools such as ellipsometry out of the picture. Since everything is going 3D, now you want to measure those thicknesses and compositions on actual 3D structures,” he said.

The solutions
For some time, GlobalFoundries and others have been talking about the solution to the 3D problem—hybrid metrology. In this approach, separate tool technologies are used in a flow. The challenge is to put rival tool vendors in the same flow and tell the competitors to collaborate and share proprietary data with each other. “Let’s take an example. You have a CD-SEM supplier. You have an OCD supplier. And let’s say you want to overlap them and get my results. You can’t do that unless you get those guys to draw an algorithm together and get them to collaborate,” Vaid said.

While hybrid metrology is perhaps the wave of the future, tool vendors are also improving their respective technologies. For example, using Applied Materials’ CD-SEM, IBM conducted measurements in a theoretical gate-all-around finFET with silicon nanowires. In this experiment, “you see nice defined edges, even when you are beyond the resolution image,” said Ofer Adan, managing technology and marketing manager at Applied Materials. “So can we go beyond 14nm? What this work tells me is that a CD-SEM can go down to 6nm on a gate-all-around device.”

This is not to say the CD-SEM can handle all finFET requirements. “It cannot see whether or not there is an undercut. We need to work together with the OCD guys,” Adan said.

Overlay is another challenge and OCD is being stretched to the limits. KLA-Tencor recently unveiled a dimensional metrology system, which includes a new OCD technology based on a laser-driven source. “We think this is an inflection point for scatterometry,” said Andrei Shchegrov, director of advanced development at KLA-Tencor. “Our signal-to-noise gets a huge boost across a very wide range of wavelengths. We found the increased sensitivity due to the light source allows us to see things we couldn’t see before. It allows us to measure deep structures like high-aspect ratio 3D NAND flash.”

Despite the breakthroughs, the industry is still searching for new and better 3D metrology solutions. There are some promising candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging. And X-ray scattering (CD-SAXS) could succeed OCD.

“The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said IBM’s Solecky. “So the question is, ‘Do you need 3D information on the smallest features?’ The answer is yes. Potentially, helium ion is the solution.”

Helium ion enables 3D images, but the technology also can damage a device. The industry is looking for ways to tweak the helium ion microscope, which would make it somewhat comparable to the CD-SEM. “Technically, this involves a lot of challenges to make (helium ion into) a CD-SEM kind of tool. Those are not unsolvable problems, but it requires a lot of investments,” said Bipin Singh, product manager for Zeiss, a supplier of helium ion scopes and other fab tools.

As a replacement for OCD, the industry is looking at CD-SAXS, an X-ray scattering technology based on a synchrotron radiation source. “If you want 3D structures, you can certainly do it with CD-SAXS,” said Joseph Kline, a materials engineer at NIST. “The main limiter for CD-SAXS is throughput. Most of the measurements with CD-SAXS are done with a synchrotron source. Clearly, we are not going to have something like this in the fab. We are trying to figure out how to get a new source and make it work.”

There are other major gaps in metrology. For example, the current buzz in lithography centers on DSA, but it’s unclear if the industry has a metrology solution. “Metrology needed for DSA is really not different than the metrology needed for the rest of the industry,” said Applied’s Bencher. “You need to measure the registration of the holes. Now, when you are defining all of your holes by a mask, things tend to shift systematically, at least within the mobile region of the wafer. So how do you obtain an overlay measurement when things on the local level are shifted randomly? That’s not clear. It requires a different way of thinking.”

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”

Crying Need For Tunable Materials
Tunable materials that adapt to environmental changes are in their infancy and currently limited, according to researchers at the Wyss Institute at Harvard University and Harvard’s School of Engineering and Applied Sciences.

Researchers at Harvard have devised a new class of adaptive materials made from liquid films and nanoporous elastic substrates. The new materials, inspired by tears in the act of crying, are based on a technology called Slippery Liquid-Infused Porous Surfaces (SLIPS).

The materials act as a coating, which repels anything it comes in contact with. Tunable materials can be used in fuel transport, textiles, optical systems, and other applications. For example, the materials could be used on a tent, which blocks light during the day and becomes water-repellent when it is raining. The materials could be used for self-adjusting contact lenses.

According to Harvard, a liquid flows within the pores, causing the smooth and defect-free surface to roughen through a continuous range of topographies. Then, the liquid is transformed into a finely tuned material, which can be dynamically adjusted from an optical transparent or wet state.

Harvard has demonstrated simultaneous control of the film’s transparency and its ability to manipulate various low-surface-tension droplets. “In addition to transparency and wettability, we can fine-tune basically anything that would respond to a change in surface topography, such as adhesive or anti-fouling behavior,” said Xi Yao, Wyss Institute and SEAS postdoctoral fellow, on the entity’s Web Site.

SOI Meets DSA
Using directed self-assembly (DSA), IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. The process could enable next-generation finFETs based on SOI.

DSA uses templates to guide the phase separation of a block co-polymer film. As part of its DSA process, IBM has demonstrated an etch transfer technology. It has demonstrated the process using three integration materials: silicon, silicon nitride, and silicon dioxide based on tetraethyl orthosilicate.

The company studied the critical dimensions, line edge roughness (LER), and line width roughness during the pattern transfer process. IBM demonstrated that co-optimization of the materials and etch process can improve the final transferred pattern.

A fin patterning example for a logic library design.11(a) Fin design. (b) Directed self-assembly (DSA) fins after etch transfer into a silicon-on-insulator (SOI) substrate. The pitch of all dense lines is 29nm. Source: SPIE.

All told, IBM demonstrated that the use of post-etch annealing can further reduce the LER of DSA-patterned SOI lines from ∼3nm to less than 2nm. “By co-optimizing both the circuit design and patterning process, we expect to enable DSA patterning of semiconductor devices and circuits in a 300mm product development environment,” according to IBM on the SPIE Web site.

Battery Boost
Battery technology is not keeping up with Moore’s Law. Consumers want more and longer battery life in cellular phones, tablets and notebook PCs. And even emerging products such as electric vehicles require a longer battery life.

ETH-Zurich is looking at ways to optimize the electrodes in batteries, thereby making them more efficient. In doing so, ETH-Zurich is exploring the discharging and charging process in lithium ion electrodes. Using X-ray tomography, researchers are able to screen lithium ion battery electrodes and reconstruct the microstructures.

Researchers discovered that the electrodes are comprised of numerous particles. The smaller particles are on the edge of the cathode, while the larger ones are in the interior, according to researchers. Smaller particles form compact structures, while the larger ones tend to be porous.

Porosity has an impact on energy density and the speeds at which the ions move through the electrodes, according to researchers. “A lithium battery’s anode is mostly made of graphite,” according to ETH-Zurich’s Web site. “The tortuosity of graphite electrodes might be improved through the use of round graphite particles. The drawback here is that up to seventy per cent of the valuable raw material is wasted during production–one reason why many battery manufacturers still use plate-shaped graphite as an anode material.”

ETH-Zurich also discovered a facile synthesis of monodisperse colloidal tin (Sn) and Sn/SnO2 nanocrystals with mean sizes tunable over the range 9–23nm and size distributions below 10%. Electrochemical measurements demonstrated that 10nm Sn/SnO2 nanocrystals enable high Lithium insertion/removal cycling stability, according to researchers.

—Mark LaPedus

By Mark LaPedus
At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969.

This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo over the potential use of DSA, an alternative patterning technology that enables fine pitches through the use of block copolymers.

A year later, DSA has joined the lithography establishment. Amazingly, within a short time span, DSA has moved from a mere curiosity item into the R&D mode at GlobalFoundries, IBM, Intel, Samsung and TSMC. “Companies are taking DSA seriously,” said Bencher, a DSA expert. “If you compared it to last year, we are now in the pre-competitive stage with DSA. The people in DSA have all grown up and are now wearing suits and ties.”

For some time, most chipmakers have kept their DSA efforts shrouded in secrecy. At the recent SPIE event, however, chipmakers finally provided the first glimpse of their initial work and results.

Based on the early findings, DSA still has a way to go before it moves into IC production. Chipmakers are just getting their arms around the problems. And they are still experimenting with an assortment of fab tools, flows, chemistries and design methodologies.

Still, the initial findings are also promising, providing a clue to where DSA is heading. For example, using DSA, Intel demonstrated 28nm structures. Separately, GlobalFoundries devised 28nm fins with DSA. IBM developed a silicon-on-insulator (SOI) DSA flow. And Samsung may have found the path towards sub-20nm DRAMs.

It’s still unclear when DSA will reach production. The projections range from the 14nm to 7nm nodes. “If you ask different people, you will get different answers,” said Joy Cheng, a research staff member at IBM.

DSA: From the lab to the fab?
DSA is not a next-generation lithography (NGL) tool per se, but rather it is a complementary and double-patterning scheme. DSA is also disruptive and threatens the status quo, because the process isn’t dependent on traditional and costly lithography. Many of the key processing steps are conducted in an existing wafer track system.

There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

In theory, DSA is attractive because it could reduce the overall cost of lithography. And compared to EUV, DSA requires less R&D funding.

“We don’t need billions of dollars,” said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications. “Materials development is inherently cheaper than tool development. The current funding is probably adequate to get the industry going for the 14nm node with DSA. If we’re talking about high chi polymers, which will be needed for the 10nm node and beyond, the industry should think about different funding mechanisms. But even so, we are not talking about huge sums.”

Meanwhile, over the last year, Albany Nanotech, CEA-Leti and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations. “Basically, DSA is still in the R&D stage,” said Charles Pieczulewski, director of strategic marketing for Sokudo, a wafer track supplier. “The industry is still working through the bugs with the materials.”

Going forward, the challenge is to bring DSA into the IC design and production phases. “The main challenge is device integration,” said Ben Rathsack, strategic marketing and technology manager at Tokyo Electron Ltd., the world’s largest wafer track supplier.

Last year, Applied’s Bencher listed defectivity as the top challenge for DSA, followed in order by registration, design flexibility and positional accuracy. For 2013, positional accuracy—or the ability to align the block copolymers in the proper place—has moved to the biggest challenge for DSA, Bencher said.

Bencher expects memory makers will be the early adopters for DSA, followed by logic and foundry vendors. The prediction is based on the ability to generate IC designs using DSA. “You hear people saying: ‘We need a whole design ecosystem to enable DSA.’ That might be true for logic, but these are the last people that would implement DSA. This is because you need the most flexible designs in logic,” Bencher said. “Memory makers don’t really need that whole design ecosystem. They need maybe 1% of the EDA ecosystem, compared to the logic people.”

Currently, there are several design approaches for DSA. One idea is using 1D gridded arrays, but the problems are obvious. “Designers don’t want to be restricted to having contacts only on a grid or vias on a grid,” Bencher said.

Another concept is laying down a sea of holes or fins on a pattern. “In the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which ones you want to keep and which ones you want to get rid of. But the problem is that the aerial image can be very sloppy,” he said.

And in another approach, Stanford University is developing an arbitrary design methodology for DSA using an alphabet soup of characters. In this approach, positional accuracy with the contact holes is the biggest challenge.

Chipmakers tip DSA efforts
Design is just one of the many challenges facing silicon foundries with DSA. For example, GlobalFoundries has set up a DSA R&D line at Albany Nanotech. Using chemical epitaxy, the company demonstrated three-stack, 28nm silicon fin structures. It also is experimenting with a graphoepitaxy flow.

“The advantage for using chemical epitaxy is that there is no loss for aerial density,” said Richard Farrell, a principal engineer at GlobalFoundries. “The advantage in working with graphoepitaxy is that it involves a relatively simple process. Some of the challenges that we face for graphoepitaxy is the translation of the edge roughness into the DSA pattern itself. For line/space, we need temperatures above 200 degrees. This has additional constraints on the lithographic performance of the resists.”

Bringing up DSA in a fab is another issue. “First, we have to deal with fab-compatibility in DSA processing,” he said. “There are contamination issues. In pattern transfer, we need to think about balance reflectivity and the use of planarization.”

Despite the challenges, chipmakers are moving full speed ahead with DSA—and for good reason. For example, NAND flash vendors are pushing 193nm immersion and multi-patterning to the limits, but suppliers are in dire need of a new solution. “EUV lithography and double patterning are widely known (to handle) sub-20nm patterning,” said Jaewoo Nam, a lithography engineer at Samsung, at the recent SPIE conference. “But EUV has some limitations. The pattern resolution for EUV is 16nm only. The cost is huge. Double patterning is also very complicated.”

Using DSA, Samsung is exploring the possibility of developing DRAMs at 18nm. Samsung’s initial goal with DSA is to devise 20nm contact holes. In a DSA R&D line, the company has implemented a graphoepitaxy flow using block PS-b-PMMA materials. With a proprietary treatment process, Samsung has improved the CD distribution by 28%, Nam said.

Like Samsung, Intel also is bullish about DSA. “DSA sparks off a dozen different ideas,” said Sam Sivakumar, a fellow and director of lithography at Intel. The possible applications for DSA include contact holes, vias, and the back-end-of-the-line (BEOL) flow, he said.

Intel is conducting its DSA R&D at IMEC. Last year, IMEC set up a 300mm DSA R&D line, which consists of TEL’s track systems. Using the University of Wisconsin flow, Intel devised a three-layer, 28nm stack. The stack includes an interconnect, via and a metal 1 layer.

Intel started with staggered contact hole arrays on a grid at 50nm to 55nm. After the pattern transfer process, the holes were reduced to 26nm to 22nm, representing a 35% shrink. With a blended DSA formula from JSR, Intel obtained the targeted resolutions with good results, said Todd Younkin, a lithography materials researcher at Intel. However, the results were less conclusive with traditional block copolymers, which are provided by both AZ Electronic Materials and Dow.

Another R&D organization, CEA-Leti, last year set up a 300mm DSA pilot line, which uses Sokudo’s track systems. Using PS-b-PMMA from Arkema and a graphoepitaxy process flow, CEA-Leti achieved resolutions from 35nm to 10nm, said Raluca Tiron, a senior scientist at CEA-Leti. “We showed good uniformity with three sigma around 2nm,” she said. “After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts.”

PS-b-PMMA is expected to hit the wall at 10nm, meaning the industry must develop next-generation high chi DSA materials. Others see it differently. “We think we can extend PS-b-PMMA down to the 7nm node,” said Laurent Pain, lithography lab manager at CEA-Leti.

Another player, IBM, is involved in several different DSA efforts. In one effort, IBM demonstrated a larger-pitch 42nm flow, which could one day enable the development of smaller chips based on SOI. In this experiment, IBM used both the Almaden and University of Wisconsin flows, which enabled 42nm and 28nm resolutions. “If we can do self-assembly at 42nm, we can do assembly at smaller pitches,” said Chi-Chun Liu, a research staff member at IBM.

By Mark LaPedus
Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning.

Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition. As before, with perhaps a slightly different twist, the candidates are EUV, multi-beam and the old standby, 193nm immersion with multiple patterning.

The same candidates also are competing for next-generation DRAM and NAND production. Nanoimprint is vying for a spot in NAND. But another option, directed self-assembly (DSA), could change the entire landscape if chipmakers can bring the technology from the lab to the fab.

Based on the delays with EUV, chipmakers could end up using 193nm with multiple patterning at 7nm. But they also are shuddering at the thought, as the costs and complexities for multiple patterning are enormous.

At 7nm, IC makers would prefer to use EUV or maskless for the critical or cut layers. But after a series of ongoing delays with these next-generation lithography (NGL) candidates, lithographers clearly are frustrated and beginning to run out of patience. “I am not happy with the progress of EUV,” said Burn Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). “I am also not happy with the progress of maskless, but it is making progress.”

Lin, considered the father of immersion lithography, is the industry’s biggest proponent for multi-beam e-beam. In addition, TSMC has installed an EUV scanner and recently invested in ASML to jumpstart technology. Intel and Samsung also have invested in ASML.

EUV or bust?
For now, chipmakers hope to put EUV in pilot production at the 10nm logic and next-generation memory nodes. At 7nm, EUV remains the leading NGL candidate, with maskless running a distant second. TSMC still has EUV and maskless running neck-and-neck, although both technologies could be used in production for different applications.

To date, the progress with EUV is mixed. ASML Holding’s production-worthy EUV scanner, the NXE:3300B, is ready to roll. The scanner has a numerical aperture (NA) of 0.33 and a resolution of 22nm (half-pitch). ASML plans to ship the first NXE:3300B in the second quarter of 2013, but the throughputs are far less than previously advertised.

The throughput issues are due to the source, which is being developed by Cymer. The development of the EUV source has been “more difficult than what we anticipated,” said David Brandt, senior director of EUV marketing and business development at Cymer, which recently was acquired by ASML.

Last year, Cymer promised to ship a 100 Watt source by the end of 2012. So far, in the lab, Cymer has demonstrated the ability to generate 40 Watts and 50 Watts of EUV power. A 55 Watt source translates to an EUV throughput of 43 wafers an hour.

Cymer’s EUV source is based on laser-produced plasma (LPP) technology. In LPP, plasma is generated by a laser pulse hitting a target. The source also makes use of a pre-pulse laser and a master-oscillator power amplifier (MOPA), which will help generate more EUV power.

By the end of 2013, Cymer hopes to ship an 80 Watt source with a MOPA upgrade, enabling an EUV throughput of 58 wafers per hour. By 2015, ASML hopes to ship an EUV scanner with a 250 Watt source, which translates to a throughput of 126 wafers an hour.

Two other vendors, Gigaphoton and Xtreme, are racing against Cymer to deliver a 250 Watt EUV source. So far, Gigaphoton has achieved an EUV light output equivalent to a maximum of 20 Watts, said Yuji Minegishi, manager of the sales division for the company.

By 2015 or so, the IC industry is expected to be at the 10nm node. EUV is a 13.5nm wavelength technology, meaning chipmakers must use multiple pattering with EUV. With self-aligned double patterning (SADP), ASML’s NXE:3300B has demonstrated resolutions down to 9nm.

But if EUV is used in conjunction with double patterning, the EUV scanner itself will require twice the source power than before—or about 500 Watts, contends TSMC’s Lin. However, to deal with the resists, Yan Borodovsky, a senior fellow and director of advanced lithography at Intel, recently said that EUV source power needs to be in the range of 1,000 Watts.

Another way to extend EUV is by moving to higher NAs. For example, with an NA of 0.45, an EUV scanner can print 9.5nm feature sizes, but the image contrast drops, according to Zeiss. To address that problem, the current 4X magnification scheme can be increased to 6X or 8X.

Current EUV scanners with 4X magnification support standard 6-inch photomasks. A 0.45 NA lens with 6X magnification may improve EUV resolutions, but in some cases, that solution may require the photomask industry to move to a new and larger 9-inch mask size. In other words, photomask tool makers must develop new equipment.

“I don’t think we should give up on 4X just yet,” said Harry Levinson, senior fellow and manager of strategic lithography technology at GlobalFoundries, at the recent SPIE conference. “We may be able to extend 4X a bit. Maybe for a later node, we can go for more of these radical changes, such as larger format masks and higher lens reductions.”

Still, Levinson urged the industry to explore the idea of moving toward 9-inch masks, a move that is less painful than some might think. To support 9-inch reticles, the optics and other critical parts of a photomask tool will not need to be re-engineered, but vendors will need to develop new handling systems, he said.

In another scenario, EUV with 8X magnification could support 6-inch masks, but scanning would be done in a smaller field size. “You put this all together and we get less than half the throughput at 8X than 4X,” he said. “This is not an attractive situation.”

Beam me up
Amazingly, multi-beam e-beam or maskless lithography has seen more delays than EUV. Summarizing the state of multi-beam, Serge Tedesco, lithography program manager at CEA-Leti, said: “It’s a shame. There is a lack of support from the industry, when you compare it to the EUV side. This is one of the reasons why the technology is not mature yet.”

In 2002, for example, Mapper Lithography claimed that within three years it would ship its 13,000-beam tool for the 45nm node. As it turned out, Mapper’s initial production tool, which only will consist of 1,300 beams, won’t ship until the end of 2013.

Two other vendors, KLA-Tencor and Multibeam, are separately developing multi-beam tools. In another major move, Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies.

In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena.

In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology. It also is working on a multi-beam tool based on a variant of VSB called multi-shape beam (MSB), said Ines Stolberg, manager of strategic marketing at Vistec Electron Beam.

Given that MSB is based on proven VSB technology, Vistec Electron Beam may have an advantage over rival multi-beam approaches, said Hans Pfeiffer, principal of HCP Consulting. “This has a greater chance for success,” Pfeiffer said.

Multi-beam’s future still remains unclear, as only two entities, CEA-Leti and TSMC, are basically propping up and supporting the entire industry. CEA-Leti recently launched the Imagine Program, a multinational consortium aimed to bring maskless into production.

TSMC is working with both KLA-Tencor and Mapper. For years, KLA-Tencor has been developing what it calls Reflective Electron Beam Lithography (REBL). REBL makes use of a six-wafer rotary stage and a linear column. The 75-100-KeV design also consists of a CMOS-based digital pattern generator module, a 4,096 x 247 pixel array unit that enables more than 1 million beams at full current.

When operating with the rotary stage, REBL has demonstrated the ability to print 120nm half-pitch resolutions, a modest effort at best. In a static mode, the tool demonstrated 28nm resolutions, said Thomas Gubiotti of KLA-Tencor. A high-throughput version of REBL is due out in 2015.

Rival Mapper is developing a multi-beam tool, which is supposed to consist of 13,260 beams with sub-25nm resolutions. However, the first production tool, dubbed the Matrix 1.1, will consist of only 1,300 beams and a throughput of 1 wafer an hour, according to CEA-Leti. In June, CEA-Leti is expected to receive one of the first Matrix 1.1 tools. First exposures for the Matrix 1.1 are slated for the fourth quarter of 2013.

By 2015 or 2016, the overall goal is to cluster 10 Matrix systems together, enabling an overall throughput of 100 wafers an hour. In terms of the cost-of-ownership (COO), the Matrix runs €1 million for a system with a throughput of 2 wafers per hours, €5 million for 10 wafers an hour, and $50 million euros for a 10-cluster unit.

Self-Assembled Sponges
Using a novel self-assembly approach, the Johannes Gutenberg University Mainz and the Max Planck Institute for Polymer Research have created a new flexible mineral inspired by deep-sea sponges. The technology could one day enable futuristic body armor.

Researchers recreated sponge spicules using calcium carbonate and a protein of a sponge. Spicules are tiny spike-like structures found in many organisms. They deter predators because they are hard, sharp and prickly.

The nanometer size of the calcite bricks facilitates bending of the synthetic spicules. The radius of curvature upon bending is very large compared to the size of the individual particles. This prevents a fracture of the brittle mineral bricks. Source: University Mainz

Researchers devised synthetic spicules using silicatein-α, which is responsible for the biomineralization of silicates in sponges. Researchers used silicatein-α to guide the self-assembly of calcite spicules, which are similar to the spicules of a calcareous sponge.

The self-assembled spicules, 10 to 300 um in length and 5 to 10 μm in diameter, are composed of aligned calcite nanocrystals. The spicules are initially amorphous, but transform into calcite within months.

The synthetic spicules are elastic. This feature is linked to a high protein content. With nano-thermogravimetric analysis, researchers measured the organic content of a single spicule to be 10% to 16%. In addition, the spicules exhibit wave-guiding properties even when they are bent.

Phase-Change DSA
Since the 1960s, the industry has been trying to commercialize phase change memory (PCM). Sometimes called PCRAMs, PCM exploits the phase change behavior of chalcogenide materials. In theory, PCRAMs are a possible replacement for today’s solid-state memory devices.

Micron Technology and Samsung Electronics have recently shipped low-density PCM devices for limited applications. But in general, PCM is difficult to scale and expensive to manufacture.

Power consumption is another problem with PCM. The Korea Advanced Institute of Science and Technology (KAIST) has developed PCM technology at a power-consumption level below 1/20th of its present level. To accomplish this feat, KAIST has devised a novel approach using directed self-assembly (DSA).

Researchers used a block copolymer to form a thin nanostructured SiOx layer, which locally blocks the contact between a heater electrode and a phase change material. Using this approach, the writing current is decreased fivefold, as the occupying area fraction of SiOx nanostructures is increased from a fill factor of 9.1% to 63.6%.

Using DSA, researchers were able to reduce power faster than expected. “This is a very good example that self-assembled, bottom-up nanotechnology can actually enhance the performance of electronic devices. We also achieved a significant power reduction through a simple process that is compatible with conventional device structures and existing lithography tools,” said Keun-Jae Lee, a professor of KAIST, on Nanowerk’s Web site.

Dirty CD-SEMs
The scanning electron microscope (CD-SEM) has been used in the fab for decades as a means to measure the critical dimensions of complex structures.

Some believe the CD-SEM will soon run out of steam. One of the problems with the CD-SEM is contamination, which could become a showstopper for measurements at the nanometer scale.

The National Institute of Standards and Technology (NIST) is looking to prolong the life of the CD-SEM, by developing cleaning and other improvements to the existing technology.

Charged particle beam-induced contamination in the SEM is the issue. There is a buildup of carbonaceous material on the surface of the sample, where the ions or electrons are focused. This, in turn, results in characteristic dark patterns, making repeatable quantitative measurements difficult or impossible.

In the 1990s, NIST tested a prototype low-energy (20 Watt) plasma unit. The system, designed by XEI Scientific, was able to clean the CD-SEM by flooding it with oxygen plasma. Later, NIST collaborated with the IBSS Group to develop a modified plasma-cleaning device. That device works in a wider vacuum range and also has up to 99 Watts of power.

Evaporated gold-on-carbon sample imaged initially (a) and after 10 minutes of continuous imaging at twice as high magnification (b) showing excessive amount of electron beam-induced contamination. The same sample after hydrogen plasma cleaning and 10 minutes of continuous imaging at twice as high magnification (c), now without the detrimental effect of contamination. Source: NIST

New research indicates that the electron bombardment itself during extended measurements can act as a cleaning process for a variety of samples. With the research, NIST and others devised the so-called Contamination Specification. These are steps that SEM users can take to determine whether their instruments need to be cleaned and how to implement an effective cleaning process.

“We know how to get the instruments clean, and we know how to clean the samples,” said András Vladár of the Semiconductor and Dimensional Metrology Division (SDMD), on NIST’s Web site. “We learned that when you clean it, the instrument can remain contamination free for months unless a dirty sample is used.”

—Mark LaPedus

High-Tech PR Insights
A new study from the University of Wisconsin-Madison has provided some key insights into the field of hi-tech public relations.

The way a scientific breakthrough is presented can change how a technology is perceived among the general public, according to the study. Participants in the study were given one of three definitions regarding the same technical breakthrough.

One definition highlighted a technology’s applications. The second focused on the risks and benefits. And the third involved both applications and risks and benefits.

The results were mixed. If the definition was highlighted, the participants would support the technology, “but they weren’t motivated to gather more information,” according to the University of Wisconsin-Madison. Meanwhile, if the definition focused on risks and benefits, participates wanted to learn more, but were “less likely to support nanotechnology,” according to the researchers.

“Explaining nanotechnology in terms of applications promotes acceptance, but motivation to learn more is triggered by mentioning potential risks,” said Dietram Scheufele, UW-Madison professor of life sciences communication, on the university’s Web site.

On the site, Ashley Anderson, a research fellow in the Center for Climate Change Communication at George Mason University, added: “This has important implications for those interested in engaging members of the public in scientific issues.”

Molecular DSA For Mobile Apps
The National University of Singapore and the Tyndall National Institute at the University College Cork have developed a molecular and self-assembly technology that could boost the energy efficiency in smart phones and tablets.

Researchers have devised tiny devices using molecules, which do not overheat while showing good electrical properties. By altering just one carbon atom of an active molecular component, the devices provide a tenfold improvement in switching efficiency.

Redox active ferrocenealkanethiol molecules pack together and assemble into monolayer thin films on silver electrodes. Molecules standing tall instead of crouching form tighter assemblies, which dramatically improve the device properties. Source: NUS

For years, researchers have been looking to tap the potential of organic and molecular electronics. The challenge is that organic and molecular electronic devices are complex. They generally consist of at least two electrodes, an organic component and two different organic/inorganic interfaces, according to researchers.

Isolating each structure has also been a challenge. Researchers have considered the idea of using “strong π–π interactions” for organic electronic devices.

Using a different approach, the National University of Singapore and Tyndall showed that changes in the “intermolecular van der Waals interactions” in the active component of a molecular diode impacts the performance of the device. In chemistry, the van der Waals force is named after Dutch scientist Johannes Diderik van der Waals. The concept involves the sum of the attractive or repulsive forces between molecules.

Researchers discovered an odd–even effect as the number of alkyl units is varied in a ferrocene–alkanethiolate self-assembled monolayer. Consequently, junctions made from an odd number of alkyl units have a lower packing energy and rectify currents 10 times more efficiently, according to researchers.

This, in turn, gives a 10% higher yield in working devices. What’s more, the molecules can be made two to three times more often than junctions made from an even number of alkyl units, according to researchers.

Balloon Lithography
Helium-ion microscopes were once targeted to replace traditional scanning-electron microscopes (CD-SEMs) for semiconductor metrology applications. Helium-ion microscopy never lived up to those promises, but the technology has found a new application in nanofabrication.

Quadruple quantum dots patterned on bilayer graphene using He-ion-beam milling. Source: SPIE

The University of Southampton and the Japan Advanced Institute of Science and Technology have demonstrated that helium-ion microscopy can be used to sputter and pattern graphene structures. In turn, the technology can be used to create tiny nanoscale designs on graphene.

In the lab, researchers first used an traditional electron-beam tool to pattern metal contacts on graphene flakes. Then, in a milling process, they used a helium-ion microscope to pattern structures. The tool patterned structures like nanoribbons and quantum dots on graphene.

With the process, researchers patterned quadruple quantum dots on bilayer graphene at 5nm feature sizes. Researchers cla
im that the process could enable devices with an accuracy of 1nm with good yields.

—Mark LaPedus