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What is Your China Strategy?

Wednesday, September 7th, 2016

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By Dave Lammers, Contributing Editor

Equipment vendors have a lot on their plates now, with memory customers pushing 3D NAND, foundries advancing to the 7 nm node, and 200mm fabs clamoring to come up with hard-to-find tools.

China, which has renewed its investments in displays, packaging, and both 200mm and 300mm front-end fab capacity, is another challenge.

“All the managers in my company are scrambling to adjust their budgets so they can support China. I can tell you people are booking lots of flights to Shanghai,” said one engineer at a major equipment supplier.

Bill McClean, president of IC Insights (Scottsdale, AZ), said China is fast becoming a center for 3D NAND production, as several companies expand production in China. Intel is converting its Dalian, China fab partly to 3D NAND, and Toshiba might very well make a deal in China to build a 3D NAND fab there, he said.

“China could be the 3D NAND capital of the world,” McClean said at The ConFab conference in Las Vegas. While the U.S. government limits exports of leading-edge technologies on national security concerns, 3D NAND relies more on overlay and etch techniques at relaxed (40nm) design rules, he noted.

“Since the 3D NAND makers are not pushing feature sizes, it doesn’t raise red flags like if Chinese companies wanted FinFET technology. That is when the alarms go off,” McClean said.

However, McClean said the 3D NAND market is not immune to the oversupply issues that now face the DRAM makers. “I’ve seen this rodeo before,” McClean said.

China’s domestic IC market is slightly more than $100 billion, McClean said, while chip production in China was about $13 billion last year, representing just under 5 percent of worldwide production (Figure 1).

Figure 1. Source: IC Insights.

The difference between consumption and domestic production, referred to as the delta, is made up by imports. “This 13 percent (from domestic suppliers) drives the Chinese government crazy. Yes, they will close that gap a little bit, but not to the extent that they think,” McClean told The ConFab audience in mid-June.

Robert Maire, who consulted for SMIC on its initial public offering in the United States, spoke at length about China at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, N.Y. Amid the mergers and acquisition frenzy of last year, China managed to pull off the acquisitions of CMOS image sensor vendor Omnivision, memory maker ISSI, the RF business of NXP, Pericom Semiconductor, and Mattson Technology. (McClean said he believes that if the Omnivision acquisition were attempted in today’s more China-wary environment that Washington would block the deal).

Maire, principal at Semiconductor Advisors (New York), said China is far behind in its domestic semiconductor production equipment business. “If China has 14nm production capacity, but buys all of its equipment from abroad, it doesn’t really help them that much. China is getting started in equipment, but it has a lot of catching up to do.”

Scott Foster, a partner in market intelligence firm TAP Japan (Tokyo), said China must have an international scope in the equipment sector if it hopes to compete with the likes of Applied, Lam, and other well-established vendors. A few of Japan’s equipment suppliers are succeeding while operating in relatively narrow niches, but overall, competing globally is a challenge for mid-sized Japanese equipment companies. “If this is what is happening to Japanese equipment vendors, what chance do Chinese companies have?” Foster said.

Packaging may prove to be key

Skeptics of China’s prospects might take a long look at China’s success in packaging, an area where China is succeeding, in part by acquisitions of Asia-based companies, notably STATS ChipPAC (Singapore), which was acquired by Jiangsu Changjiang Electronics Technology Co. (JCET) last year. Separately, SMIC and JCET formed a joint venture to focus on chip scale packaging, wafer bumping, and fan-out wafer level packaging. The packaging joint venture is located 90 minutes from Shanghai, said Sonny Hui, senior vice president of worldwide marketing at SMIC.

Jim Walker, the packaging analyst at market research firm Gartner, said China-based packaging is now valued at nearly half (43 percent) of all worldwide packaging value by IDMs and OSATs. While the packaging industry overall is dealing with price pressures, the advent of wafer level packaging, and other forms of multi-chip integration, bodes well for the higher end of the back-end industry.

“As the semiconductor industry matures and Moore’s Law scaling slows, multi-chip integration via packaging is providing system vendors with a faster time-to-market, and a lower-cost means, of solving system-level challenges,” Walker said.

Packaging multiple chips in a module is likely to play a key role in the Internet of Things (IoT) markets, Walker said. Automotive, medical, home, and consumer solutions are all “heavily reliant on packaging,” he said.

Sam Wang, a Gartner analyst who focuses on foundries, pointed out at Semicon West that China’s semiconductor industry faces continued challenges in a hotly contested foundry market. Few China-based foundries have enjoyed the strong growth that SMIC has demonstrated, he said. (SMIC has been “running at very high utilizations, and we are working very hard to solve the problem,” said SMIC’s Hui.)

While SMIC has enjoyed double-digit growth for several years, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total worldwide foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

China-based companies are focusing partly on MEMS and other devices made on 200mm wafers, including analog, sensors, and power. SMIC’s Hui said “most of our customers don’t see much benefit to migrate to 12-inch. 200mm still has a lot of potential; just consider the hundreds of products still made on 180nm technology, which was developed 20 years ago. Many customers still see that as a sweet spot.”

Foster, who has three decades of tech-watching experience from his base in Tokyo, said the 200mm wafer fabs being built in China will make products that “do not need the gigantic scale” required of Intel, TSMC, Samsung and Toshiba. Figure 2, courtesy of SEMI, shows the seventeen 200mm wafer fabs/lines that are expected begin operation in 2015 to 2019. Six of the seventeen will be in China.

Figure 2. Source: SEMI

“After decades of trying, China has found a market-based strategy: building scale and experience from the bottom up. In the long run, this is likely to be far more effective than going out to buy foreign companies,” Foster said.

Display is another area China is counting on. In an Aug. 18 conference call following a strong quarter, Applied Materials chief financial officer Bob Halliday told analysts: “In display, we recorded record orders of $803 million with more than half coming from projects in China.”

The Applied CFO also said, “Just listening to the Chinese government, they’re in this for a long-term and their interest in investing in the semiconductor industry is probably only going to increase.”

Kateeva turns to China funds

China is often lumped together with other Asian nations as a country that has a government-led, me-too, follower mentality. But increasingly, China is either proving innovative itself, or able to quickly adopt innovations from the West.

At the Innovation Forum at Semicon West, Conor Madigan, co-founder of ink jet printer startup Kateeva (Newark, Calif.) spoke about the readiness of Chinese venture capital funds to step in where Silicon Valley-based VCs were overly hesitant. China proved a more receptive place to raise money than the United States, though the early establishment of the M.I.T. spinout did come from U.S. based sources.

After its initial development effort, Kateeva figured it needed more than $100 million to accomplish its goals. After making the rounds to raise funds in the United States without success, Kateeva turned to China, where five different funds eventually became investors.

Asked why Chinese investors were willing to back Kateeva when funds in the United States and other Asian countries were reluctant, Madigan pointed to a confluence of factors.

The Chinese government had identified OLED displays as a focus of its Five Year Plan. The follow-on economic plan further identified inkjet technology as a critical technology. Investors in China favor companies which can provide the equipment for products, such as OLEDs, which have the government’s blessing and financial support. That government support reduced the investment risks in ways that are not readily seen in Japan or the United States, he said.

Madigan had studied OLEDs as an undergraduate at Princeton University, and then studied under an M.I.T. professor who had developed ink jet technology for large formats.

Though an early goal was to use large-format inkjet to deposit the RGB materials in OLEDs, the Kateeva team learned that its YieldJet system could be adapted to solve a more urgent problem: thin film encapsulation (TFE). It “pivoted” on the advice of an early customer, which fortunately already had developed the “ink” which under UV light would form a uniform encapsulation layer for the large OLED substrates required for TVs and other large display applications.

Two display companies in China identified Kateeva as a strategic partner, which allowed Kateeva to raise money from private Chinese VC funds, rather than taking money from regional government funds which might have asked Kateeva to locate its manufacturing operations in their local area.

Madigan also pointed to the tendency of U.S.-based venture capital funds to favor software companies over manufacturing-focused opportunities. As VCs make money in software-related startups, the funds gradually have more partners and investors which favor software because that is what they are familiar with.

VC fund managers with backgrounds in software “want to invest in the space that they understand. In the United States, that often means software, because you pick companies in the space that you understand.”

Conference Features “The Year of Stacked Memory” in 2015

Thursday, December 17th, 2015

By Jeff Dorsch, Contributing Editor

The theme of this year’s 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is “The Year of Stacked Memory,” noting how memory die stacked in one package are becoming more commonplace in 2015.

Put on by RTI International, the 3D ASIP conference is in its 12th year. Attendees and presenters are generally people involved in chip packaging, from academia and industry.

One presentation on Wednesday (December 16) was by Teruo Hirayama of Sony, which has a long history of developing CMOS image sensors, dating back to 1998 with the graphics synthesizer for the PlayStation 2 video-game console, employing embedded DRAMs.

Embedded DRAMs present a number of manufacturing challenges, such as requiring four photomasks at the time, compared with three masks for commodity DRAMs and two or so masks for “pure logic” chips, Hirayama noted.

To address the issue, Sony turned to “chip-on-chip” technology, combining the merits of system-on-a-chip devices and system-in-package technology, according to Hirayama. The chipmaker later resorted to stacked CMOS image sensors, which offer a cost advantage over conventional CMOS image sensors.

During fiscal 2014, stacked CMOS image sensors accounted for 64 percent of Sony’s CMOS image sensor shipments, with back-illuminated image sensors representing 31 percent and front-illuminated image sensors 5 percent, Hirayama reported.

For future directions in stacked image sensors, Hirayama pointed to connecting pixels to analog-to-digital converters, with a device that has memory, a microelectromechanical system device, and a radio-frequency chip on the bottom layer, topped with a logic device, the ADC, and pixels, in that order.

The conference also heard Wednesday from Bryan Black of Advanced Micro Devices, a senior AMD fellow who spearheaded development of the company’s Fiji graphics processing unit.

The project started in 2007 and took 8.5 years to complete, Black said. “The industry needed a new memory system,” he commented. “We ended up with a die-stacking solution.”

Virtual prototyping was employed along the way, according to Black.

With a silicon interposer measuring 1,011 square millimeters and an ASIC coming in at 592 square millimeters, with four high-bandwidth memories, the Fiji GPU module is a big device. “We realized the part was going to be much bigger than we expected,” Black recalled. “Then we realized this thing would be huge.”

Wrapping up on Wednesday, the conference also heard presentations by three suppliers of semiconductor production equipment – EV GroupSPTS Technologies, and Rudolph Technologies.

SEMICON Show Highlights Chip Manufacturing in South Korea

Wednesday, February 4th, 2015

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By Jeff Dorsch

The SEMICON Korea conference and exhibition opens Wednesday in Seoul for a three-day run. The show highlights the importance of semiconductor manufacturing in South Korea, home to two of the biggest memory chip makers in the world, Samsung Electronics and SK Hynix.

The DRAM market in 2014 posted a 34.7 percent increase in revenue, compared with 2013, as the total memory chip market grew 18.2 percent last year to $79.2 billion, according to World Semiconductor Trade Statistics. Samsung and Hynix together account for about two-thirds of the worldwide DRAM market, and South Korea holds 40 percent of the global memory output.

Semiconductor Equipment and Materials International forecasts Korean expenditures on front-end wafer fabrication equipment will be $7.8 billion in 2015, nearly 28 percent higher than 2014. Korean chipmakers will spend more than $14 billion on semiconductor equipment and materials this year, according to SEMI.

IC Insights estimates Samsung grew its semiconductor sales by 8 percent in 2014 to $37.26 billion, while Hynix boasted 22 percent growth to $15.84 billion, compared with the year before.

Samsung and Hynix (once the semiconductor arm of the Hyundai chaebol and now part of the SK Group) dominate the semiconductor scene in their home country, yet they aren’t the only chipmakers in South Korea. Dongbu HiTek is a specialty silicon foundry, emphasizing analog and mixed-signal chip fabrication. Its parent conglomerate, the Dongbu Group, has been seeking to sell its 37 percent ownership in the foundry for more than a year, without success. Samsung and Hynix haven’t been interested in Dongbu HiTek, although Samsung has a substantial foundry business, making chips for Apple and other customers. The LG Group at one point expressed interest in bidding for the Dongbu HiTek stake, but hasn’t advanced that interest.

There’s also MagnaChip Semiconductor, which designs and manufactures analog and mixed-signal chips for consumer applications. The company also provides foundry services.

SEMICON Korea is co-located with the LED Korea 2015 exhibition, featuring light-emitting diode manufacturing.

Applied Materials Introduces New Hardmask Process, Saphira

Monday, November 24th, 2014

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A new hardmask material and process was introduced this month by Applied Materials. Designed for advanced logic and memories, including DRAM and vertical NAND, the hardmask is transparent, which simplifies processing. It also exhibits very high selectivity, low stress and good mechanical strength. It’s also ashable, so that it can be removed after etching is completed. Called Saphira, the process was developed in conjunction with Samsung and other customers. An Applied Materials-developed process for stripping the hardmask was licensed to Korea-based PSK.

Hardmasks are used for etching deep, high aspect ratio (HAR) features that conventional photoresists cannot withstand. Applied Materials first introduced an amorphous carbon hardmask in 2006, and now has a family of specialized films. The Advanced Patterning Films (APF) family now includes APFe, which enables deposition of thicker layers than APF (e.g., in capacitor formation and metal contacts for memory devices), and APFx, design to address patterning of metal lines and contacts at 5xnm and beyond.

The new Saphira APF process – which runs on the Applied Materials Producer XP Precision CVD chamber and works with PSK’s OMNIS Asher systems — introduces new film properties that include greater selectivity and transparency. The Saphira APF deposition and resolve major issues to improve patterning of more complex device structures at advanced technology nodes. “It’s a materials solutions,” said Terry Lee, vice president of strategy and marketing for the dielectrics systems and modules group at Applied Materials. “It’s delivered with the patterning film itself, Saphira, as well as the combination of technologies and processes, whether it’s in the CVD chamber or etch chamber, reducing process steps and simplifying process complexity.

Applied Materials isn’t saying exactly what the Saphira hardmask is composed of, but a recent patent filing describes it as boron-rich amorphous carbon layer. The patent notes that, compared to carbonaceous masking layers, boron-doped carbonaceous layers, which include between 1 wt. % and 40 wt. % boron provide even greater etch resistance.

Lee said the Saphira film “In general behaves very much like a ceramic. But unlike most ceramics, it’s ashable. It’s structurally hard like a ceramic, but it’s ashable like our standard carbon hard mask,” he said.

In general, the selectivity of Saphira is twice the conventional masking materials on the open market, Lee said.

The new process reduces process complexity and cost in a couple of different ways. Because it’s transparent, no extra step is needed to open the mask to find the alignment mark. And because the film has high selectivity, fewer masking steps are required. That all reduces the process complexity. Lee said that with conventional masks, in order to mask these high aspect ratio features, a thicker mask material is often needed. “When you have a thicker mask and you need to etch fine features, what you wind up with is a very narrow mask. In order to prevent the mask itself from collapsing or titling, you need very strong mechanical strength. With Saphira, we have that high mechanical strength and it resists the deformation,” he said.

Saphira can also reduce the need for multiple hardmasks. “Instead of having the hardmask, oxide and poly (see figure), it drops down to a one mask that’s thinner because the selectivity is higher,” Lee explained. “What we’re seeing is that we can reduce around 20 steps. When you reduce steps, you reduce cost. What we’re seeing based on our calculations is something like 35% reduction in cost of this one module. Across multiple modules, that adds up to a lot of money,” he added.

The Week in Review: September 19, 2014

Friday, September 19th, 2014

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

North America-based manufacturers of semiconductor equipment posted $1.35 billion in orders worldwide in August 2014 (three-month average basis) and a book-to-bill ratio of 1.04, according to the August EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

Samsung Electronics announced this week that it has begun mass producing its six gigabit (Gb) low-power double data rate 3 (LPDDR3) mobile DRAM, based on advanced 20 nanometer (nm) process technology. The new mobile memory chip will enable longer battery run-time and faster application loading on large screen mobile devices with higher resolution.

ProPlus Design Solutions, Inc. announced this week it expanded its sales operations to Europe.

Mentor Graphics this week announced the appointment of Glenn Perry to the role of vice president of the company’s Embedded Systems Division. The Mentor Graphics Embedded Systems Division enables embedded development for a variety of applications including automotive, industrial, smart energy, medical devices, and consumer electronics.

3D memory for future nanoelectronic systems

Wednesday, June 18th, 2014

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By Ed Korczynski, Sr. Technical Editor

The future of 3D memory will be in application-specific packages and systems. That is how innovation continues when simple 2D scaling reaches atomic-limits, and deep work on applications is now part of what global research and development (R&D) consortium Imec does. Imec is now 30 years old, and the annual Imec Technology Forum held in the first week of June in Brussels, Belgium included fun birthday celebrations and very serious discussions of the detailed R&D needed to push nanoelectronics systems into health-care, energy, and communications markets.

3D memory will generally cost more than 2D memory, so generally a system must demand high speed or small size to mandate 3D. Communications devices and cloud servers need high speed memory. Mobile and portable personalized health monitors need low power memory. In most cases, the optimum solution does not necessarily need more bits, but perhaps faster bits or more reliable bits. This is why the Hybrid Memory Cube (HMC) provides >160Gb/sec data transfer with Through-Silicon Vias (TSV) through 3D stacked DRAM layers.

“We’re not adding 70-80% more bits like we used to per generation, or even the 40% recently,” explained Mark Durcan, chief executive officer of Micron Technology. “DRAM bits will only grow at the low to mid-20%.” With those numbers come hopes of more stability and less volatility in the DRAM business. Likewise, despite the bit growth rates of the recent past, NAND is moving to 30-40%  bit-increase per new ‘generation.’

“Moore’s Law is not over, it’s just slowing,” declared Durcan. “With NAND, we’re moving from planar to 3D, and the innovation is that there are different ways of doing 3D.” Figure 1 shows the six different options that Micron defines for 3D NAND. Micron plans for future success in the memory business to be not just about bit-growth, but about application-specific memory solutions.

Fig. 1: Different options for Vertical NAND (VNAND) Flash memory design, showing cell layouts and key specifications. (Source: Micron Technology)

E. S. Jung, executive vice president Samsung Electronics, presented an overview of how “Samsung’s Breaking the Limits of Semiconductor Technology for the Future” at the Imec forum. Samsung Semiconductor announced it’s first DRAM product in 1984, and has been improving it’s capabilities in design and manufacturing ever since. Samsung also sees the future of memory chips as part of application-specific systems, and suggests that all of the innovation in end-products we envision for the future cannot occur without semiconductor memory.

Samsung’s world leading 3D vertical-NAND (VNAND) chips are based on simultaneous innovation in three different aspects of materials and design:

1)    Material changed from floating-gate,

2)    Rotated structure from horizontal to vertical (and use Gate All Around), and

3)    Stacked layers.

To accomplish these results, partners were needed from OEM and specialty-materials suppliers during the R&D of the special new hard-mask process needed to be able to form 2.5B vias with extremely high aspect-ratios.

Rick Gottscho, executive vice president of the global products group Lam Research Corp., in an exclusive interview with SST/SemiMD, explained that with proper control of hardmask deposition and etch processes the inherent line-edge-roughness (LER) of photoresist (PR) can be reduced. This sort of integrated process module can be developed independently by an OEM like Lam Research, but proving it in a device structure with other complex materials interactions requires collaboration with other leading researchers, and so Lam Research is now part of a new ‘Supplier Hub’ relationship at Imec.

Luc Van den hove, president and chief executive officer of Imec, commented, “we have been working with equipment and materials suppliers form the beginning, but we’re upgrading into this new ‘Supplier Hub.’ In the past most of the development occurred at the suppliers’ facilities and then results moved to Imec. Last year we announced a new joint ‘patterning center’ with ASML, and they’re transferring about one hundred people from Leuven. Today we announced a major collaboration with Lam Research. This is not a new relationship, since we’ve been working with Lam for over 20 years, but we’re stepping it up to a new level.”

Commitment, competence, and compromise are all vital to functional collaboration according to Aart J. de Geus, chairman and co-chief executive officer of Synopsys. Since he has long lead a major electronic design automation (EDA) company, de Geus has seen electronics industry trends over the 30 years that Imec has been running. Today’s advanced systems designs require coordination among many different players within the electronics industry ecosystem (Figure 2), with EDA and manufacturing R&D holding the center of innovation.

Fig. 2: Semiconductor manufacturing and design drive technology innovation throughout the global electronics industry. (Source: Synopsys)

“The complexity of what is being built is so high that the guarantee that what has been built will work is a challenge,” cautioned de Geus. Complexity in systems is a multiplicative function of the number of components, not a simple summation. Consequently, design verification is the greatest challenge for complex System-on-Chips (SoC). Faster simulation has always been the way to speed up verification, and future hardware and software need co-optimization. “How do you debug this, because that is 70% of the design time today when working with SoCs containing re-used IP? This will be one of the limiters in terms of product schedules,” advised de Geus.

Whether HMC stacks of DRAM, VNAND, or newer memory technologies such as spintronics or Resistive RAM (RRAM), nanoscale electronic systems will use 3D memories to reduce volume and signal delays. “Today we’re investigating all of the technologies needed to advance IC manufacturing below 10nm,” said Van den hove. The future of 3D memories will be complex, but industry R&D collaboration is preparing the foundation to be able to build such complex structures.

DISCLAIMER:  Ed Korczynski has or had a consulting relationship with Lam Research.

3D NAND: To 10nm and beyond

Wednesday, January 29th, 2014

By Sara Ver-Bruggen, contributing editor

In launching the iPod music player, Apple bumped consumption of NAND flash – a type of non-volatile storage device – driving down cost and paving the way for the growth of the memory technology into what is now a multibillion dollar market, supplying cost-effective storage for smart phones, tablets and other consumer electronic gadgets that do not have high density requirements.

The current iteration of NAND flash technology, 2D – or planar – NAND, is reaching its limits. In August 2013, South Korean consumer electronics brand Samsung announced the launch of its 3D NAND storage technology, in the form of a 24-layer, 128 GB chip. In 2014, memory chipmakers Micron and also SK Hynix will follow suit, heralding the arrival of a much-anticipated and debated technology during various industry conferences in recent years. Other companies, including Sandisk, are all working on 3D NAND flash technology.

Like floors in a tower block, in 3D NAND devices memory cells are stacked on top of each other, as opposed to being spread out on a two-dimensional (2D), horizontal grid like bungalows. Over the last few decades as 2D NAND technology has scaled, the X and Y dimensions have shrunk in order to go to each chip generation. But scaling, as process nodes dip below 20nm and on the path towards 10nm, is proving challenging as physical constraints begin to impinge on the performance of the basic memory cell design. While 2D NAND has yet to hit a wall, it is a matter of time.

Transition to mass production

But despite the potential of 3D NAND and announcements by the leading players in the industry, transferring 3D NAND technology into mass production is very challenging to do. As Jim Handy, from Objective Analysis, points out: “The entire issue of 3D NAND is its phenomenal complexity, and that is why no one has yet shipped a 3D NAND chip yet.” Mass production of Samsung’s device will happen this year. With 3D NAND there is the potential for vertical scaling, going from 16-bit-tall strings to string heights of more than 128 bits.

But while 3D NAND does not require leading-edge lithography, eventually resulting in manufacturing costs that are lower than they would be for the extension of planar NAND, new deposition and etch technologies are required for high-aspect-ratio etch processes. This “staircase” etching requires very precise contact landing. In 3D NAND manufacturing depositing layers of uniform thickness across the entire wafer presents issues with pull-back etching for these “stair steps” that currently increase the lithography load more than was originally anticipated.

Staircase etching requires very precise contact landing.

“Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic-layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer, which is also true of the layers that are deposited on the walls of the hole,” according to Handy.

Indeed, while the best combination of cost, power and performance will be found in 3D NAND architectures, there still remain issues concerning cost, especially. These issues, in the context of their respective memory technology roadmaps, were discussed by memory chipmakers, including Sandisk, SK Hynix and Micron, at a forum organized and sponsored by semiconductor industry equipment manufacturer Applied Materials in December 2013, while the equipment supplier provided some in-depth discussion on 3D NAND manufacturing considerations and challenges. The session was hosted by Gill Lee, Senior Director and Principal Member of Technical Staff Silicon Systems Group at Applied Materials.

Sandisk plays its 2D hand for as long as possible

Ritu Shrivastava, Vice President Technology Development, at Sandisk Corporation, set out the challenge. “Whenever you talk about technology, it has to be in relation to the objectives of your company. In our case we have a $38 billion total available market projected to 2016 and any technology choices that we make have to serve that market.” Examples of products he was referring to include smart phones and tablets. “Our goal is to choose technologies that are most cost-effective and deliver in terms of performance.”

Sandisk has a joint NAND fab investment with Toshiba and the two have had a 128 GB 2D NAND flash chip using 19 nm lithography in production for a while now. They have also previously announced plans to build a semiconductor fab for 16-17 nm flash memory.

”One of our goals is to extend the life of 2D NAND technologies as far as possible because it reflects the huge investment that we have made in fabs and the technology, over the number of years,” said Shrivastava. “Of course, 3D NAND is extremely important and when it becomes cost-effective then it will move into production.” Sandisk plans to start producing its 3D NAND chips in 2016.

“We are travelling in what we think is the lowest cost path in every technology generation, going from 19 nm to 1Y where we at the limit with lithography, and then we will scale to 1Z, which is our next-generation 2D NAND technology. We believe that this scaling path gives us the lowest cost structure in each of the nodes and in terms of cumulative investment.”

But it is not just achieving the smallest die size, it is the cost involved in scaling. Capital equipment investment is what determines success in the market, according to Shrivastava. “Even though we are saying that 3D NAND is a reality there are a couple of things that we need to keep in mind. It leverages existing infrastructure, which is good, but there are still a lot of challenges. 3D NAND devices use TFT as opposed to the floating gate devices commonly used in 2D NAND chips. New controller schemes and boards will be required also.”

So while, according to Shrivastava, 3D NAND is looking very promising, there is a big ‘but’ for a company such as Sandisk, which produces some of the most cost-competitive flash memory devices on the market. “2D NAND still continues to be more cost-effective than 3D NAND and 3D NAND is not yet proven in volume manufacturing. Every new technology takes some time. Getting to mass manufacturing will take time. Our goal is to extend 2D NAND as long as possible, continue to work on 3D NAND and introduce it when it becomes cost-effective.”

Shrivastava sees 2D and 3D NAND technologies co-existing for the rest of the decade. Beyond 3D NAND the company is developing a 3D resistive RAM (RRAM) as the future technology beyond 3D NAND.

From 3D DRAM to 3D NAND

Next Chuck Dennison, Senior Director Process Integration, from Micron, provided an overview of where the company is today in terms of its own NAND memory technology roadmap.

“Our current generation is 16nm NAND that is now in production and we’re showing that it is getting to be a very competitive and very cost-effective technology,” according to Dennison. Micron’s new 16nm NAND process provides the greatest number of bits per sq mm at the lowest cost of any multilayer cell (MLC) device. Eight of these die can hold 128 GB of data. The 16nm storage technology will be released on next-generation solid state drives (SSDs) during 2014. SSDs consist of interconnected flash memory chips as opposed to platters with a magnetic coating used in conventional hard disk drives (HDDs).

Micron 16nm NAND die

“Our next node is a 256 GB class of the NAND memory. Technically it could be extended before taking the full step to 3D NAND.”

Today NAND is the lowest cost-per-bit memory technology and this continued cost-per-bit reduction is really driving the whole of the NAND industry, according to Dennison. It is why NAND replaced DRAM in terms of total dollars and has continued to proliferate across various applications, and is responsible for continued innovation in portable consumer electronics, such as tablets, where so much functionality enabling photography, video recording, storage of an entire music library, and so on, can be packed into one device.

Outlining Micron’s technology scaling path, Dennison explained: “We went to high-K/metal gate to 20 nm and we used the same technology to extend us to 16nm. From there, the company is moving to a vertical channel 3D NAND for a 256 GB class.

“In terms of capital expenditure (CapEx) per wafer it all looks very cost-effective, with a little bit of transition going to 20 nm,” explained Dennison, because of the high-K metal gate, but with minimal increase going to 16nm. “But when you go to 3D NAND it is expensive, per wafer. So if you are increasing your wafer costs by X amount you need a much higher amount of GB per cm sq, so the density we are choosing to go with is a 256 GB class. And when you start actively looking at 3D NAND there are a lot similarities between 3D NAND and DRAM,” he explained, referring to the stacked capacitor of DRAM. “There is a lot planarization, you are etching very high aspect ratio contacts where you need to be very controlled, in terms of how you define your control and CD uniformity. Then there are a lot of additional modules requiring ALD deposition. So we think that there is a lot of opportunity to utilize our DRAM expertise.”

He outlined an inflection point going from 16nm, again. “We’re transitioning to go to the 256 GB density. We think that when we do this it will make financial sense and it will be a cost-effective solution despite the high Capex. And then from there we will continue. With the majority, or bulk, of the market we’ll see vertical NAND continuing to scale with a couple of us scaling fast for that market.”

Dennison also touched on longer term advances in classes of flash memory, in the form of 3D cross-point technology. These are memories stacked in cross-point arrays over CMOS logic to enable memory technology with speed features akin to DRAM but the density and cost effectiveness of NAND. The 3D stacked memory arrays in 3D cross-point technology would make these devices suitable, for future, in very high density computing and even biological systems.

“But, to conclude, NAND will not be replaced and will continue to be the lowest cost, it’s going to be the largest market in tablets, phones and so on. It’s not the best memory technology – it has poor cycling endurance and it has a terrible latency – but it is very low cost at very high density so it is the most cost-effective solution. We think that 3D cross-point absolutely has a market in terms of displacing DRAM and will selectively displace some NAND in very high performance applications but we will stay with NAND and go to 3D NAND.”

Soek-Kiu Lee, VP and Head of the Flash Device Technology Group, at SK Hynix brought the audience up to speed on his company’s NAND technology. Every year SK Hynix has increased bit density per area by around 50%. The company’s 16nm 64 GB MLC NAND flash, based on floating gate technology, has been in production since mid-2013 with SK Hynix now entering full scale mass production of 16nm chips. SK Hynix will start to ship samples of its 3D NAND chips this year with mass production happening later in 2014.

Like Shrivastava, Lee expects that 2D NAND and 3D NAND will co-exist and compete with each other in terms of reliability, performance and density, for some time and that the big challenges facing the transition to 3D NAND architectures include stabilization of multi-stack patterning to improve yields, better metrology and defect monitoring in the 3D structure itself.

Head for heights

Lastly, Applied Materials was able to provide some insight into manufacturing the more complex structures that moving to 3D NAND device architecture entails. Very simplistically, to make 3D NAND flash devices requires building extremely tall multilayer structures. Every layer in the device requires an insulating layer, so – for example – a 32-layer device is really a 64-layer device. As a result of this, aspect ratios of the structure being etched are getting to be very high and the challenge that this poses is nothing less than a game-changer for etch and deposition, according to Applied Materials’ Vice President, Advanced Technology Group Etch Business Unit, Bradley Howard.

“Historically, if you look at how scaling has gone, it has been limited by lithography on getting to the next node down, now we getting to the point where scaling is being driven by deposition and etching because as the scaling is now going in a vertical direction you’ve eased out the design rules.” The reality is that lithography is still important, Howard said, listing off control, good uniformity and other factors. ‘Everything that you had to have from lithography before still needs to be there but it just does not need to be the limiting factor for scaling.”

High aspect ratios present lots of challenges. Standard photolithography will not hold up for the long etches required for etching such deep features so hard mask layers are needed. “Depositioning is transitioning from single layer depositions in typically thinner films to multilayer stacks where you go and deposit alternating stacks of films and then also very thick films for both device and the hard mask,” said Howard.

Howard addressed the gates axis, an alternating stack of materials built up with alternating layers. “You need to have very precise control and very low defectivity. Historically, if you had a defect come in on a film it affected that bit, or that area. Now if you get a defect that gets deposited on your first layer down at the bottom it becomes a propagating defect that goes up the entire stack and it is going up in regions , which means that the defect density on deposition is becoming more important.”

Howard then moved on to hard masks. “We are going to have thicker hard masks because the aspect ratios of what you are trying to etch are getting very extreme as well as the amount of depth you have to etch. Having a micron or a micron-and-a-half of hard mask is not unusual. In effect, the hard mask that you are forming is its own high aspect ratio feature and then it is forming a high aspect ratio feature below it. In addition, there are various challenges on the isolation on getting the gap filled between the features and also into these very complex three dimensional structures.

“On the etch side high aspect ratio is really the key. There are multiple features, contacts in the array, there are contacts coming out of the staircase, and 60: 1 aspect ratios are becoming the common target here.

“At the edge of the array access still has to be made at each one of the layers, so a staircase structure is made to enable different landing pads for contacts to come down. But some of the contacts – towards the top – are very shallow and the ones at the bottom are extremely deep.

“You might think it might be achieved by doing a litho step and an etch step and a litho step and an etch step and doing that 32, 64, or whatever number of times, but what happens is that you are starting out with a feature and you etch down into the feature then you pull back the resist and then you etch again and then you pull back the resist and so you start to form your ‘steps’ that way and you do that as many times as you can get away with, depending on the amount of resist that you have. So, you can envision that you are trying to pull this resist back really fast. The problem is the resist is now determining the CD for the cell, so you need to have good control in place.” Howard summarized the challenges as being about sequential processes for both deposition and etching, thick films – whether it be the alternating stack of films or the thick films that are done to separate out the different arrays – and, finally, defect densities – especially with deposition – which are becoming more critical than ever before because of the additive effect on the deposition.

The panellists:

Dr Ritu Shrivastava, Vice President Technology Development, at SanDisk Corporation

Chuck Dennison, Senior Director, Process Integration, at Micron

Dr Soek-Kiu Lee, VP and Head of the Flash Device Technology Group, at SK Hynix

Hang-Ting Liu, Deputy Director Nanotechnology R&D Division, at Macronix International Co.

Dr Bradley Howard, Vice President, Advanced Technology Group Etch Business Unit, at Applied Materials

FinFET on SOI: Potential Becomes Reality

Thursday, December 5th, 2013

Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center

We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions.  However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.  Accordingly, we use SOI as the base on which to build the FinFET, which not only simplifies the process but enables full realization of the potential of the device.
Fully depleted transistor technologies – both planar and SOI-based FinFET – offer excellent circuit operation for SRAM and DRAM due to the unsurpassed threshold voltage matching associated with the near-absence of doping.   Additionally, good low voltage and stacked-fet circuit operation is realized due to the superior electrostatics associated with thin-body devices.  Hardware data specifically illustrating these features is described below.

Threshold voltage matching and distribution

A significant improvement in threshold voltage mismatch has been well documented, as well as the degradation associated with adding doping to a FinFET.  Less well publicized, however, is the even larger relative benefit to be found in thick-dielectric transistors, such as are used for analog and IO devices, and also in DRAM.

Random dopant fluctuation is not the only mechanism contributing to local threshold voltage mismatch, but it has historically been the largest contributor.  It has been an even larger contributor for thicker dielectrics, as its baleful influence scales directly with dielectric thickness, unlike work function variations for example.   Therefore an even more dramatic improvement in matching is found in thick-dielectric devices, as shown in Figure 1.

Figure 1. Mismatch data as a function of tinv for conventional doped (dotted line) and SOI FinFET (solid line). While the improvement in matching for ‘thin-oxide’ (1.2-1.5nm) is well known, less widely recognized is the even larger advantage obtained with ‘thick-oxide’ (>3nm) devices commonly used in IO and analog applications.

This improvement is important to IO and analog circuit operation and is vital to scaling the DRAM transfer device into the next generations.
In Figure 2 are shown probability plots of the threshold voltage for two DRAM transfer gate transistors and the profound improvement is obvious.   The FinFET version actually has a considerably thicker gate dielectric than the conventional doped device and a shorter gate yet much better matching.  The absence of thickness-driven matching opens up the device design space and enables optimization of the overall design, as well as allowing for the fundamental area scaling needed to move to the next generation.

Figure 2: Threshold voltage matching for DRAM transfer devices. Blue: 32nm generation thick oxide doping-controlled device. Red: 14nm generation thick oxide FinFET device. The FinFET device is shorter and has a thicker dielectric, yet the threshold voltage matching standard deviation is 0.7X that of the conventional planar doped version. This improvement is applicable also to other thick oxide devices, such as are used in IO and analog applications.

SRAM Vmin
One of the most important benefits of improved matching is the much-desired reduction in the minimum operating voltage of the classic 6T SRAM.  While the transistor matching data clearly show an advantage, putting it all together into a quantized FinFET SRAM cell with correct beta and gamma ratios and device centering to actually achieve low Vmin is a larger challenge.
Additionally, there may be other factors present in the scaled-up SRAM array that may not be so evident in the classic Pelgrom analysis from which most matching data are derived, such as some perturbation to line-edge-roughness, or nfet/pfet interactions, or any number of other possibilities.

Our data demonstrate that these concerns are surmountable and that real SOI FinFET SRAMs can operate at very low voltages. Figure 3 shows remarkable results on an SRAM array, with full read and write operation down to 400mV, without any assist circuitry.  This is among the best results ever reported, even among those that utilize boost techniques and in-situ tuning of the devices.

Figure 3: Shmoo plot of 14nm SOI FinFET SRAM array showing a minimum operating voltage of 400mV, with full read and write capability. This result, as good or better than any yet reported, was obtained without benefit of the chip-specific tuning techniques associated with planar fully depleted devices or specialized independent double-gate FinFETs.

Low Voltage Circuit Operation
A considerable improvement in electrostatics associated with the FinFET over conventional doped devices not only enables the necessary gate-length scaling, but simultaneously improves the relative performance at reduced voltage and therefore reduces the power density at a given performance.  While fully-depleted devices should in principle enjoy this advantage, the introduction of non-uniformity such as is involved with the tapered fin profile associated with bulk-based FinFET seriously compromises the output conductance and may obviate these expectations, as shown in Figure 4.

Figure 4: Representative bulk-based and SOI-based fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET.

The fin profile obtainable in SOI-based FinFETs is very nearly ideal and our data show that the low voltage benefits are fully realized in hardware.  The frequencies of a suite of ring oscillator circuits (inverter, NANDs, and NORs) were measured on 14nm SOI-based FinFET hardware as a function of voltage and compared to the modeled expectations.
Figure 5 shows excellent correspondence with expectation, and also shows how the data are far superior to the voltage dependence of conventional planar technology.

Figure 5: Normalized frequency reduction as a function of Vdd for a suite of circuits (NANDs, NORs, and inverters). Near-perfect correspondence of the SOI FinFET data with the compact model is shown. This flatter voltage dependence is highly superior to that typical of doping-controlled planar technology.

Conclusion
Several key elements of the putative advantages of FinFETs over conventional devices have been demonstrated in hardware.  By using SOI-based FinFET technology, the need for doping in the body has been effectively minimized, resulting in excellent matching characteristics in the undoped DRAM transfer device, and truly remarkable minimum operating voltage in the SRAM.  Additionally, the superior voltage dependence and stacked-fet circuit behavior relative to conventional devices has also been demonstrated through measurements of ring oscillators of various sorts.

Inside the Hybrid Memory Cube

Friday, September 27th, 2013

By Thomas Kinsley and Aron Lunde

The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.

Since the beginning of the computing era, memory technology has struggled to keep pace with CPUs. In the mid 1970s, CPU design and semiconductor manufacturing processes began to advance rapidly. CPUs have used these advances to increase core clock frequencies and transistor counts. Conversely, DRAM manufacturers have primarily used the advancements in process technology to rapidly and consistently scale DRAM capacity. But as more transistors were added to systems to increase performance, the memory industry was unable to keep pace in terms of designing memory systems capable of supporting these new architectures. In fact, the number of memory controllers per core decreased with each passing generation, increasing the burden on memory systems.

To address this challenge, in 2006 Micron tasked internal teams to look beyond memory performance. Their goal was to consider overall system-level requirements, with the goal of creating a balanced architecture for higher system level performance with more capable memory and I/O systems. The Hybrid Memory Cube (HMC), which blends the best of logic and DRAM processes into a heterogeneous 3D package, is the result of this effort. At its foundation is a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon -vias (TSVs), as depicted in FIGURE 1. An energy-optimized DRAM array provides access to memory bits via the internal logic layer and TSV – resulting in an intelligent memory device, optimized for performance and efficiency.

By placing intelligent memory on the same substrate as the processing unit, each system can do what it’s designed to do more efficiently than previous technologies. Specifically, processors can make use of all of their computational capability without being limited by the memory channel. The logic die, with high-performance transistors, is responsible for DRAM sequencing, refresh, data routing, error correction, and high-speed interconnect to the host. HMC’s abstracted memory decouples the memory interface from the underlying memory technology and allows memory systems with different characteristics to use a common interface. Memory abstraction insulates designers from the difficult parts of memory control, such as error correction, resiliency and refresh, while allowing them to take advantage of memory features such as performance and non-volatility. Because HMC supports up to 160 GB/s of sustained memory bandwidth, the biggest question becomes, “How fast do you want to run the interface?”

The HMC Consortium

A radically new technology like HMC requires a broad ecosystem of support for mainstream adoption. To address this challenge, Micron, Samsung, Altera, Open-Silicon, and Xilinx, collaborated to form the HMC Consortium (HMCC), which was officially launched in October, 2011. The Consortium’s goals included pulling together a wide range of OEMs, enablers, and tool vendors to work together to define an industry-adoptable serial interface specification for HMC. The consortium delivered on this goal within 17 months and introduced the world’s first HMC interface and protocol specification in April 2013.

The specification provides a short-reach (SR), very short-reach (VSR), and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking and computing along with test and measurement equipment.

FIGURE 1. The HMC employs a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon-vias (TSVs).

The next goal for the consortium is to develop a second set of standards designed to increase data rate speeds. This next specification, which is expected to gain consortium agreement by 1Q14, shows SR speeds improving from 15 Gb/s to 28 Gb/s and VSR/USR interconnection speeds increasing from 10 to 15–28 Gb/s.

Architecture and Performance

Other elements that separate HMC from traditional memories include raw performance, simplified board routing, and unmatched RAS features. Unique DRAM within the HMC device are designed to support sixteen individual and self-supporting vaults. Each vault delivers 10 GB/s of sustained memory bandwidth for an aggregate cube bandwidth of 160 GB/s. Within each vault there are two banks per DRAM layer for a total of 128 banks in a 2GB device or 256 banks in a 4GB device. Impact on system performance is significant, with lower queue delays and greater availability of data responses compared to conventional memories that run banks in lock-step. Not only is there massive parallelism, but HMC supports atomics that reduce external traffic and offload remedial tasks from the processor.

As previously mentioned, the abstracted interface is memory-agnostic and uses high-speed serial buses based on the HMCC protocol standard. Within this uncomplicated protocol, commands such as 128-byte WRITE (WR128), 64-byte READ (RD64), or dual 8-byte ADD IMMEDIATE (2ADD8), can be randomly mixed. This interface enables bandwidth and power scaling to suit practically any design—from “near memory,” mounted immediately adjacent to the CPU, to “far memory,” where HMC devices may be chained together in futuristic mesh-type networks. A near memory configuration is shown in FIGURE 2, and a far memory configuration is shown in FIGURE 3. JTAG and I2C sideband channels are also supported for optimization of device configuration, testing, and real-time monitors.

HMC board routing uses inexpensive, standard high-volume interconnect technologies, routes without complex timing relationships to other signals, and has significantly fewer signals. In fact, 160GB/s of sustained memory bandwidth is achieved using only 262 active signals (66 signals for a single link of up to 60GB/s of memory bandwidth).

FIGURE 2. The HMC communicates with the CPU using a protocol defined by the HMC consortium. A near memory configuration is shown.

FIGURE 3.A far memory communication configuration.

A single robust HMC package includes the memory, memory controller, and abstracted interface. This enables vault-controller parity and ECC correction with data scrubbing that is invisible to the user; self-correcting in-system lifetime memory repair; extensive device health-monitoring capabilities; and real-time status reporting. HMC also features a highly reliable external serializer/deserializer (SERDES) interface with exceptional low-bit error rates (BER) that support cyclic redundancy check (CRC) and packet retry.

HMC will deliver 160 GB/s of bandwidth or a 15X improvement compared to a DDR3-1333 module running at 10.66 GB/s. With energy efficiency measured in pico-joules per bit, HMC is targeted to operate in the 20 pj/b range. Compared to DDR3-1333 modules that operate at about 60 pj/b, this represents a 70% improvement in efficiency. HMC also features an almost-90% pin count reduction—66 pins for HMC versus ~600 pins for a 4-channel DDR3 solution. Given these comparisons, it’s easy to see the significant gains in performance and the huge savings in both the footprint and power usage.

Market Potential

HMC will enable new levels of performance in applications ranging from large-scale core and leading-edge networking systems, to high-performance computing, industrial automation, and eventually, consumer products.

Embedded applications will benefit greatly from high-bandwidth and energy-efficient HMC devices, especially applications such as testing and measurement equipment and networking equipment that utilizes ASICs, ASSPs, and FPGA devices from both Xilinx and Altera, two Developer members of the HMC Consortium. Altera announced in September that it has demonstrated interoperability of its Stratix FPGAs with HMC to benefit next-generation designs.

According to research analysts at Yole Développement Group, TSV-enabled devices are projected to account for nearly $40B by 2017—which is 10% of the global chip business. To drive that growth, this segment will rely on leading technologies like HMC.

FIGURE 4.Engineering samples are set to debut in 2013, but 4GB production in 2014.

Production schedule

Micron is working closely with several customers to enable a variety of applications with HMC. HMC engineering samples of a 4 link 31X31X4mm package are expected later this year, with volume production beginning the first half of 2014. Micron’s 4GB HMC is also targeted for production in 2014.

Future stacks, multiple memories

Moving forward, we will see HMC technology evolve as volume production reduces costs for TSVs and HMC enters markets where traditional DDR-type of memory has resided. Beyond DDR4, we see this class of memory technology becoming mainstream, not only because of its extreme performance, but because of its ability to overcome the effects of process scaling as seen in the NAND industry. HMC Gen3 is on the horizon, with a performance target of 320 GB/s and an 8GB density. A packaged HMC is shown in FIGURE 4.

Among the benefits of this architectural breakthrough is the future ability to stack multiple memories onto one chip. •

**********
THOMAS KINSLEY is a Memory Development Engineer and ARON LUNDE is the Product Program Manager at Micron Technology, Inc., Boise, ID.

Today’s Top Reliability Challenges

Friday, March 1st, 2013

By Pete Singer

BTS, BTI, soft errors, dielectric breakdown and other reliability challenges will be addressed at the upcoming International Reliability Physics Symposium.

A double challenge faces today’s reliability engineers. They not only must understand the physics behind a complex set of mechanisms, such as bias temperature instability (BTI), but they must accurately simulate those mechanisms through modeling to predict device performance over time and estimated end-of-life.

These challenges will be front and center at the upcoming International Reliability Physics Symposium (IRPS), to be held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA. The conference begins with tutorials on Sunday that run through Monday afternoon (40% of attendees are first time attendees). A plenary session on Monday afternoon after the tutorials is a “Year in Review” where experts highlight work published over the last year. Tuesday morning starts with a keynote by Berkeley’s Chenming Hu who will talk about compact modeling as well as tri-gate scaled reliability challenges. Krishnan said that compact modeling is one of the main themes of this year’s conference. “There has been a lot of work on how do we take reliability into the circuits and how do we model, not only at the SPICE level, but from a compact modeling perspective,” he said. The Compact Modeling Council will have a meeting immediately following IRPS at the same location. Tuesday’s keynote is followed by 19 sessions in three tracks, with a panel session, workshop and a combined poster session and buffet at Chateau Julien wine estate on Wednesday evening.

In terms of the overall reliability concerns now facing the industry, Krishnan said the number one thing people are worried about is the tri-gate finFET. “Our devices have been planar but now all of the sudden you have three sides to it. How do you reject the heat from a finFET?” he asks. “The second concern is basically electromigration. How do we scale EM?” The third main challenge lies in gallium nitride and HEMT structures. “What is the reliability of these GaN FETs in the field when you have some of these trapping effects that go on?” Krishnan asks. “The switch is good on day one but it slowly degrades over time. That’s why you’re seeing a lot on GaN FETs.”

A few examples that will be presented at this year’s IRPS will serve to highlight the reliability issues facing the industry.

Reliability in memories

Researchers from Mila Polytechnic, Micron and Intel will present a paper titled “Resolving Discrete Emission Events: a New Perspective for Detrapping Investigation in NAND Flash Memories.” Charlie Slayman, IRPS Vice Technical Program Chair, said that researchers looked at the effects of individual discrete traps in the tunnel oxide for 30nm NAND flash. “Looking at the threshold voltage over time, you can actually see the threshold voltage change in discrete quantized steps. They’ve analyzed this and determined these are individual traps in the device that are trapping and detrapping. This will have an impact on future flash technologies where single electron and defects become increasingly important,” Slayman said.
In a second paper on resistive RAM, authors are from Minatec and coauthors from the Center for Semiconductor Components at the University of Campinas Brazil and the department of electrical engineering at Stanford studied the retention time — the ability of a resistive RAM device to maintain its resistance state. The RAM consists of two metal electrodes and a hafnium oxide between those, where the hafnium oxide acts as a variable resistor. The authors look at the use of different metal materials. In one case they use platinum for the electrode, and in a second example they use a TiN-Ti to sandwich the hafnium oxide. They showed that the Pt/Pt electrode device loses its on-state resistance sooner than the TiN/Ti device. “They attribute the phenomenon to oxygen interstitials in the HfO2, and TiN-Ti’s ability to basically getter those interstitials and pin them at the surface,” Slayman said. This is illustrated in FIGURE 1.

Figure 1. Atomistic structure of HfO2 with an Oi intersitials leading the the recombination of Oi+Vo in Pt/Pt during reset (left). Atomistic structure of Ti awith an Oi interstitial creating more Vo in HfO2 (right).

A third paper on memory focuses on flash, specifically erratic bit classification in flash devices used in automotive applications. The authors studied error correction code and redundant addresses, both of which are widely used in flash as well as SRAM and DRAM memory. “What’s new with this paper is the authors have classified these erratic or bad bits,” Slayman said. FIGURE 2 shows three different types of erratic bits and their behavior over time. “In the first case, they are looking at the read current of one type of erratic bit where it will periodically spike to a higher read current. Then there’s another type of erratic bit they observed where about half the time, it’s in a low read current state and the other half of the time it’s in a high read current state. Then they have a third class of erratic bits where it’s just going back and forth constantly between the high read state and the low read state,” Slaymain explained.

Figure 2. Examples of different erratic bit signatures (left). Normal and erract states are highlighted for clarity. Erratic bits percentage per signature classification in delay time cycling experiments are shown on the right.

Typically, redundant address repair would be used when these bad bits are created, after so many read-write cycles, but that can be an expensive fix. “For a certain class of bad bits — such as the erratic bits on the top of Fig. 3, that are most of the time good and only infrequently bad — don’t bother using redundant address, just use your error correction code and that’s sufficient,” Slayman said. “Save your redundant addresses for the really bad erratic bits.” The authors demonstrated that they can save 35% of their redundancy space by using this classification scheme.

FinFET concerns

At the device level, Giuseppe Larosa, IRPS Technical Program Chair, said the focus in squarely on FinFETs. “For future nodes, 14nm and down to 10nm, FinFETs will be the device design of choice,” he said.

Larosa said one of the key questions people ask is how BTI is actually scaling when we go to finFETs. “Key information is coming from Intel, suggesting that NBTI seems to be an issue because it’s increasing with finFET scaling.” At IRPS, Intel will present a comparison of 32nm planar technology to a 22nm finFET technology, as shown in FIGURE 3 (32 in red and 22nm in blue). “You can see they can manage to really reduce the PBTI but the NBTI is actually getting worse with scaling,” he said.

Figure 3. 22nm BTI is comparable to 32nm. NMOS is significantly improved due to gate optimization and WF scaling. The second item on the list for finFETs is self-heating. "Self-heating is always there," said Larosa. "Anytime you drive current through a channel you produce some self-heating. But if you have a bulk technology, the self-heating will just move away down into the bulk. But in finFETs, because it's a three-dimensional structure, this self-heating is a bottleneck in scaling down."

Another Intel paper talks about the effect of self-heating in accelerating aging, not only at the level of the device in terms of finFETS, but also in terms of metal wires that are sitting on top of the finFET. “You may have some impact on electromigration in the metal wires. You can have enhanced electromigration simply because the self-heating of the finFET can locally increase the temperature in the metal wires above,” Larosa explained. “A key issue here is how to calibrate the self-heating to make sure that you have a good understanding of the local temperature of the structure, and then how to take that into account in your models that predict end-of-life aging, specifically finFETs and metal lines,” he said.

Figure 4. Self-heat manifests as a sensitivity to the fin or gate count in switching aging degradation. Here, switching conditions are accelerated to enhance the sensitivity.

FIGURE 4 shows how self-heating at the device level is affecting aging of a given FET: It’s a function of the number of fins and the number of active lines per transistor. “It looks like through optimization of the gate stack with appropriate oxide scaling and metal gate work function tuning and so on, you can achieve reliability similar to previous nodes,” Larosa said.
Another reliability concern to be discussed at IRPS: High-k dielectrics. “There are two aspects of high k dielectrics that people have to face,” Larosa said. “BTI is again a concern with continued scaling. Contrary to nitride oxides, high-k bring a higher sensitivity to the NFET devices to PBTI. This is mostly due to the fact that the high-k material can be sensitive to electron trap activation or generation, producing PBTI effects that you will not see in standard nitride oxide technologies.”
At IRPS, GLOBALFOUNDRIES will present the first large-scale stochastic BTI (particularly PBTI) study in metal gate/high-k technology confirming fundamental BTI area scaling trends derived from conventional SiO2 technologies, and IBM will report on TDDB in high-k, and how it will lead to more accurate models. “Without this model you cannot be confident in predicting end of life, and having this type of simulation can help in making a projection that will be relevant for product level of circuit level reliability,” Larosa said.