Posts Tagged ‘diamond’
Synaptic transistor learns while it computes
Materials scientists at the Harvard School of Engineering and Applied Sciences (SEAS) have now created a new type of transistor that mimics the behavior of a synapse. The novel device simultaneously modulates the flow of information in a circuit and physically adapts to changing signals.
Exploiting unusual properties in modern materials, the synaptic transistor could mark the beginning of a new kind of artificial intelligence: one embedded not in smart algorithms but in the very architecture of a computer.
In principle, a system integrating millions of tiny synaptic transistors and neuron terminals could take parallel computing into a new era of ultra-efficient high performance.
Several prototypes of the synaptic transistor are visible on this silicon chip. (Photo by Eliza Grinnell, SEAS Communications.)
While calcium ions and receptors effect a change in a biological synapse, the artificial version achieves the same plasticity with oxygen ions. When a voltage is applied, these ions slip in and out of the crystal lattice of a very thin (80-nanometer) film of samarium nickelate, which acts as the synapse channel between two platinum “axon” and “dendrite” terminals. The varying concentration of ions in the nickelate raises or lowers its conductance—that is, its ability to carry information on an electrical current—and, just as in a natural synapse, the strength of the connection depends on the time delay in the electrical signal.
Structurally, the device consists of the nickelate semiconductor sandwiched between two platinum electrodes and adjacent to a small pocket of ionic liquid. An external circuit multiplexer converts the time delay into a magnitude of voltage which it applies to the ionic liquid, creating an electric field that either drives ions into the nickelate or removes them. The entire device, just a few hundred microns long, is embedded in a silicon chip.
Diamond imperfections pave the way to technology gold
Researchers at the Lawrence Berkeley National Laboratory (Berkeley Lab) and the University of California (UC) Berkeley have taken an important step towards unlocking this key with the first ever detailed look at critical ultrafast processes in these diamond defects.
Using two-dimensional electronic spectroscopy on pico- and femto-second time-scales, a research team led by Graham Fleming, Vice Chancellor for Research at UC Berkeley and faculty scientist with Berkeley Lab’s Physical Biosciences Division, has recorded unprecedented observations of energy moving through the atom-sized diamond impurities known as nitrogen-vacancy (NV) centers. An NV center is created when two adjacent carbon atoms in a diamond crystal are replaced by a nitrogen atom and an empty gap.
The next big thing in the energy sector: Photovoltaic generated DC energy
Rajendra Singh, D. Houser Banks Professor in the Holcombe Department of Electrical and Computer Engineering and PhD student Githin F. Alapatt at Clemson University, along with and Akhlesh Lakhtakia, Charles Godfrey Binder (Endowed) Professor in Engineering Science and Mechanics at the Pennsylvania State University, recently examined the most promising types of solar cells to power every home. On October 23, 2013 they published a paper entitled “Making Solar Cells a Reality in Every Home: Opportunities and Challenges for Photovoltaic Device Design” in IEEE Journal of Electron Devices (Volume 1, number 6, June 2013 Issue).
The researchers have proposed a new multi-terminal multi-junction architecture for inexpensive PV electricity generation. Efficiency will exceed the currently feasible 25%. The proposed architecture is based on the use of currently commercial Crystalline solar cells and thin-film solar cells made of materials (such as copper oxide) that are abundant in Earth’s crust. Management of the flux of solar photons through the solar cells is expected to boost efficiency, but the additional manufacturing costs to be incurred thereby remain unknown, according to the researchers.
Prof. Singh says that “the creation of local DC power grids can save power being lost in the transmission and unnecessary conversion from DC to alternating current (AC) and then back to DC.” Most electronic appliances and electric loads operate on DC and by transmitting and converting AC power to DC about 30% of the total power generated is lost. Today, PV electricity generation and distribution on a DC microgrid is the best way to power villages without access to electricity. It is also the best option to replace aging power generation and transmission infrastructure in USA and other developed countries.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.