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Posts Tagged ‘DFY’

Foundry, EDA partnership eases move to advanced process nodes

Monday, September 15th, 2014

By Dr. Lianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc., San Jose, Calif.

Partnerships are the lifeblood of the semiconductor industry, and when moving to new advanced nodes, industry trends show closer partnerships and deeper collaborations between foundries, EDA vendors and design companies to ease the transition.

It’s fitting, then, for me to pay homage in this blog post to a successful and long-term partnership between a foundry and an EDA tool supplier.

A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement. The goals were to improve SRAM yield and provide faster turnaround of a new process platform development.

The foundry used the EDA firm’s high-sigma DFY solution to optimize its SRAM yield for 28nm processes development. Early this year, it announced 28nm readiness for multi-project wafer (MPW) customers. One of the reasons it was able to release the 28nm process with acceptable SRAM yield in a short time was due to a new methodology for SRAM yield ramping that deployed a DFY engine.

During advanced technology development, the time spent on SRAM yield ramping is significant because statistical process variation, particularly local variation between two identical neighboring devices sometimes called mismatch, limits SRAM parametric yield. The impact of local process variation increases when moving to smaller CMOS technology nodes.

In the meantime, supply voltage is reduced, so operating regions are smaller. The difficulty achieving high yield for SRAM is greater because smaller nodes require higher SRAM density. Such challenges require very high sigma robustness or high SRAM bitcell yield. Statistically, the analysis for the SRAM bitcell at 28nm needs to be at around 6 σ, while FinFET technology at 16/14nm sets even higher sigma requirements for SRAM bitcell yield.

During technology development, foundry engineers improve the process to solve defect-related yield issues first. Design-for-manufacturing methodologies can be used to eliminate some systematic process variations. However, many random process variations, such as random dopant fluctuations (RDF), line edge and width roughness (LER, LWR), are fundamental limiting factors for parametric yield particular to SRAM.

Traditionally, foundry engineers rely on experience and know-how from previous node development efforts to analyze and decide how to run different process splits for different process improvement scenarios to optimize SRAM yield. These efforts are often time-consuming and less effective at advanced nodes like 28nm because the optimization margin is much smaller.

The fab’s new SRAM yielding flow used a high sigma statistical simulator as the core engine. It provided fast and accurate 3-7+σ yield prediction and optimization functions for memory, logic and analog circuit designs. During process development, the tool proved its technology advantages in both accuracy and performance, and was validated by silicon in several rounds of tape outs throughout the development process. It required no additional tuning on technology or special settings on the tool usage, so even process engineers who are not familiar with EDA tools could run them to get reliable results to guide their process tuning for SRAM yield improvement.

The flow was able to predict SRAM yield for different process and operating conditions. It simulated SRAM yield improvement trends and provided process improvement direction and guidelines within hours. A methodology such as this becomes necessary for advanced nodes where the remaining optimization margin is small. A simulation-based methodology can run through all possible combinations that process engineers want to explore, providing better yield results and faster yield ramping. Comparatively, the traditional way of exploration based on experiences and running large amount of process splits is limited and may not yield optimum results. It also is time consuming as the engineer would need to wait for tape out results then run another set of trials that could consume months.

The flow saved months ramping up SRAM yield for the 28nm process node. It reduced iteration time and saved wafer cost. Process engineers now only need to fabricate selective wafers to validate simulation results. They know which direction is optimal and have guidelines to run process splits that will help them identify the best conditions and converge on the best yield. They gained greater certainty as they saw more simulation-to-silicon correlation data as the project progressed.

A well-established methodology and flow brings value to process engineers because they can rely on DFY high sigma simulations to lay the foundation for their process improvement strategies to reach certain SRAM yield targets. They can run selective process splits to verify the results for lower wafer costs, fewer process tuning iterations and faster time to market.

Overall, this is a highly successful and mutually beneficial partnership, and the value of DFY to process technology development, is obvious. The same DFY methodology can be used for memory designers as SRAM yield is their primary target as well. The only difference is it tunes design variables using the same methodology, flow and tool solutions.

It’s easy to see the value of a tight collaboration between the foundry, EDA vendor and design companies and why it will be a trend on top of the “foundry-fabless” business model.

About Dr. Lianfeng Yang

Lianfeng Yang, ProPlus Solutions, Inc.

Dr. Lianfeng Yang currently serves as the Vice President of Marketing at ProPlus Design Solutions, Inc. Prior to co-founding ProPlus, he was a senior product engineer at Cadence Design Systems leading the product engineering and technical support effort for the modeling product line in Asia. Dr. Yang has over 40 publications and holds a Ph.D. degree in Electrical Engineering from the University of Glasgow in the U.K.

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