By Ann Steffora Mutschler

For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes.

The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “The way we used to do things is not going to work anymore.”

It’s common knowledge that getting a good yield at advanced nodes is getting tougher. “It’s a big challenge for foundries because the lithography equipment is still the same and they are pushing the technology nodes,” said Manoj Chacko, product marketing director at Cadence. “At 28nm they are using the 193nm immersion stepper or scanner. At 20nm it is the same equipment; at 16nm it’s probably going to be the same machine and most likely for 10nm it is likely to be the same machine unless EUV kicks off. What’s happening here happening here is that the wavelength is 193nm, immersion has to improve the K-1 factor, but the foundries are pushing feature sizes more than 10 times smaller. So the lithography issue is a big problem.”

Finding lithography issues in a design is based on computational lithography, which is an extremely compute-intensive process. “Compute-intensive processes are good in manufacturing and were okay at 40nm, but as we go down to 28nm and 20nm the computing power needed is not like just 1X or 2X. It’s almost like 5X or 10X more, so the number of CPUs needed to do a job is higher,” Chacko pointed out.

While a fab or foundry may be outfitted with the CPU power to handle these processes, the design team is not. This is where is where pattern analysis comes in. “Just like the same thing we are hearing in the Web space— they call it big data—there is a similar analogy here. How do you process large amounts of data in an intelligent way? That is the whole crux of this thing.”

Cadence, Mentor Graphics and Synopsys all have worked with the foundries on essential pattern matching meant to evolve DFM signoff with minimal impact to the design community. Each has its own approach, but they all meet the requirement of the foundry for signoff.

In the case of Cadence, following the acquisition of CommandCAD in 2007, the company includes pattern classification as the core essence of its approach in order to reduce the sheer number of patterns from the foundry, which could number in the hundreds of thousands depending on the process.

“What we do for foundries with this technology for pattern classification is to try and reduce hundreds of thousands of patterns into pattern families. If we can reduce say 100,000 patterns into 100 patterns, this becomes an economical and deployable capability for the design community. We are able to reduce and classify hundreds of thousands of patterns into pattern families. So what pattern matching tools do is they have the tech file, which is a library of about patterns from the foundry, and after they’ve done routing they do a pattern certain match. Whatever that patterns are found that information is fed back to the router to avoid those patterns,” Chacko said.

In the case of lithography hotspot checking, which also falls into the pattern-matching genre, it turns out that there are certain specific patterns and combinations of physical shape. When one shape of a certain type is next to another shape of this type and it is exposed to lithography, it will not come out right. There may be some pinching or shorts– and those patterns need to be fixed, Haider explained.

“The set of patterns that are bad—the violating patterns—for a given node is not necessarily a static set. So we start with a large number of potential violators. As the process matures the people in the factory fine-tune the processes and the patterns are not violators anymore, so slowly the need for very strict checking gets mitigated. This is what we saw at 45nm. We are seeing a bit of it at 28nm as well, and at 20nm it remains to be seen,” he continued.

Identifying and preventing problems
At Synopsys, Haider noted that the company has been working on hotspot checking technology for a long time and has invested in internal development. The company comes at the problem from two trajectories.

First is the ability to perform a detailed lithography simulation on the entire design whereby it is very exact but admittedly heavy. There is also a pattern matching technology where instead of simulating the entire process Synopsys works with the
foundry to obtain a library of potentially offending patterns, searches the design for those, and that is 1,000 times faster than the first approach.

Technically, explained Stelios Diamantidis, product marketing manager at Synopsys, “with pattern matching technology what we’re doing is taking a problem that is very mathematical on the foundry side—it is very much related to optics and simulation and applies a lot of high complexity convolution to design shapes—and we are turning it into a much more manageable physical design and verification problem that is closer to a traditional design rule check or a search-and-repair type application. That’s really the special sauce in the pattern matching technology—how to transition from a foundry-side manufacturing application into something that can be much more designer friendly and also much more intuitive and usable. The technology itself really works with managing geometries. It leverages our hierarchical design analysis validator, which we use for design rule checks, but then translates this or augments it into a two-dimensional space, multi-shape search capability.”

Michael White, director of product marketing for Calibre physical verification at Mentor Graphics, agreed that the challenge that engineers have seen is that doing simulation over the entire design is very computationally expensive and the run times for doing lithography at the full chip level are prohibitively long. “Lots of folks were doing full litho on their IP. They were doing full litho on their IP blocks as they were building up their design. But when they were getting to the full chip level the pain level was pretty high. That is still true today where folks are doing full LFD simulation at the cell or block level as they are building up their design. But again, you need to come up with a different strategy at the full-chip level.”

That is why pattern matching has become so interesting at 28nm as the way to make it practical to do full-chip lithography simulation. Using the equation-based DRC technology, he noted that when a match is found, the designer can get a hint on how to fix the problem within the flow.

Interestingly, White has observed more rapid adoption by fabless companies because while producing a new chip, “they get back that their yields aren’t quite what they want. Their failure analysis teams working at the last chip [tell them], ‘We had a failure here, we had a failure there.’ The failure analysis team typically are former foundry or fab folks, so they are used to looking at a CD SEM and looking a series of shapes. The traditional communication methodology was for them to draw on a piece of paper and say, ‘I saw this set of shapes.’ Somebody then tries to use a text-based syntax to describe that, and then they go off and do checks to find out if there are other designs in process within the company, and whether this pattern is present anywhere else. That whole flow takes weeks, and you are going from a CD SEM image, to something on paper, to a text-based syntax. You are transforming how you are communicating what the problem is through multiple different mediums. It’s not very effective.”

Pattern matching allows the DFM engineers to clip out patterns from the GDS and use that to populate a library of weak and detractor patterns, which significantly speeds up the feedback loop from what they were finding in failure analysis and test back up to the design teams. That allows the teams to start fixing yield detractor patterns and stop using the patterns that cause problems, he said.

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Semiconductor Manufacturing & Design sits down with Mentor Graphics’ Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular.

By Ann Steffora Mutschler
As semiconductor design teams struggle to wring the last few percentage of die shrink from a technology node, much of the ability to do that rests on the EDA tools.

From place and route through DFM checks—essentially, everything that happens before the design is sent to the fab or foundry—it all must be tightly integrated with the manufacturing process so it correctly reflects what the process will print.

“We’ve pushed the limits to keep it manufacturable and that’s about it, and we want to get the very best die size from a technology point of view,” said Subi Kengeri, vice president of advanced technology architecture in the office of the CTO at GlobalFoundries. “But if the place and route and the EDA tools are going to be so inefficient that all the technology value does not get translated to the SoC level value then you’ve failed. Who cares how capable your technology is by itself, if it does not get translated to SoC-level product value?”

At 20nm, the most obvious impact of the required double patterning on DFM is cycle time. Design teams must build in additional cycle time due to some foundries (i.e. TSMC) performing a gray-level check, explained Manoj Chacko, product marketing director at Cadence, which means they don’t require the designers to decompose the layout. Other foundries require their customers to decompose and then do the DFM checks.

“Decomposition is not a simple thing, meaning there are a lot of complexities here—the cycle time at the signoff DFM checks, the runtimes are going to take longer,” Chacko said. When we talk specifically about DFM, like for example, a litho verification check is going to be more complex. Even today at 20nm with the litho verification check, the layout has to be decomposed, then the litho checks have to be run and it takes quite a lot of time. When we talk about triple and quadruple splitting there’s definitely a direct impact there. The most obvious one is if we propagate this up into the design chain, it’s really getting more complex because the routers have to do more than double—three colors, four colors. Then you add one more level of complexity to that.”

To make matters worse, there are two flavors of double patterning. One is litho-etch litho-etch (LELE); the other is self-aligned double patterning (SADP) or spacer patterning.

“What if, say, at 10nm the foundry says, ‘for these two layers, we’re going to use litho-etch, litho-etch, for another two layers we’re going to use self-aligned double patterning.’ Imagine the complexity now. These kinds of things are within the realms of possibility,” Chacko said.

David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics confirmed for triple and quadruple patterning there is already work being done. “We already have people using code and testing it out.”

He noted that the term DFM means ‘design for manufacturing,’ and in essence that’s all multi-patterning is. “You have to design it in a way that it can be manufactured. In particular there’s this new constraint that in order to recreate the shapes that you want on the mask at the dimensions we’re talking about you have to constrain the layout in a way that the shapes can be placed on separate masks, so it inherently is a DFM requirement because it’s a design constraint driven by a manufacturing requirement making it able to be manufactured. Whether it’s double, triple or SADP just depends on the manufacturing tricks, so to speak.”

Those approaches affect other DFM technologies, though, such as hotspot protection.

“Now it’s not as simple as it was because for a given layer, you’re not printing once, you’re printing twice,” Abercrombie said. “Whereas before double patterning you would take the layer and you would simulate the contours of the lithographic image, then basically do spacing checks or width checks on the contours to find out as printed, the question now is will it actually be robust?”

Simply put, once the lithographic process is simulated, the result is measured. With double patterning, the litho simulation has to be done on two separate masks, separately, and then those contours must be overlayed on top of each to see what the final contour will look like.

“Then because the two masks can misalign compared to each other, you’ve got to then do corners,” he said. “The same thing impacts fill—the fill data has to be colored too. Now you’re not only balancing the density of a mask, you’re balancing the density of two. Not only do the sum of the two masks including the fill have to meet some level of density, but each mask has to be uniformly dense unto itself or the etch process associated with printing and etching them. So fill becomes one of the tools to do that, not only to fill it so that you get a total amount of data uniformly but then biasing the colors of the fill shapes. Imagine in the surrounding real shapes (the shapes that make up the circuit) that for some reason there was more of one color than the other. Then when you put in the fill, you’d want to bias the coloring of the fill the opposite way to even out in that region the color percentage of each. You have to start looking at doing things like that.”

Complexity drives collaboration
Given the challenges at 20nm, there is a lot of collaboration that happens early on in the EDA-foundry ecosystem. “Essentially the motivation and the goal of the foundry partner and the EDA partner have been to reduce the impact for the design community,” Chacko said. “Think about at 20nm right now, two years ago there was a lot of anxiety about whether designers, place and route people, do a decomposition. You look at it now and the rules are all there—there are double-patterning rules, there’s decomposition. In the end, that’s what’s going the happen. The EDA tools will develop and whatever has to be done will happen. Essentially the impact is designers will have to budget more verification time. Signoff definitely is getting more intense as you think of the next nodes because there’s more complexity, more checks to be done because of not just one mask, now two masks, three masks and too many interactions and therefore the critical problem is the predictability of the yield. That what really becomes key.”

The risk for the foundry is going up, and to mitigate the risk they require more verification in the design and the signoff flows. That means DFM verification will become more complex.

“It’s not that they’re trying to make things more difficult, but they have good consistency with their process and the infrastructure that they are delivering, which are the tech files and the rule decks and so on. So if you give a foundry the design and the foundry does OPC, they do this decomposition, they do OPC, they make a mask. The key thing is that they are enforcing a nice tie-in with what they are using in manufacturing or not having too much imbalance between their manufacturing flow and the signoff flow,” he added.

Help wanted
All of this complexity also translates to a need for additional engineering talent, Abercrombie said. “The designs are bigger, there’s more complexity not just with double patterning but with all the other various rules. You just look at the number of rules in the design rule deck. It continues to increase almost exponentially from node to node to node. It gets more complex; there’s more to account for. You’re doing more layouts that are harder layouts.”

What this boils down to is that semiconductor companies must hire additional skilled engineers, as well as purchase additional CAD tools. “Not only do they need more tools, but they need a tool that now can do double patterning or pattern matching or all of these other things. They need to run on more CPUs because the designs are so huge that you just need more CPU power to crunch it.”

By Ed Sperling
The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process.

At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. That has prompted everything from new design strategies that incorporate more third-party IP and full subsystems to changes in how long companies stay at one process node and whether they skip nodes. In some cases, it also has led to shrinking the verification schedules, which raise questions about just how bug-free chips will be in the future, and how much can be accomplished once chips hit the market through software updates.

Particularly hard hit are the routers. Routers are a key part of any design. Place and route has automated much of this complex but highly redundant task for decades, only to be pushed back into redressing the issue at each successive node. Something has changed over the past couple nodes, though. There is more to consider, and routers are paying the price. Because wires don’t scale as well as transistors, the resistance causes heat and noise that can interrupt signals. That has to be taken into account by the router.

Add to that more metal layers, more and increasingly complex interconnects, and more congestion around memories that are scattered throughout SoCs and the problem of routing becomes even tougher. There has been much work done to solve this problem, one node at a time. But EDA vendors say there is much more to be done at each new node, making the problem worse.

“Yesterday’s routers were overworked, too,” said Aart de Geus, chairman and co-CEO of Synopsys. “But the advances being made are remarkable.”

Whether those advances are sufficient, though, is a matter of debate, particularly at 28nm and beyond. Throw in double patterning at 20nm, and finFETs at 14nm, and it’s enough to create panic in some circles.

“With double patterning and triple patterning, all the EDA guys say everything is ready—and it’s true that most of the pieces are ready—but not everything can be combined,” said Jean-Marie Brunet, product marketing director for litho-friendly design and DFM at Mentor Graphics. “You need to change how you deal with place and route in double patterning. It impacts the router, the placer, how you create router fill and pin access.”

Brunet said there are now about 2,000 to 2,500 rules for the router to deal with. And he said almost every major EDA player’s router does basically the same thing, so if one vendor is wrestling with the problem then so is everyone else.

“It’s no longer just layout that is very complicated. The problem is that the router has to understand the rules and still do all the things that it has been doing. The complexity of vias is unbelievable. At 14nm we’re seeing double vias everywhere, while at 28nm we did not have double vias. And how do you explain to a router that a via is rectangular?”

Rectangular vias were introduced by the major foundries at 28nm. It is uncertain at this point whether they will be replaced by cylindrical vias in the future, but it’s clear this has made routing more difficult. More complexity equals more design rules.

“We used to have 10 pages of design rules 20 years ago,” said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “It’s now more than 100 pages, and that puts a huge burden on automated layout and routing. You need to work on the tools a couple years in advance.”

From a design standpoint, each new node requires more restrictive design rules just to make sure that chips are functional and that yield is sufficient. But adding 3D transistors and double patterning require another big jump in the number of design rules. Bohr, who is working on the 10nm node, said Intel is now in the early development phase of defining design rules for that node.

“This is the price we pay to expand 193nm immersion lithography,” he said. “The good news is that we can re-use some of the tools. The bad news is that it requires a lot more rules.”

GlobalFoundries is working on 10nm place and route tools, as well, according to CTO Gregg Bartlett. “This requires a lot of collaboration across the ecosystem,” he said. “We’re in early discussions on this.”

Going up
One of the ways that chipmakers have dealt with this kind of complexity has been to add more metal layers. This is a sort of crude stacked die approach, rather than one using through-silicon vias and separate die or subsystems, but it brings its own unique brand of problems from a design standpoint.

“There are two challenges as far as the router goes,” said Rob Aitken, an ARM fellow. “The first involves metal layer one rules, which need to have bi-directionality—vertical and horizontal. Then there is everything else. But a huge amount of the complexity in the rules is the interaction of the vertical and the horizontal. That can bring it to its knees.”

And increasingly it has. The amount of time spent on the routing side of the design is increasing, which is part of the reason there has been such slow movement to the next process node. It’s also one of the reasons there has been such an explosion recently in the design for manufacturing software market, which serves as yet another checkpoint for rules violations.

FinFETs will add yet another volume of design rules, which is one of the reasons that fully depleted silicon on insulator (FD-SOI) has gained more attention lately. The rules are basically the same, making it an attractive alternative all the way down to 14nm. After that, it is likely that both finFETs and FD-SOI will be required.

“The big question is what is the turnaround of the routing capability,” said Mentor’s Brunet. “One way you get around that is to turn off all the features when you test it, so it looks good when you bring a product to market. But that doesn’t work for long. And improving layout at the end of the design cycle is difficult.”

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. (Part one can be found here.)

SMD: Let’s re-visit e-beam again. Why is direct-write and maskless so critical for the industry?
Fujimura: Hopefully, people see the benefits. It’s generally not for huge volumes. Let’s say you want to develop a chip and you are not sure it’s going into high volume production yet. It’s getting incredibly difficult to do that now. Innovation in the ecosystem supply chain is being stifled because of cost issues. To help those types of customers, we can do something like direct-write, where there is no mask cost and there are lower volumes. These are important things for the ecosystem to invest in for the sake of the whole semiconductor industry. We are trying to do that with our eBeam Initiative. We were talking about 450mm earlier. With any new technology, in order to get the level of funding you want, you have to appeal to the mass market. But some investments are better for the long term. E-beam investments can be very important not just for the e-beam community, but also the entire semiconductor supply chain.

SMD: How does maskless gain traction?
Fujimura: We also see it in complementary lithography. In complementary litho, you can draw the lines with nanoimprint, EUV or anything else. And then you cut the lines using e-beam. I think that kind of concept being prompted by the major players will be a great way to fund and kick-start the technology into the mass market.
Rey: We have been looking at e-beam direct-write techniques. But we completely agree with Aki about the level of investments in maskless. We have looked at the published information in terms of how much research money has been going in EUV as compared to direct-write. There are orders of magnitude difference between the two of them. In terms of the type of research that we are doing, Mentor has been following the Imagine program with Leti in Europe for direct-write. We see a level of maturity that is still required to even understand the whole magnitude of what the problem is. We don’t have clarity, as compared to what we have for multi-patterning techniques. There is a large gap between the two things.

SMD: When will maskless lithography go into production?
Fujimura: There are people that use direct-write for the 65nm node. But predicting the future has its risks. So that’s a difficult question. It depends on the volumes. In some ways, it’s ready to go.

SMD: Any thoughts on nanoimprint?
Fujimura: One of the things about nanoimprint is that it enables line and space patterns. It seems like they are having some success in being able to print small features very reliably. It’s great for that. It’s also perfect for the complementary lithography idea. Nanoimprint can draw lines. And then e-beam can cut the holes. Something like that can be a good combination. One thing to note is that nanoimprint masters are made with e-beam technology. It’s 1x dimensions, unlike photomask, which are 4x dimensions. It’s basically a direct-write problem to write those masks.
Enami: Nanoimprint is very effective for NAND flash applications. One manufacturer has started pre-production at 11nm by using nanoimprint.
Rey: We are having conversations regarding what is required at 10nm these days. They all seem to be coming from the other techniques and not from nanoimprint.

SMD: DFM is playing a greater role in lithography and in the manufacturing space, right?
Rey: There is something interesting happening. There is increased communications between the manufacturing community and the design community. Many of the barriers have been overcome. This includes discussions to make the process more efficient. And so at least today, the industry is more aware and open to have a dialogue. Many years ago, to get the two sides together was impossible, because everyone was pre-occupied with one’s own worries. They refused to have a discussion. Right now, a dialogue is expected.

SMD: What DFM is needed in litho and other parts of the flow?
Rey: Right now, you see it in double patterning. You see it in the establishment of rules that bring more regularity in design. You see it with several types of things that extend traditional design rule checking. For example, you establish pattern matching techniques that essentially identify the patterns you can manufacture. You can use the information in a way that designs are efficiently done. Each one of these techniques brings all sorts of limitations and needs. But there is a willingness to bring the design and manufacturing communities to the table to discuss them.
Fujimura: Designers want more flexibility. For example, it seems like you should be able to use the techniques like what Tela Innovations is talking about and apply them to SOC designs.

SMD: It’s a cliché, but isn’t there more collaboration in the industry now?
Fujimura: That’s a trend. The whole ecosystem is collaborating together. Even competitors are working together, because the problem is so hard. Making sure the pie continues to grow is the number one issue. But it’s a tough shift. You start with competition. The mindset is if you tell your competitor what you’re doing, then it’s not going to work. But if you don’t talk to other people, then you can’t start the collaboration. If you don’t sell the idea that you have, and try to promote it in a public forum, you can’t make it go. You almost need your competitors to line up with what you are trying to do. That way the industry is working on one thing and investing enough in that. And that way it can actually happen on time.
Rey: A few years back, (IBM fellow) Bernie Meyerson made the point at a keynote at SPIE, where he showed the need for collaboration across the board. This included the process side for developing next-generation technologies, as well as the design side. There must be interaction between the two communities. And at that point, Intel was not that open. But clearly, the industry is moving in the right direction.
Enami: Collaboration is everything. Otherwise, nothing happens.

By Ed Sperling and Mark Lapedus
Despite hurdles in getting 28nm rolling and predictions that process technology will stick around for years to come, there appears to be rapidly growing interest in 20nm—at least from the design side.

This is significant for a couple reasons. First, for most companies 20nm will be the first encounter with double patterning because EUV still is not viable—and there is no clear timetable when it will be. And second, it’s just one process node away from where companies are expected to begin triple or quadruple patterning and using FinFETs to replace planar transistors. Rather than risk multiple changes at once, companies appear to be hedging their bets and dealing with one problem at a time.

“There’s a lot of anxiety about double patterning,” said Joe Sawicki, vice president and general manager of Mentor Graphics’ Design-to-Silicon Division. “There’s basically one license required for double patterning and we already have 20 paying customers. This is the first such blatant signal that companies are moving in this direction. It’s as aggressive a push as we saw at 28nm, plus a couple of new companies.”

Double patterning has its share of challenges for design teams. The pitch on each side is supposed to be divided in half, but deciding where to actually create the split in a design isn’t easy. Sawicki said it makes optical proximity correction far more complex—and more expensive. It takes almost twice as many processors to run the large file sizes for double patterning. And that’s just on the design side. On the manufacturing side, the shift from dummy fill to smart fill reduces the process variation, but add in process variation and an increasing number of corners and it gets still harder—and, once again, more expensive.

Follow the money
In April, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) raised its capital spending to the $8 billion-to-$8.5 billion range for this year. The new CapEx plan is a strong upward revision from the earlier plan to spend $6 billion for this year on capacity expansions.

As part of the plan, TSMC accelerated and pulled in the construction of a 20nm R&D process line. In terms of capital expenditures, TSMC will spend $1.3 billion to $1.5 billion on 28nm capacity expansions, $700 million on 20nm, $200 million on image sensor and embedded flash, and $100 million on its new turnkey 2.5D/3D chip stacking line.

“28nm is turning out to be a roaring success,” said Morris Chang, chairman and chief executive of TSMC, during a recent conference call. “In 20nm, the ramp up will be faster than 28nm.”

Therefore, at 20nm, Chang encouraged customers to engage with TSMC much earlier than previous process generations. TSMC’s move to accelerate its 20nm pilot line will allow the company to “shorten the learning cycle” for customers, Chang said.

TSMC has been ramping up 28nm for some time, with plans to move to early or “risk production” for the 20nm node by the end of 2012. The definitions of “risk” and “pilot” production vary from company-to-company and it’s unclear which foundry vendor is actually ahead at 20nm.

At 20nm, GlobalFoundries plans to move into risk production in the second half of this year, followed by volume production next year. “We have a very competitive 20nm offering following right on the heels of 32/28nm,” said Michael Noonen, senior vice president of worldwide sales and marketing at GlobalFoundries.

“It has been well endorsed by the marketplace because it is the most comprehensive, cost-effective platform in the industry,” he said. “Technology development is moving full-steam ahead and our Fab 8 in New York began running full-loop 20nm silicon in January. We have multiple active customer design activities with silicon delivery expected by 2H 2012.”

Samsung Electronics Co. plans to have 20nm qualified and ready for production in the second half of 2012. Rival United Microelectronics Corp. (UMC) will move into 20nm “pilot production” by mid-2013.

UMC recently broke ground for its 300mm Fab 12A Phase 5 and 6 complex, located in Tainan, Taiwan. Phase 5 and 6 will provide 28nm, 20nm, and 14nm capacity. The fab is scheduled to move in equipment during the second half of 2013.

In a statement, Stan Hung, chairman of UMC, said, “Cumulative CapEx for UMC’s Fab 12A phases 1-4 is projected to reach $8 billion, with P5 and P6 to add nearly $8 billion more. There are further plans for P7 and P8.”

In total, phase 5 and 6 has a cleanroom area of 53,000m2, about the size of 10 American football fields. The phases are expected to contribute 50,000 wafers per month, bringing total monthly design capacity for Fab 12A to 130,000 wafers. With the planned Phase 7 and 8, the eight phase fab complex will have a total design capacity of 180,000 wafers per month.

Mentor Graphics and Samsung Electronics said they have developed a complete design-for-manufacturing (DFM) sign-off reference solution for Samsung’s foundry customers based on the Calibre platform.

The DFM sign-off solution is available for consumer and telecommunications designs targeting advanced process nodes. Samsung has already released the Calibre kits to their customers for 32 nm and 28 nm, and has completed evaluation for 20 nm.

The components of the Calibre DFM platform at Samsung include the Calibre LFD product for litho simulation and hot spot pattern identification, the Calibre nmDRC and Calibre PM products for pattern-based design rule and hot spot checking and fixing, and the Calibre YieldAnalyzer product, which is used in conjunction with the Samsung manufacturing analysis deck for DFM scoring and critical area analysis (CAA).

“We have used Mentor’s 32/28 nm DFM solution on several advanced SoCs to reduce late-stage problems that could lead to delayed product releases or slower-than-expected yield ramp-up. We are currently working with Mentor to expand the DFM solution to 20 nm processes as well,” said Kee Sup Kim, vice president of Samsung’s Infrastructure Design Center.

“At advanced nodes, proper incorporation of DFM techniques can create a competitive edge for both foundries and fabless designers,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon Division at Mentor Graphics. “We are pleased to be working with Samsung on the Calibre platform to provide this competitive edge to our mutual customers.”

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: What’s the big challenge with 3D stacking from a DFM perspective?
Ramaswami: People want to put a couple of vias in the place of one because they don’t know if the first one is filled or not. What happens is you put a lot of strain on the transistors adjacent to them—5 microns, 10 microns or 15 microns away. In response to that, people want to shrink the via dimensions, but that’s not practical to fill. This is where design, manufacturing and design for manufacturing all come together. Right now the industry has a sweet spot around a 5 to 6 micron CD (critical dimension). Let’s get that working first before we move onto other dimensions.

SMD: How about testing of these stacked die?
Mason: We’re feeding design for manufacturability risk areas into the ATPG (automatic test pattern generation) flow. We’re informed by our analysis of the chip of what likely problem areas might be—stress, TSVs, lithographic hot spots, or strain-induced problems—and we feed those locations into the test pattern flow and they set up test vectors that are diagnostic against those problems. One of the solutions I see is heavier use of ATPG. If you have informed manufacturing people who can anticipate where the problems might be—and I think we can—then you can develop test methodologies targeted for those problems. That’s part of the answer.
Smayling: A big problem for test will be that these 3D chips are different functions. If you’re used to working with logic testers and now you’ve got DRAMs or NAND flash or mixed signal, do you call up three different test guys? It’s going to be a real nightmare to integrate test and to make it cost-effective.
Michaels: I agree that test will be a great challenge. The other fundamental issue is that failures at the stacked die level are extremely expensive. How you minimize failure and catch it upstream through probability of good die, through system disaggregation and choosing the right technology for the right chip will fundamentally have a big impact.

SMD: The cost escalates not just because of the design, but also because of a larger bill of materials, right?
Michaels: Absolutely. You’re throwing out multiple chips and the packaging for something that is likely a single chip or integration failure. You have to catch those early on in the process or it’s going to be extremely uneconomical.

SMD: Will we see more restrictive design rules as we move down Moore’s Law and into 3D?
Capodieci: The complex set of design rules that have been burdening the design manual since 65nm will be radically simplified. That does not mean designs will become simpler, though. They will become more regular. The problem with the complex set of design rules is they need to deal with a very large number of exceptions. When we have extremely regular functions, we’ll also be able to simplify the design rules. There’s been bad synergy between design rules and design when designers became more creative. We are now at a point where everything will become simpler, but new criteria will have to be introduced at the physical design level. What we’re looking at here are special constructs that violate the design rules but which achieve manufacturability.

SMD: But if we put die A on die B, we may be creating a bad die from two known good die, right?
Capodieci: That’s correct. We need to start thinking in 3D. The density is now an issue. What kind of thermal densities will we create? There will be rules for 3D, but they will be subsumed by the fact that we will start thinking about those rules in 2D, as well.
Michaels: Those issues exist today with differences in density. The super-linear growth in design rules was driven in part by trying to define what is not allowed. If you look at any hyperspace of design rules, it’s looking like Swiss cheese. You have to make the transition or flip to defining what is allowed. What patterns are allowed vs. what isn’t allowed? That’s a big change for designers, and it’s a way for foundries to help them make the best choices. At the leading edge you’re starting to see a closer partnership between the fabless companies and the foundries.

SMD: As we look at 3D and advanced 2D, there also is more rationalization to match functionality with what’s needed. Does it make sense to move analog IP to 14nm, for example. How are these changes affecting design?
Mason: If the 20nm node is going to cost you so many dollars per square millimeter of silicon, and 130nm or 180nm analog silicon running on depreciated capital equipment is going to cost you 10% or 1% of that, with proven yield, and you have a cost-effective way to integrate that with a 3D solution, it’s a very simple business problem. That assumes you have a way to do it and your architecture allows you that much decoupling of your analog systems. There are issues there. Sometimes a little bit of analog needs to be proximate to some other circuit. But we will take full advantage of the fact that we have this enormous analog infrastructure and digital infrastructure in the same company.
Ramaswami: Any new application is an opportunity, for sure. Having said that, this is the first time I’ve seen in a long time where a customer’s customer, a customer and Applied are all working together to see what can be done and what should not be done from a technical and a cost point of view.
Smayling: A regular design allows a surprising amount of integration of different functions. The tremendous improvement in variability of critical dimensions is something the analog engineers are interested in getting a piece of. That regularity can extend back to older technology nodes. The whole debate about regular design vs. 3D complex design is driven by people trying to sell supercomputers to do very complex point solutions to increasingly complex problems.
Mason: One of the reasons you do regular designs is you can certify them. They’re known to be good, and you can make aggressive decisions because you know what’s going to happen. But if GlobalFoundries has one set of regular designs, TSMC has another, UMC has another and SMIC has another one, how do you standardize all of this? It’s one thing to talk about regular designs in the IDM space, but when you’re talking about commoditized silicon manufacturing, I’m not sure how to do that.
Capodieci: The overall family of forbidden patterns is more a function of the technology and the technology node. We’re all dealing with the same wavelength and materials. The secret sauce lies not in a special solution. It is reasonable to imagine the patterns will overlap about 95%. The difference will be when we go to the esoteric stuff—more than Moore. That will have radically different shapes and the designs will be radically different. But as long as we keep pushing optical lithography, immersion and on to EUV, we’re going to see the same patterns.
Michaels: At the end of the day there are going to be differences driven by design rule choices, integration choices and material choices. You’re still going to want to maintain your designs at the physical layer. You’ll want to maintain your design requirements—your track height, your pin access, etc.—but fundamentally you’re going to have to do a port anyway. And porting may be easier in a pattern-based world than a design-based world.

SMD: As we push time to market in design, does yield get affected?
Michaels: The challenge of accelerating design is keeping the costs in line. If you look at complex SoCs, the amount of unique IP required on every chip is going up. The desire to re-use hard IP is much greater. The challenge is, what that IP is placed next to can have a strong impact on the parametric or functional unit. How you get to the point where you can re-use IP more effectively comes back to driving from the elimination of the unknown stuff.

SMD: What happens at 450mm? Does yield go up or down?
Michaels: The cost of a good die will go down.
Mason: Yes, and that’s the only thing that matters—cost.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: How good is the information exchange across the supply chain these days?
Capodieci: We need to push a lot of design information onto the manufacturing floor. This is a huge area. The EDA industry really needs to wake up and create a new set of flows. This is one of the most advanced industries in the world. We fabricate sophisticated devices without actually knowing what we’re fabricating. We ask for less-than-optimal information about where the critical issues are. New flows and new interfaces can be added to the manufacturing floor, respecting the IP and the proprietary nature of the design. But the information can be passed on to the manufacturing floor so it can be monitored and acted upon.

SMD: We’re not just creating hardware anymore. How does software affect yield, and is it even considered part of yield?
Michaels: If you look at the fabless sector, they’re hiring multiple software engineers per design engineer. It’s where a great deal of effort is going. But for our purposes, once you get past test and packaging and yield we tend to view it as the fabless problem. It’s not our market.
Mason: At TI we’re investing enormous resources in software and compilers that our customers use. It’s something we have to deliver to the ecosystem to use our products. We’re not using software to fix a yield problem. We’re typically not coupling the software with the fab yield problem right now. It’s more of a design enablement activity.

SMD: Will that change?
Mason: There’s more and more integration across the entire design space, and that includes software. Software is a critical part of what we do on the product side.
Capodieci: In the foundry space, we are still very active in doing esoteric R&D with universities. This is a little futuristic, but we have seen interesting research out of UCSD (University of California San Diego) on dark silicon, which is the silicon that does not get activated. We make it fully functional, but it is hardly used because of power issues. So there are software techniques and architectural techniques that go into making the best use and creating opportunistic cores. This is beyond our traditional field, but in the future we need to keep an eye on how the architectures will evolve with a focus on what needs to yield with a certain variability level and what needs to yield with a different variability level. This is an approach I call managed variability. Not all of the physical components react equally to the process. We need to be able to distribute this, but we need to know which components we’re building. This will be beyond 20nm.
Ramaswami: Most of our investments in software have been in three areas. One, of course, is process design. When you have very deep vias, you have diffusion of materials from the very top to the very bottom. A lot of the modeling has to be done in terms of concentration of gradients as well as mechanical agitation. The second area is around chamber control. When you have a multichip system, how do you measure the parameters? The feedback to the system becomes critical. An example is CMP, where you look to measure in real time the thickness of the materials and you control the polish rate. These get very critical with 10nm or 15nm films at the gate level. The third area is for inspection, where inspection and analysis are becoming a big deal at the wafer and at the mask level.

SMD: What happens with stacking of die and we have to drill holes in the silicon? Where are we now and where will be in a couple years?
Ramaswami: Most of these vias are made in the via-middle process, which is basically a blind via and done right after contact. You have the contact formation to do the blind via, you etch it, line it, and it’s all done. Or you assume it’s done, because you have no way of really knowing. Of course we can do some X-ray analysis at the full wafer level, but we only get ghost images of gray and white. It’s like looking at an ultrasound. You have to be a trained radiologist to figure out what it is. You’re sending the wafer on and putting faith in the rest of the logic line, which may be 10 or 20 layers, each one going through a heat cycle. You’re just hoping the via is in good shape at the very end, and you really don’t know until you do backside testing. In terms of mechanical yield and cross sections, we believe today that filling the via is not an issue as far as structural analysis is concerned. How well it is done electrically, with heat cycles, we just don’t know because data is limited. And often a different side of the fab—the packaging side—finds the data. That feedback loop takes a long time.
Capodieci: In terms of 3D, we’re a little bit behind—particularly with extraction. The problem becomes bigger, of course. But the process side is ahead of the curve. Still, it’s something that needs to be brought to fruition if we are going to bring 3D architectures to market.
Michaels: From the foundry standpoint you can’t completely test at the single-chip or wafer level. That will require the foundries to use more equipment data, more characterization, to find a probability to finding out how close they are to being in the center of the process. You may not be able to test exactly but you can clearly determine when should you scrap, etc. These new techniques of leveraging more data out of the fab than traditional metrology will become more important.
Smayling: In stacking, one of the opportunities for yield improvement stems from the fact that fab inspection traditionally has been on a surface. We’re going to have to think about how to inspect these stacked structures. It’s something we don’t have technology for today, but it’s going to be needed to drive these activities. For EDA, whether they’re stacked or not they’re going to be designed piece by piece. One of the biggest problems for EDA is that each of the pieces is done potentially at a different technology node. Now you’ve got a PDK that works with one version of verification software, a different PDK that works with a different version of verification software. And so when you stack these things together there’s no consistent environment for even doing verification. There is a big opportunity for verification to take on these kinds of issues.
Mason: There are lots of challenges with 3D. TI is right in the middle of those kinds of technologies because that’s the way the industry is heading. One issue that’s important in all of this is DFM. There are all kinds of mechanical stresses in this process, and these mechanical stresses have electrical implications. Where these TSVs are on the wafer relative to transistors and whether those are timing-critical circuits that are impacted by mechanical stresses has to be considered. There is research in this area now. We haven’t worried about these DFM issues in the past, but we will have to.

SMD: What kinds of mechanical stresses?
Mason: Where you physically change the silicon and that has an electrical effect. If you take a chip and macroscopically bend it, that affects the speed of transistors because of the electrical impact of that strain. When you’re doing that locally, you can change the timing of that circuit and break the circuit. That can happen because you’re putting a through-silicon via there that you didn’t simulate.

SMD: Stacking in 2.5D seems much more straightforward compared to full 3D stacking. Which one will come out first and why?
Ramaswami: I think 2.5D is much simpler. But we see the end market today driven by mobile devices, which requires a DRAM stack on top of a logic chip. That clearly does not lend itself to 2.5D or interposer technology. So we need to get that working, no matter what. The questions we’re getting now on 2.5D is how to make the interposer more active rather than just having a piece of silicon with lines through it. Putting more capacitors and inductors on them is an area we’re beginning to pursue with a couple of universities.