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Posts Tagged ‘device’

2D Materials May Be Brittle

Tuesday, November 15th, 2016

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By Ed Korczynski, Sr. Technical Editor

International researchers using a novel in situ quantitative tensile testing platform have tested the uniform in-plane loading of freestanding membranes of 2D materials inside a scanning electron microscope (SEM). Led by materials researchers at Rice University, the in situ tensile testing reveals the brittle fracture of large-area molybdenum diselenide (MoSe2) crystals and measures their fracture strength for the first time. Borophene monolayers with a wavy topography are more flexible.

A communication to Advanced Materials online (DOI: 10.1002/adma.201604201) titled “Brittle Fracture of 2D MoSe2” by Yinchao Yang et al. disclosed work by researchers from the USA and China led by Department of Materials Science and NanoEngineering Professor Jun Lou at Rice University, Houston, Texas. His team found that MoSe2 is more brittle than expected, and that flaws as small as one missing atom can initiate catastrophic cracking under strain.

“It turns out not all 2D crystals are equal. Graphene is a lot more robust compared with some of the others we’re dealing with right now, like this molybdenum diselenide,” says Lou. “We think it has something to do with defects inherent to these materials. It’s very hard to detect them. Even if a cluster of vacancies makes a bigger hole, it’s difficult to find using any technique.” The team has posted a short animation online showing crack propagation.

2D Materials in a 3D World -222

While all real physical things in our world are inherently built as three-dimensional (3D) structures, a single layer of flat atoms approximates a two-dimensional (2D) structure. Except for special superconducting crystals frozen below the Curie temperature, when electrons flow through 3D materials there are always collisions which increase resistance and heat. However, certain single layers of crystals have atoms aligned such that electron transport is essentially confined within the 2D plane, and those electrons may move “ballistically” without being slowed by collisions.

MoSe2 is a dichalcogenide, a 2D semiconducting material that appears as a graphene-like hexagonal array from above but is actually a sandwich of Mo atoms between two layers of Se chalcogen atoms. MoSe2 is being considered for use as transistors and in next-generation solar cells, photodetectors, and catalysts as well as electronic and optical devices.

The Figure shows the micron-scale sample holder inside a SEM, where natural van der Waals forces held the sample in place on springy cantilever arms that measured the applied stress. Lead-author Yang is a postdoctoral researcher at Rice who developed a new dry-transfer process to exfoliate MoSe2 from the surface upon which it had been grown by chemical vapor deposition (CVD).

Custom built micron-scale mechanical jig used to test mechanical properties of nano-scale materials. (Source: Lou Group/Rice University)

The team measured the elastic modulus—the amount of stretching a material can handle and still return to its initial state—of MoSe2 at 177.2 (plus or minus 9.3) gigapascals (GPa). Graphene is more than five times as elastic. The fracture strength—amount of stretching a material can handle before breaking—was measured at 4.8 (plus or minus 2.9) GPa. Graphene is nearly 25 times stronger.

“The important message of this work is the brittle nature of these materials,” Lou says. “A lot of people are thinking about using 2D crystals because they’re inherently thin. They’re thinking about flexible electronics because they are semiconductors and their theoretical elastic strength should be very high. According to our calculations, they can be stretched up to 10 percent. The samples we have tested so far broke at 2 to 3 percent (of the theoretical maximum) at most.”

Borophene

“Wavy” borophene might be better, according to finding of other Rice University scientists. The Rice lab of theoretical physicist Boris Yakobson and experimental collaborators observed examples of naturally undulating metallic borophene—an atom-thick layer of boron—and suggested that transferring it onto an elastic surface would preserve the material’s stretchability along with its useful electronic properties.

Highly conductive graphene has promise for flexible electronics, but it is too stiff for devices that must repeatably bend, stretch, compress, or even twist. The Rice researchers found that borophene deposited on a silver substrate develops nanoscale corrugations, and due to weak binding to the silver can be exfoliated for transfer to a flexible surface. The research appeared recently in the American Chemical Society journal Nano Letters.

Rice University has been one of the world’s leading locations for the exploration of 1D and 2D materials research, ever since it was lucky enough to get a visionary genius like Richard Smalley to show up in 1976, so we should expect excellent work from people in their department of Materials Science and NanoEngineering (CSNE). Still, this ground-breaking work is being done in labs using tools capable of handling micron-scale substrates, so even after a metaphorical “path” has been found it will take a lot of work to build up a manufacturing roadway capable of fabricating meter-scale substrates.

—E.K.

Memristor Variants and Models from Knowm

Friday, January 22nd, 2016

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By Ed Korczynski, Sr. Technical Editor

Knowm Inc. (www.knowm.org), a start-up pioneering next-generation advanced computing architectures and technology, recently announced the availability of two new variations of memristors targeting different neuromorphic applications. The company also announced raw device data available for purchase to help researchers develop and improve memristor models. These new Knowm offerings enable the next step in the R&D of radically new chips for pattern-recognition, machine-learning, and artificial intelligence (AI) in general.

There is general consensus between industry and academia and government that future improvements in computing are now severely limited by the amount of energy it takes to use Von Neumann architectures. Consequently, the US Whitehouse has issued a grand challenge with the Energy-Efficient Computing: from Devices to Architectures (E2CDA) program (http://www.nsf.gov/pubs/2016/nsf16526/nsf16526.htm) actively soliciting proposals through March 28, 2016.

The Figure shows a schematic cross-section of Knowm’s memristor devices—with Tin (Sn) and Chromium (Cr) metal layers as the new options to tungsten (W)—along with the device I/V curves for each. “They differ in their activation threshold,” explained Knowm CEO and co-founder Alex Nugent in an exclusive interview with Solid State Technology. “As the activation thresholds become smaller you get reduced data retention, but higher cycle endurance. As that threshold increases you have to dissipate more energy per event, and the more energy you dissipate the faster it will burn-out.” Knowm’s two new memristors, as well as the company’s previously announced device, are now available as unpackaged raw dice with masks designed for research probe stations.

Figure: Schematic cross-section of Knowm’s memristor devices using Tin (Sn) or Chromium (Cr) or tungsten (W) metal layers, along with the device I/V curves for each. (Source: Knowm)

Knowm is working on the simultaneous co-optimization of the entire “stack” from memristors to circuit architectures to application-specific algorithms. “The potential of memristors is so huge that we are seeing exponential growth in the literature, a sort of gold rush as engineers race to design new circuits and re-envision old circuits,” commented Knowm CEO and co-founder Alex Nugent. “The problem is that in the race to publish, circuit designers are adopting models that do not adequately describe real devices.” Knowm’s raw data includes AC, DC, pulse response, and retention for different memristors.

Additional memristors are being developed by Knowm’s R&D lab partner Dr. Kris Campbell of  Boise State University (http://coen.boisestate.edu/kriscampbell/), using different metal layers to achieve different activation thresholds beyond the three shown to date. “She has discovered an algorithm for creating memristors along this dimension,” said Nugent. “From a physics perspective it makes sense that there would be devices with high cycle endurance but reduced data retention.”

“In the future what I image is a single chip with multiple memristors on it. Some will be volatile and very fast, while others will be slow,” continued Nugent. “Just like analog design today uses different capacitors, future neuromophic chips would likely use memristors optimized for different changes in adaptation threshhold. If you think about memristors as fundamental elements—as per Leon Chua (https://en.wikipedia.org/wiki/Leon_O._Chua)—then it makes sense that we’ll need different memristors.”

The applications spaces for these devices have intrinsically different requirements for speed and retention. For example, to exploit these devices for pattern recognition and/or anomaly detection (keeping track of confidence in making temporal predictions) it seems best to choose relatively high activation thresholds because the number of operations is unlikely to burn-out devices. Conversely, for circuits that constantly solve optimization problems the best memristors would require low burn-out and thus low activation thresholds. However, analog applications are generally problematic because the existing memristors leak current, such that stored values degrade over time.

Knowm is shipping devices today, mostly to university researchers, and has tested thousands of devices itself. The Knowm memristors can be fabricated at <500°C using industry-standard unit-process steps, allowing for eventual integration with silicon CMOS “back-end” metallization layers. While still in early R&D, this technology could provide much of the foundation for post-Moore’s-Law silicon ICs.

—E.K.

EMC2015 – New Devices, Old Tricks

Tuesday, June 30th, 2015

By Ed Korczynski, Sr. Technical Editor

The 57th annual Electronic Materials Conference (http://www.mrs.org/57th-emc/), held June 24-26 in Columbus, Ohio, showcased research and development (R&D) of new device structures, as well as new insights into the process-structure-properties relationships of electronic devices now running in high-volume manufacturing (HVM) lines globally. A plethora of papers on compound-semiconductor quantum-dots and nanorods, LEDs and quantum-dot detectors, power electronics, and flexible and bio-compatible devices all show that innovation will not slow down despite the limitations of Dennard Scaling and Moore’s Law. With 3D stacking of existing devices on novel substrates an ongoing integration challenge for HVM, the conference also explored substrate engineering and 3D stacking technologies.

CEA-Leti’s “Smart-cut” technology has been used for over 20 years to cleave crystalline layers for transfer and bonding to stack substrate functionalities, such as Silicon-On-Insulator (SOI) wafers. Researchers from Leti looked at the discrete steps involved in the hydrogen implantation, annealing to create the buried plane of micro-bubbles within the crystal, and then the acoustic wave that travels through the plane to complete the cleave. A periodic wave pattern is dynamically generation during cleaving, with the evolving wavefront dependent upon the contribution of all the past fracture fronts to any particular point. The cleaved roughness is related to the speed of the fracture wave moving through the wafer plane, and that depends on the micro-cracks the are originally present due to the micro-bubbles.

Leti researchers also reported on “Copper grain-size effects on direct metallic bonding mechanisms” such as will be used in 3D chip-stacking. The main limitation on the density of 3D copper (Cu) connections between chips is the micro-bump pitch, with Cu-Cu bonds providing both electrical and mechanical connections. Since the grain-size of annealed Cu thin-films depends on film thickness, they used electro-chemical deposition (ECD) to grow two different thicknesses, annealed each at 400°C for 10 hours to allow for maximum grain growth, and then used CMP to get all samples to the same final thickness. The result was fine-grain Cu bumps with 0.6 micron diameter grains, and large-grain bumps with ~2.1 micron diameter grains. With no post-bond-anneal there was significant improvement in bonding strength with fine-grain-structure Cu compared to large-grains, but with post-bond-anneals up to 300°C the grain-size effect was reduced such that all samples approaching the same high levels of bond strength. However, 400°C annealing resulted in a newly observed voiding phenomenon between the Cu and TiN barrier layers, with more voids associated with finer-grains.

Artificial Neural Networks

Researchers from Sandia Labs showed data on multi-level data storage using memristors. Lacking repeatable processes to manufacture memristors, people have used SRAM arrays to build the first Artificial Neural Networks (ANN) such as those commercialized by NeuroMem Inc. However, models indicate that changing from SRAM- to memristor-arrays would reduce power by 16x and chip area by 6x (assuming 25,600 elements). Sandia has been working with TaOx (where 3 < x < 5) as the memristor switching layer, and has been able to show up to 5 discrete High Resistance States (HRS) to be able to do multi-bit storage in a single cell. For multilevel switching, the standard deviation of a target resistance increases with increasing resistance (not with the magnitude of the resistance change). However, each cell was only cycled 25-50 times, so reliability/wear-out has not yet been explored.

IBM Almaden Labs began work on Phase-Change Memory (PCM) with Macronix and Qimonda in 2004, and recently have explored PCM to build ANN. They sacrifice density and double up the artificial synapses to separately encode excitory and inhibitory functions. In PCM it is easy to slowly step up the High-Resistance State (HRS) levels since a crystalline plug is the Low Resistance State (LRS) and gradual crystallization of the edges of the plug gradually increases resistance, while reset back to LRS either happens on doesn’t across the entire plug so there is an inherently asymmetrical response. For Resistance RAM (ReRAM) structures there is opposite asymmetry in that the conductive filament either forms or doesn’t, while reset to LRS can happen gradually. These asymmetries  in the inherent dynamic responses of artificial synapses result in problems for learning/programming of ANN since ideal learning calls for slight increases and decreases in resistances.

—E.K.