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Posts Tagged ‘device architecture’

XPoint NVM Array Process Engineering

Wednesday, October 18th, 2017

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By Ed Korczynski, Sr. Technical Editor

Now that TECHINSIGHTS has published a teardown of a 3D XPoint array, we have seen cross-section transmission electron micrographs (TEM) of the device. From first principles of process engineering, we can make educated guesses as to the process flows and challenges in creating this type of non-volatile memory (NVM) integrated circuit (IC). Evolution of device technology over more than fifteen years has resulted in cross-point arrays connecting precise stacks of chalcogenide materials. Intel with “Optane” and Micron with “QuantX” branded ICs can now claim success in commercializing what has always looked good in R&D but was notoriously difficult to make in high-volume manufacturing (HVM).

Figure 1 shows the TEM cross-section, parallel to the wordline direction, of a XPoint memory cell array taken from an Intel Optane product. There are two levels of cross-point cell-stacks, connected in the middle by bitlines (orthogonal to the wordlines). The upper- and lower-wordlines have been analyzed as tungsten (W) metal with tungsten-nitride (WN) barriers. The memory cell material is a variant on a germanium-antimony-teluride (GeSbTe or “GST”) chalcogenide glass, while the selector material is made with arsenic-silicon-germanium-selenide.

Fig. 1: Cross-section TEM of Intel XPoint NVM array in the wordline direction, showing two levels of memory cell stacks separated by bitline arrays. (Source: greyscale image by TechInsights, color commentary by Ed Korczynski)

Details about the device architecture and memory circuitry are included in the Solid State Technology online blog post by TechInsights’ senior technical fellow Dr. Jeongdong Choe, “Comparing XPoint memory architecture with NAND and DRAM products”. In his presentation at the 2017 Flash Memory Summit, Choe disclosed that the composition of the memory material is Ge0.12Sb0.29Te0.54:Si0.05 and the selector material is As0.29Si0.17Ge0.10Se0.44 while there have been no public mentions yet of what materials are used as buffers to electrodes.

As explained in the Ed’s Threads blog post on June 22nd of this year under the title “PCM + ReRAM = OUM as XPoint,” there has been confusion regarding used of Phase-Change Memory (PCM) material in a device that has a completely different architecture, different switching mechanism, and different performance than what are now known as standard PCM ICs. In standard PCM chips, high current-flow through a bit cell heats up a small mass of material until it changes phase (from crystalline to amorphous or vice-versa). In XPoint arrays, a small current-flow through a bit cell causes ions and atoms to re-arrange following voltage potentials until it changes resistivity, while it is not yet public knowledge how much change happens in material phase. Intel has said that the resistance change is not due to conductive “filament” formation in the GeSbTe:Si but due to some change in the “bulk” of the material.

Processing Speculations

From a HVM perspective, all cross-bar memory architectures share similar constraints and opportunities to design for relatively low-cost and high-yield:

1)     Use PVD blanket layers of complex material stacks as memory and selector and buffers,

2)     Use lithography to mask memory cells in a regular two-dimensional array,

3)     Use ion-beam or chemically-neutral plasma to etch pillars of complex material stacks,

4)     Use ALD/CVD and spin-on-dielectrics to gap-fill electrical isolation around pillars, and

5)     Use dielectric CMP to prepare for metal deposition.

Physical Vapor Deposition (PVD) or “sputtering” processing is based on sublimating a solid material “target” inside a vacuum chamber, which provides a relatively fast and inexpensive way to coat surfaces. Thickness uniformity is typically excellent wafer-to-wafer, while within-wafer uniformity is controlled by process chamber and target geometries. The major concern with PVD using multi-component targets—such as the four element GeSbTe:Si—is that different elements sublimate at different rates such that targets “age” and experience slight predictable composition changes over time. PVD target aging can be compensated for by cleverly varying the ratio of the different elements through the thickness of the target.

When integrating PCM materials into NVM devices, the ability to use a blanket 2D PVD deposition is an inherent advantage over ALD into nano-scale 3D features:  faster, cheaper, and potentially more repeatable if target aging can be managed. Patterning of the memory cell stack requires excellent control over ion directionality to prevent sidewall erosion within the material stack. As can be seen in Figure 1, the sidewalls of the GST:Si are slightly recessed from the thin dark layers directly above and below, indicating a well-controlled process with relatively higher removal rate during etching/milling.

Dielectric gap-fill into what appears to be ~10:1 aspect-ratio features is certainly one of the integration challenges of this process flow. The cross-section shows at least one conformal barrier layer is used in the dielectric isolation between array elements and between bitlines. Dielectric ALD is likely used for barrier formation, while spin-on dielectric (SOD) technology likely provides the gap-filling capability. If the metal interconnects for the CMOS circuitry below the array are built using copper, then a 400°C upper limit on process temperatures would be required for all array fabrication.

Future R&D

Milind Weling, expert in materials/device innovation and senior vice president of programs and operations for Intermolecular, presented at the 2017 Flash Memory Summit on the company’s ability to accelerate the pace of R&D experimentation for the complex materials stacks needed in XPoint memory arrays. In an exclusive interview with SemiMD, Weling discussed the inherent challenges of finding the ideal material within a multi-element compositional space.

“We’ve been working on selectors, and a single-element material is almost useless. What you need is at least a binary, maybe a quaternary, and some people experiment with targets composed of up to seven elements! Once we find a composition that is interesting in our R&D tool, our customers create large targets for their HVM tools.” Figure 2 shows a wafer with 28 isolated circular regions within which different PVD compositions can be independent controlled in a custom R&D tool made by Intermolecular. This tool allows a complete design-of-experiments within a ternary compositional space to be run on a single 300mm-diameter silicon wafer.

Fig. 2: Site-isolated circular regions on a 300-mm silicon wafer A) can each have a different composition within B) a ternary phase diagram when deposited in a special PVD R&D tool. Chalcogenide alloys explored as memory and selector materials in cross-bar NVM arrays may have more than three elements. (Source: Intermolecular)

The materials stack is necessarily complex to be able to form chalcogenide-based NVM cells, and even more complex when buffers are added to allow for integration with CMOS-compatible materials. “Each memory cell is two electrodes sandwiching a GST-type of material, and the selector is two electrodes with one ‘magic’ layer,” explained Weling. “Except for the novel ‘magic’ selector, most of the other materials used in the stack have precedent as unit-process steps in HVM of DRAM or NAND. The difficulty is in tuning the compositions of all layers simultaneously.”

—E.K.

[DISCLOSURE:  Ed Korczynski has no ongoing business relationship with nor owns any equity in Intermolecular.]

ARM debuts embedded architecture, new 64-bit processor

Tuesday, November 10th, 2015

By Jeff Dorsch, Contributing Editor

November 10, 2015 — ARM Holdings today is introducing the ARMv8-M architecture for embedded devices and the ARM Cortex-A35 64-bit processor as the company opens the annual ARM TechCon conference and exposition in Santa Clara, Calif.

Advanced RISC Machines Ltd. was established 25 years ago this month as a joint venture among Acorn Computers, Apple Computer (now Apple), and VLSI Technology. The company changed its name to ARM Ltd. in 1998 and went public as ARM Holdings on the London Stock Exchange and NASDAQ.

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ARM CEO Simon Segars

At this week’s ARM TechCon event, attendees will hear keynote addresses by CEO Simon Segars and Chief Technology Officer Mike Muller. There will be presentations by Google, Oracle, and Twentieth Century Fox on the main stage of the conference. ARM TechCon runs through Thursday, November 12, at the Santa Clara Convention Center.

The ARMv8-M architecture is intended to address “the growing billions of endpoint devices” in the Internet of Things, says Nandan Nayampally, vice president of marketing for ARM’s CPU Group. It encompasses providing the ARM TrustZone security technology for IoT devices, which will work in concert with TrustZone CryptoCell and AMBA 5 AHB5 to secure ultra-low-power systems.

Device integrity is the goal of the embedded architecture, according to Nayampally. “We need every component along the chain to be secure,” he says.

In addition to device integrity, ARM aims to provide lifecycle security and communication security, Nayampally adds.

“The baseline for all this is trusted hardware,” Nayampally says. “TrustZone has been very successful; it’s been around for a decade.”

ARMv8-M targets Cortex-M embedded processors, he notes. The new architecture aims at “microcontrollers up to the smartphone generation and to the enterprise,” Nayampally says.

For the benefit of embedded-device developers, “you have to be real-time,” Nayampally says. “You have to be really small. We cannot compromise on that.”

ARMv8-M will be supported by a number of third-party tool suppliers, including Mentor Graphics, Micrium, Green Hills Software, and Symantec.

The ARM Cortex-A35 processor has already been licensed to multiple customers and will be found in devices by the end of next year, says Ian Smythe, director of marketing programs for the CPU Group. “Each partner will announce on their own schedule,” he adds.

The 64-bit processor is “targeted at mobile,” Smythe says. Half of smartphones shipped this year will include chips with the ARMv8-A architecture, he notes. ARM and Gartner are predicting 1 billion entry-level smartphones will ship in 2020, as the entry-level smartphone market enjoys a compound annual growth rate of 8 percent.

The Cortex-A35 consumes 10% less power than the Cortex-A7, according to Smythe, and offers performance improvements of 6 percent to 40 percent in various functions.

Compared with the Cortex-A53 processor, the Cortex-A35 has a 25 percent smaller core, 32 percent lower power consumption, and 25 percent greater efficiency, Smythe says. ARM touts the Cortex-A35 as an ultra-high-efficiency processor, suitable to succeed the Cortex-A5 and Cortex-A7 in entry-level smartphones.

“The ARM Cortex-A35 processor brings efficient, secure 64-bit processing to the next billion smartphones,” Smythe concludes.

ARM CTO looks forward and backward in keynote

Tuesday, November 10th, 2015

UPDATE 15 December 2015: Minor changes made to reflect correct ARM product nomenclature.

By Jeff Dorsch, Contributing Editor

“Innovation is still thriving in semiconductors,” said Mark Muller, chief technology officer of ARM Holdings, in a keynote address Tuesday morning (November 10) at the ARM TechCon conference and exposition in Santa Clara, Calif.

“We’ve always had constraints on what we can do,” he added. Still, “there’s an incredible amount of innovation ahead of us.”

ARM CTO Mike Muller describes the company's strategy, upside in server opportunities, and technology's march towards the IoT.

With ARM marking its 25th anniversary this month, Muller briefly reviewed the history of the company and the technology that preceded its establishment, harking back to the BBC Micro Model A/B computer of 1981 and the 1985 introduction of the ARM1 processor. The BBC Micro has ultimately led to this year’s introduction of the BBC micro:bit single-board computer, which is being provided for free to 10-year-old and 11-year-old schoolchildren in the United Kingdom.

Muller talked about ARM’s progress in getting its designs into server chips, with “multiple manufacturers” shipping ARM-based servers, he noted. Such servers are being implemented at the Barcelona Supercomputing Center in Spain and at Sandia National Laboratories, Muller said.

Moving on, Muller said, “Mobile computing has been transformed.” While the annual growth rate of mobile devices is expected to decline to 10 percent by 2020, such “not bad” growth will primarily be coming from entry-level smartphones by the end of the decade, he added.

The CTO touted “a truly remarkable product,” the ARM Cortex-A35 processor, being introduced at this week’s conference. Chips with that processor design will be able to run on less than 6 milliwatts, he said.

At the same time, Muller said of ARM’s product strategy, “It’s so much more than processors.” The company aspires to provide “all of the IP [intellectual property] you need,” he said to the designers in attendance.

Muller enthused about what he called “the product of the year,” an energy-harvesting Bluetooth Low Energy insulin pen designed by Cambridge Consultants, incorporating a Dialog Semiconductor chip. The KiCoPen concept has no battery, he noted. Using piezoelectric technology, it derives its energy from the injector cap being removed from the pen.

The ARM executive also addressed the security issue with the Internet of Things and related products. “We’re under attack in a way we never were before,” Muller said.

“How do we make a $1 microcontroller design done by people with no security experience, secure?” he asked.

ARM also introduced the TrustZone CryptoCell security technology this week, along with its ARMv8-M architecture for embedded devices.

“The hardware is the easy part,” Muller commented. With the IoT, there are familiar problems in chip and system design, “times trust,” he said.

“You have to be able to secure them,” Muller said of IoT devices. “You share that trust around you.”

Research Alert: August 12, 2014

Tuesday, August 12th, 2014

SRC, UC Davis explore new materials and device structures to develop next-generation “Race Track Memory” technologies

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

Notre Dame paper offers insights into a new class of semiconducting materials

A new paper by University of Notre Dame researchers describes their investigations of the fundamental optical properties of a new class of semiconducting materials known as organic-inorganic “hybrid” perovskites.

The research was conducted at the Notre Dame Radiation Laboratory by Joseph Manser, a doctoral student in chemical and biomolecular engineering, under the direction of Prashant Kamat, Rev. John A. Zahm Professor of Science. The findings appear in a paper in the August 10 edition of the journal Nature Photonics.

The term “perovskites” refers to the structural order these materials adopt upon drying and assembling in the solid state.

“Hybrid perovskites have recently demonstrated exceptional performance in solid-state thin film solar cells, with light-to-electricity conversion efficiencies approaching nearly 20 percent,” Manser said. “Though currently only at the laboratory scale, this efficiency rivals that of commercial solar cells based on polycrystalline silicon. More importantly, these materials are extremely easy and cheap to process, with much of the device fabrication carried out using coating and or printing techniques that are amenable to mass production. This is in stark contrast to most commercial photovoltaic technologies that require extremely high purity materials, especially for silicon solar cells, and energy-intensive, high-temperature processing.”

Manser points out that although the performance of perovskite solar cells has risen dramatically in only a few short years, the scientific community does not yet fully know how these unique materials interact with light on a fundamental level.

Manser and Kamat used a powerful technique known as “transient absorption pump-probe spectroscopy” to examine the events that occur trillions of a second after light absorption in the hybrid methylammonium lead iodide, a relevant material for solar applications. They analyzed both the relaxation pathway and spectral broadening in photoexcited hybrid methylammonium lead iodide and found that the excited state is primarily composed of separate and distinct electrons and holes known as “free carriers.”

“The fact that these separated species are present intrinsically in photoexcited hybrid methylammonium lead iodide provides a vital insight into the basic operation of perovskite solar cells,” Manser said. “Since the electron and hole are equal and opposite in charge, they often exist in a bound or unseparated form known as an ‘exciton.’ Most next-generation’ photovoltaics based on low-temperature, solution-processable materials are unable to perform the function of separating these bound species without intimate contact with another material that can extract one of the charges. ”

This separation process siphons energy within the light absorbing layer and restricts the device architecture to one of highly interfacial surface area. As a result, the overall effectiveness of the solar cell is reduced.

Pairing old technologies with new for next-generation electronic devices

UCL scientists have discovered a new method to efficiently generate and control currents based on the magnetic nature of electrons in semiconducting materials, offering a radical way to develop a new generation of electronic devices.

One promising approach to developing new technologies is to exploit the electron’s tiny magnetic moment, or ‘spin’. Electrons have two properties – charge and spin – and although current technologies use charge, it is thought that spin-based technologies have the potential to outperform the ‘charge’-based technology of semiconductors for the storage and process of information.

In order to utilise electron spins for electronics, or ‘spintronics’, the method of electrically generating and detecting spins needs to be efficient so the devices can process the spin information with low-power consumption. One way to achieve this is by the spin-Hall effect, which is being researched by scientists who are keen to understand the mechanisms of the effect, but also which materials optimise its efficiency. If research into this effect is successful, it will open the door to new technologies.

The spin-Hall effect helps generate ‘spin currents’ which enable spin information transfer without the flow of electric charge currents. Unlike other concepts that harness electrons, spin current can transfer information without causing heat from the electric charge, which is a serious problem for current semiconductor devices. Effective use of spins generated by the spin-Hall effect can also revolutionise spin-based memory applications.

The study published in Nature Materials shows how applying an electric field in a common semiconductor material can dramatically increase the efficiency of the spin-Hall effect which is key for generating and detecting spin from an electrical input.

The scientists reported a 40-times-larger effect than previously achieved in semiconductor materials, with the largest value measured comparable to a record high value of the spin-Hall effect observed in heavy metals such as Platinum. This demonstrates that future spintronics might not need to rely on expensive, rare, heavy metals for efficiency, but relatively cheap materials can be used to process spin information with low-power consumption.

As there are limited amounts of natural resources in the earth and prices of materials are progressively going up, scientists are looking for more accessible materials with which to develop future sustainable technologies, potentially based on electron spin rather than charge. Added to this, the miniaturization approach of current semiconductor technology will see a point when the trend, predicted by Moore’s law, will come to an end because transistors are as small as atoms and cannot be shrunk any further. To address this, fundamentally new concepts for electronics will be needed to produce commercially viable alternatives which meet demands for ever-growing computing power.

Research Alert: Jan. 7, 2014

Tuesday, January 7th, 2014

SRC launches industry consortium, partners with NSF to research trustworthy and secure semiconductors and systems

The growing scale and complexity of information networks and embedded systems, and our increasing reliance upon them, are accompanied by challenges and risks.  Are the networks and systems on which we depend trustworthy and secure?  Are they resistant to unintended access, tampering and counterfeiting?

The Semiconductor Research Corporation announced the launch of the The Trustworthy and Secure Semiconductors and Systems (T3S) initiative, to focus on developing strategies, techniques, and tools to provide assurance that electronic systems will perform as intended. Such assurance is a function of processes and tools integrated across all steps of design, manufacture, and distribution.  In order to build a technological foundation that business and government can use to make systems that are trustworthy and secure, there is a need for fundamental, multidisciplinary research that spans architecture, design and manufacture.

T3S is an industry consortium that partners with government agencies to fund university research — building and coordinating an academic network, generating new ideas and understanding, and providing a pipeline of relevantly educated talent. Member companies set the research agenda and get early and easy access to research and researchers, while leveraging their investment.

Work on growth of novel materials and structures

Imagine that you could combine materials with different properties into new heterostructures with a vast range of designer properties. Now imagine what you could create.

“What I am looking for is something that is unique, something that you might not be able to do anything with now. We are trying to solve technological problems. I don’t necessarily know what the final product will be. It might be something that no one has thought of yet. That is the only way you can beat a well-established technology,” said Chris Palmstrom, a professor of electrical and computer engineering materials at the University of California Santa Barbara.

Palmstrom fabricates new heterostructures using electronic, magnetic, and mechanical properties of dissimilar materials, as he explained to a group of 65 people at a Physics and Astronomy Department Colloquium entitled Growth of Novel Materials and Structures at Ohio University in September.

“We are trying to combine different materials, things like metals and semiconductors to make structures with new properties. If I have a metal and a semiconductor, I am going to put the two together as layers and composites to see what structures and properties I can obtain,” he said.

Palmstrom has used molecular beam epitaxial growth, in combination with in-situ and ex-situ atomic level characterization techniques, to investigate the growth of epitaxial metals on semiconductors and metal oxides, Heusler alloys, and rare earth monopnictides, which have been used to optimize properties of these heterostructures for semiconductor spintronics, thermoelectric, and shape memory applications. Palmstrom’s work relies heavily on both theoretical work and experimentation. He often combines dissimilar materials with a specific application in mind, but the results can fall outside of his expectations.

“We have a plan or an idea on what would happen. We have a lot of curiosity. Then we do experiments to try to verify our ideas about what would happen. With some of our experiments, we have no idea what is going to happen. There is no theory. Then it is a matter of going back and trying to understand why it happened,” Palmstrom said.

New center to lead Purdue efforts in computational nanotechnology, materials and devices development

The devices and technologies of the future will only be as good as the materials used to make them – and that’s part of the problem. A new Purdue University research center hopes it can be a leader in finding solutions.

The Purdue Center for Predictive Materials and Devices (c-PRIMED) and its focus on modeling for materials engineering dovetails with the national Materials Genome Initiative (MGI). Announced by President Barack Obama in 2011, this federal initiative will concentrate on developing methods to double the speed and halve the cost of creating new advanced materials.

Purdue’s nanoHUB.org, developed by the Network for Computational Nanotechnology and arguably the world’s largest nanotechnology user facility, is highlighted in the White House’s National Science and Technology Council report in June 2011 that paved the way for the MGI.

The 18-page report, titled Materials Genome Initiative for Global Competitiveness, says: “Accelerating the pace of discovery and deployment of advanced material systems will, therefore, be crucial,” adding, “Open innovation will play a key role in accelerating the development of advanced computational tools.” The council’s report goes on to say, “An existing system that is a good example of a first step toward open innovation is the nanoHUB.”

“c-PRIMED represents a continuation and a deepening of ongoing Purdue research efforts through nanoHUB.org,” said Gerhard Klimeck, a professor of electrical and computer engineering.

The new Discovery Park research center, part of $12 million in new investment by Purdue’s research infrastructure, is led by Klimeck and Alejandro Strachan, a professor of materials engineering. Other Purdue investment efforts in this area include Conte, the nation’s fastest university-owned supercomputer; and the Center for Prediction of Reliability, Integrity and Survivability of Microsystems (PRISM).

“Our efforts will focus on ways to accelerate the time it takes to introduce advanced materials to the marketplace for everything from airplane wings, solar cells and electronic devices to packaging that keeps food fresher,” Klimeck said. “That’s the dream behind c-PRIMED – and it’s more attainable now.”

Solid State Watch: Nov. 15-22, 2013

Friday, November 22nd, 2013
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Research News: Oct. 29, 2013

Tuesday, October 29th, 2013

ASU, Georgia Tech create breakthrough for solar cell efficiency

Crystals are at the heart of diodes. Not the kind you might find in quartz, formed naturally, but manufactured to form alloys, such as indium gallium nitride or InGaN. This alloy forms the light emitting region of LEDs, for illumination in the visible range, and of laser diodes (LDs) in the blue-UV range.

Research into making better crystals, with high crystalline quality, light emission efficiency and luminosity, is also at the heart of studies being done at Arizona State University by Research Scientist Alec Fischer and Doctoral Candidate Yong Wei in Professor Fernando Ponce’s group in the Department of Physics.

In an article recently published in the journal Applied Physics Letters, the ASU group, in collaboration with a scientific team led by Professor Alan Doolittle at the Georgia Institute of Technology, has just revealed the fundamental aspect of a new approach to growing InGaN crystals for diodes, which promises to move photovoltaic solar cell technology toward record-breaking efficiencies.

The InGaN crystals are grown as layers in a sandwich-like arrangement on sapphire substrates. Typically, researchers have found that the atomic separation of the layers varies; a condition that can lead to high levels of strain, breakdowns in growth, and fluctuations in the alloy’s chemical composition.

“Being able to ease the strain and increase the uniformity in the composition of InGaN is very desirable,” says Ponce, “but difficult to achieve. Growth of these layers is similar to trying to smoothly fit together two honeycombs with different cell sizes, where size difference disrupts a periodic arrangement of the cells.”

As outlined in their publication, the authors developed an approach where pulses of molecules were introduced to achieve the desired alloy composition. The method, developed by Doolittle, is called metal-modulated epitaxy. “This technique allows an atomic layer-by-layer growth of the material,” says Ponce.

Analysis of the atomic arrangement and the luminosity at the nanoscale level was performed by Fischer, the lead author of the study, and Wei. Their results showed that the films grown with the epitaxy technique had almost ideal characteristics and revealed that the unexpected results came from the strain relaxation at the first atomic layer of crystal growth.

New device stores electricity on silicon chips

Solar cells that produce electricity 24/7, not just when the sun is shining. Mobile phones with built-in power cells that recharge in seconds and work for weeks between charges.

These are just two of the possibilities raised by a novel supercapacitor design invented by material scientists at Vanderbilt University that is described in a paper published in the Oct. 22 issue of the journal Scientific Reports.

It is the first supercapacitor that is made out of silicon so it can be built into a silicon chip along with the microelectronic circuitry that it powers. In fact, it should be possible to construct these power cells out of the excess silicon that exists in the current generation of solar cells, sensors, mobile phones and a variety of other electromechanical devices, providing a considerable cost savings.

Instead of storing energy in chemical reactions the way batteries do, “supercaps” store electricity by assembling ions on the surface of a porous material. As a result, they tend to charge and discharge in minutes, instead of hours, and operate for a few million cycles, instead of a few thousand cycles like batteries.

These properties have allowed commercial supercapacitors, which are made out of activated carbon, to capture a few niche markets, such as storing energy captured by regenerative braking systems on buses and electric vehicles and to provide the bursts of power required to adjust of the blades of giant wind turbines to changing wind conditions. Supercapacitors still lag behind the electrical energy storage capability of lithium-ion batteries, so they are too bulky to power most consumer devices. However, they have been catching up rapidly.

Researchers advance scheme to design seamless integrated circuits etched on graphene

Researchers in electrical and computer engineering at UC Santa Barbara have introduced and modeled an integrated circuit design scheme in which transistors and interconnects are monolithically patterned seamlessly on a sheet of graphene, a 2-dimensional plane of carbon atoms. The demonstration offers possibilities for ultra energy-efficient, flexible, and transparent electronics.

Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing “contact resistance” between them, both of which lead to degrading performance and rising energy consumption. Graphene-based transistors and interconnects are a promising nanoscale technology that could potentially address issues of traditional silicon-based transistors and metal interconnects.

“In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns – narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices in a seamless fashion and lower interface/contact resistances,” explained Kaustav Banerjee, professor of electrical and computer engineering and director of the Nanoelectronics Research Lab at UCSB. Banerjee’s research team also includes UCSB researchers Jiahao Kang, Deblina Sarkar and Yasin Khatami.

“Accurate evaluation of electrical transport through the various graphene nanoribbon based devices and interconnects and across their interfaces was key to our successful circuit design and optimization,” explained Jiahao Kang, a PhD student in Banerjee’s group and a co-author of the study. Banerjee’s group pioneered a methodology using the Non-Equilibrium Green’s Function (NEGF) technique to evaluate the performance of such complex circuit schemes involving many heterojunctions. This methodology was used in designing an “all-graphene” logic circuit reported in this study.

“This work has demonstrated a solution for the serious contact resistance problem encounterd in conventional semiconductor technology by providing an innovative idea of using an all-graphene device-interconnect scheme. This will significantly simplify the IC fabrication process of graphene based nanoelectronic devices.” commented Philip Kim, professor of physics at Columbia University, and a renowned scientist in the graphene world.

As reported in their study, the proposed all-graphene circuits have achieved 1.7X higher noise margins and 1-2 decades lower static power consumption over current CMOS technology. According to Banerjee, with the ongoing worldwide efforts in patterning and doping of graphene, such circuits can be realized in the near future.