Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘design’

FD-SOI Targets Mobile Applications

Monday, September 30th, 2013

GIORGIO CESANA, STMicroelectronics, Crolles, France and CARLOS MAZURE, Soitec, Bernin, France

The FD-SOI technology platform is perfectly suited for mobile IC applications where power consumption has to be very low to maximize battery lifetime.

The IC industry has been innovative with the introduction of new materials and process modules like stressors, high-k and metal gates (HKMG). It has been very conservative in keeping the bulk planar transistor structure. As a result, the planar transistor has become a highly doped device with decreasing dimensions. Moreover, at these smaller dimensions, transistor characteristics suffer from statistical fluctuations like random dopant fluctuations (RDF) in the channel, which impair device matching in sub-100nm circuits. This has become an important problem beyond node 28/32nm limiting VDD reduction, thus limiting the reduction of both dynamic and standby power consumption.

There is strong consensus in the IC community that fully depleted (FD) transistors, also known as Ultra Thin Body (UTB) devices, are an effective solution for reducing the VT variability caused by random dopant fluctuation (RDF). FD devices can be vertical, (FinFETs, 3D MOSFET) [1], or planar (FD-SOI) [2, 3]. Their key characteristic is that the silicon channel is undoped.

FD-SOI is an evolutionary innovation because it has the advantage of being a planar transistor structure that extends the applicability of bulk design flows with existing design and EDA tools. It is a non-disruptive MOSFET architecture change for SOC design and processing. FD-SOI requires ultra-thin Si (<20nm) over an ultra-thin buried oxide (BOX<25nm) for improved electrostatics [3]. FD technology brings numerous benefits for power reduction, area scaling and performance improvement while enabling a lower VDD [3]. The IC SOC community has accepted that technology nodes beyond 20nm will have to use fully depleted (FD) MOSFETs.

Pushing performance, Intel introduced the 3D transistors, FinFET, first in 2011 for CPU applications [1]. The foundry world, in contrast, was able to scale conventional bulk CMOS technology from to 28nm to 20nm. The gain in density came with a higher price per unit area and little performance gain, however. Indeed, beyond the 28nm node, CMOS technology has become more complex with double patterning (node 20nm) and with 3D FinFET devices (node 14/16nm). The performance gain from node to node is well below the 30% boost we have seen historically with scaling from a nodes n to the following n+1.

In this landscape, 28nm FD-SOI [4, 5] offers a very attractive value proposition: best low power at HKMG performance. In fact, 28nm FD-SOI gives the performance boost of scaling without changing the node. This is very interesting option for low-power ICs where area is not the driving factor and which could profit from a performance boost at constant or lower power consumption. Thus for many IC products moving to FD-SOI without changing the node can be very attractive from a power, performance and cost point of view. Only density-driven ICs need to rush to the next node. The offering of 28nm FD-SOI by foundries [6] will, without doubt, be interesting for numerous fabless companies having products in 28nm that could take advantage of a higher performance second generation 28nm technology without sacrificing low-power operation. Furthermore, low-power HKMG 28nm FD-SOI will also be very attractive 40nm IC products moving to 28nm.
FD-SOI technology

For bulk MOSFETs, the channel VT is tuned through channel and Halo doping, which is where RDF originates. In contrast, the FD-SOI channel is undoped, significantly decreasing or eliminating RDF. The FD transistor VT is tuned through the gate work function and the back-bias voltage. Because of better electrostatics, FD-SOI transistors exhibit lower parasitics, which improves the transistor driving behavior. This is particularly advantageous at low VDD supplies. The better electrostatics also improve the short-channel effect as compared to the bulk 28nm version. This in turn enables a CMOS technology with shorter gate lengths (Lg=24nm), relaxing the integration constraints on the source and drain contact module.

FD-SOI in the ultra-thin body and buried oxide (UTBB) configuration [2, 3] offers the additional benefit of modulating the FD transistor characteristics by applying a back bias (FIGURE 3a). The FD-SOI transistor is, in principle, controlled by two gates: the actual transistor gate and the back plane, which acts as a second independent gate. Forward (FBB) and reverse back bias (RBB) circuit techniques have been used by many designers in earlier technology nodes but the range of biases were limited, on the one hand, by the source/drain to well diode forward-biasing, and, on the other hand, by the diminishing back biasing modulation of the bulk-transistor threshold voltages (VT) due to increasing channel doping levels. UTBB enables an extended back-biasing range of several VDD (-3V<VBB<+3V) and is a very powerful design tool for power management as well as for performance boosting, as illustrated in FIGURE 3b. Moreover, FD-SOI technology allows for dynamically adjusted threshold voltages.

Body bias requires a limited area overhead (2-3%), and can be restricted only to the IPs (i.e. CPU/GPU cores) that would benefit most from it to reduce the implementation effort and area overhead.

The 28nm FD-SOI process flow is a modified bulk 28nm HKMG LP process. It uses the same back end of the line andsame gate module. It is a simple incremental porting from bulk 28nm. Manufacturing even uses the same tool set. Several process steps, specifically channel implants, halo implants and masking levels, are removed compared to the traditional 28nm bulk technology because of the undoped FD-SOI channel. There is less than a 20% change to the typical CMOS bulk flow [4, 6].

The extremely thin body and buried oxide layers makes it possible to etch them and to co-integrate SOI and bulk devices on the same SoC. The ESD and I/O structures are kept in bulk for simplicity (FIGURE 4b). This is the hybrid integration with diodes and bipolars in bulk [2, 3, 4].

FD-SOI Substrates

FD-SOI technology builds on an SOI substrate with ultra-thin top Si (<12nm) and ultra-thin buried oxide (25nm) and with the utmost thin-layer uniformity of 6 = 0.5nm, all sites and all wafers [8].

Ultra-thin Silicon: The starting ultra-thin Si thickness has to be matched to the subsequent FD CMOS processing. Cleaning and sacrificial oxidations remove a few Si monolayers and this has to be considered when specifying the initial SOI thickness. The targeted Si channel thickness is typically between 5nm ??? 7nm [3, 7]. The SOI thickness (TSi) has a direct effect on the MOSFET characteristics [5]. To take advantage of the improved electrostatic behavior of FD-SOI, the rule of thumb is LG=1/3 TSi (5) in the channel region.

Thickness uniformity is the key parameter to control the VT variation and short-channel effects (SCE) of the planar FD-SOI device. Typical uniformity requirements include on-wafer uniformity and wafer-to-wafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the nanometer or sub-nanometer range for the SOI layer for all wafers and all sites in order to meet the FD specifications.

From circuit and device considerations, the maximum TSI fluctuation that can be tolerated is ??5?? within-wafer (WiW), total wafer range of the TSi non uniformity, and wafer-to-wafer (WtW) TSi reproducibility.

Ultra-thin BOX: The thin BOX (Buried Oxide) suppresses the lateral electrostatic coupling between source, drain and channel of the transistor through the thick BOX. Furthermore, the BOX thickness reduction improves the scalability of the FD-SOI device at almost constant channel silicon thickness down to LG=10nm, which corresponds to the targeted gate length for the 10nm node. An ultra-thin BOX (UTBOX) enables the use of a back bias and a forward bias to adjust the transistor characteristics like current drive (Ion), off leakage (Ioff) and VT within an extended VBB voltage range [9].
The BOX thickness TBOX and silicon thickness TSi are independent parameters for the SOI fabrication and can therefore be adjusted without degrading the properties of the top silicon layer. The oxide quality of ultra-thin BOX is very similar to the quality of equivalent gate oxides.

FD-SOI Design

We use standard commercial EDA flow to design both bulk and FD-SOI. Design migration from Bulk to FD-SOI EDA flow is straightforward. The interconnects and routing are identical. FD-SOI devices behave very much like bulk transistors because there is no history effect and no floating-body effect, if TSi is sufficiently thin (<10nm). Logic and memory design and architecture are also similar to bulk.

The differences between FD-SOI and bulk are related to process and devices, and include, SPICE models, integration of ESD and analog devices, and application of back-bias schemes.

FD-SOI standard and custom cells can be duplicated or ported from existing bulk cells. Re-characterization is required due to a different SPICE model: Input capacitance, timing, leakage and dynamic power data in library files will change. Timing analysis needs to be rerun to check that there are no setup/hold violations in case of direct porting. Porting bulk designs to FD-SOI is as simple as porting to an updated bulk design [10, 11, 13, 14].

The device models are validated on FD-SOI hardware and available with EDA tools. Compact device models [11, 12] are production ready.

Circuit Results

SRAM Robustness: The lowest AVT values are achieved with FD-SOI [3, 9] due to the undoped channel and consequently the strong RDF reduction. Thus, lower VDD operation is enabled for minimum SRAM cell size as compared to its bulk equivalent. The FD-SOI cell has a better read stability and write ability with respect to the bulk cell. The typical bulk countermeasures of increasing VDD, or increasing the channel length and width to compensate for the VT variability are no longer necessary. At the same cell size, FD-SOI makes it possible to gain 100mV to 200mV in Vmin compared to the bulk cell [4]. The operation regime at VDD<0.8V is very attractive for mobile hand-held applications.

Circuit Performance: FD-SOI technology is particularly suited for high speed at low-voltage operation, reducing signifantly the power consumption (~VDD).

At 0.6V, FD-SOI is already capable of delivering 550MHz, >3x the performance of an equivalent 28LP technology implementation, without requiring any Forward Body Bias (FBB). Using Forward Body Bias, it is possible to reach 1GHz operation with a 0.6V source.

FD-SOI can also deliver the same performance as bulk while running at a lower operating voltage. As highlighted in Fig. 7, we have achieved the same performance in 28nm FD-SOI as 28LP while running with 200mV lower supply, and an even further saving of 200mV is possible when applying Forward Body Bias. This impressive reduction of 400mV on the supply voltage immediately translates into huge dynamic power savings.
In overdrive conditions, by boosting performance with FBB, we have demonstrated 3GHz operation [13], overtaking what has been obtained to date with the A9 architecture.

Conclusion

The FD-SOI technology targets fast performance at low voltage VDD and is an ideal technology to reduce the energy gap between battery energy supply and smart handheld system energy needs, so it runs cool. The industrial ecosystem is in place for the substrate supply, technology platform and design infrastructure. The FD-SOI technology platform is perfectly suited for mobile IC applications where the power consumption has to be very low to maximize battery lifetime. Furthermore, with its simplicity, FD-SOI is an evolutionary step from bulk towards fully depleted design because it maintains the planar device structure.

References

1. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarme, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L.Pipes, I. Post, S. Pradhan, M.Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sanford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry, “A 22nm High Performance and Low Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, self-Aligned Contacts and High Density MIM Capacitors”, VLSI Symp. Tech. (2012).
2. N. Planes, O. Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, PO Sassoulas, X. Federspiel, A. Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, D. Petit, D. Golansli, C. Fenouillet-Beranger, N. Guillot, M. Rafik, V. Huard, S. Puget, X. Montagner, MA Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud and M. Haond, “28nm FD-SOI Technology Platform for High-Speed Low-Voltage Digital Applications”, VLSI Symp. Tech. (2012).
3. T. Skotnicki; IEDM Short Course “Low Power Logic and Mixed Signal Technology”, IEDM 2009.
4. J. Hartmann, STMicroelectronics, “Planar FD-SOI technology at 28nm and below for extremely power efficient SOCs”, 13 Dec 2012, San Francisco, California, USA. www.soiconsortium.com
5. T. Skotnicki, Proc. of ESSDERC 2000, pp. 19-33.
6. S. Kengari, GlobalFoundries, ” SoC Differentiation using FD-SOI ??? A Manufacturing Partner’s Perspective FD-SOI Workshop”, 22 April 2013, Hsinchu, Taiwan. www.soiconsortium.com
7. K. Cheng, et al; “ETSOI CMOS with Record Low Variability for Low Power System-on-Chip Applications”, IEDM 2009, session 3.2.
8. FD-SOI substrate Soitec data sheet.
9. F. Andrieu, et al; “Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond”, VLSI 2010, session 6.1.
10. J.L. Pelloie and B. Hold, “FD-SOI Design Portability from BULK at 20nm Node”, Fully Depleted Workshop, San Francisco, Feb. 24, 2012. www.soiconsortium.com
11. G. Cesana, “20nm and 28nm FD-SOI Technology Platforms”, Fully Depleted Workshop, San Francisco, Feb. 24, 2012. www.soiconsortium.com
12. C. Hu, A. Niknejad, Sriramkumar V., Darsen Lu, Yogesh Chauhan, Muhammed Karim, Angada Sachid, “BSIM-IMG: A Turnkey Compact Model for Back-gated FD-SOI MOSFETs”, Fully Depleted Workshop, Hsinchu, Taiwan, April 28, 2011. www.soiconsortium.com
13. L. Le Pailleur, Proc. of VLSI-TSA 2013.
14. L. Le Pailleur, “Seamless design migration to 28nm FD-SOI”, 22 April 2013, Hsinchu, Taiwan.
GIORGIO CESANA is director of technology marketing at STMicroelectronics, Crolles, France and CARLOS MAZURE is chief technology officer at Soitec, 38190 Bernin, France.

SPICEing up Circuit Design

Friday, September 27th, 2013

Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, blogs about the challenges of designing for yield using SPICE models.

The ubiquitous SPICE circuit simulator, initially released 40 years ago, made a recent list of the top 10 most significant developments in the history of EDA, as it should. Its widespread use and importance among circuit designers cannot be understated.

However, the third-generation of SPICE (Simulation Program with Integrated Circuit Emphasis) simulation is showing its age. Circuit designers are doing giga-scale simulations because of complex designs, increasingly simulated post-layout and the large number of simulations required to design for variation effects.

Giga-scale designs range from post-layout analog circuits, high-speed I/Os, memory and CMOS image sensor arrays to full-chip power ICs, and clock trees and critical path nets. They require a parallel SPICE simulator with high capacity in the order of tens of millions of elements for analog designs and hundreds of million elements for memory designs. A SPICE simulator needs to deliver high performance with pure SPICE accuracy and offer support for the latest process technologies such as FinFETs.

Three dimensional FinFETs bring additional challenges to device modeling and circuit simulations. Modeling and simulation tools must be able to handle increased layout dependencies in device characteristics and more complex parasitics, including internal parasitics and interactions between the device and surrounding components.

Current SPICE simulators can offer few of these must haves. Traditional SPICE simulators lack capacity even with parallelization capabilities. FastSPICE simulators deliver capacity at the cost of accuracy and are losing steam as an increasing number of designs require post-layout verification that weakens circuit hierarchy. The FastSPICE table model approach and approximated matrix solutions can offer unreliable results and poor usability for complicated giga-scale designs with multiple operating modes and supply voltages.

The key is to maintain simulation accuracy as traditional SPICE simulators do, and simultaneously, be able to handle large circuit simulation capacity that typically only FastSPICE simulators can do with reasonable simulation time. In today’s bleeding-edge designs, designers often can’t settle for performance or capacity by sacrificing accuracy as FastSPICE simulators can.

EDA vendors are aware of these trends and the increasingly urgent market needs. Almost all existing SPICE and FastSPICE simulators have been working hard to utilize parallel technologies on multicore and/or multi-CPU computing environments to improve simulation performance. However, patched-on parallelization offers short-term improvement, and can’t fully meet the need for simulation accuracy, performance and memory consumption for giga-scale circuit designs.

New simulation technology is essential for deep-nanometer technology designs where process variations impact circuit yield and performance. In addition to capacity challenges related to increasing circuit size, designers need to run large numbers of repeated simulations to tackle the impact of process variations. Process-Voltage-Temperature (PVT) analysis and statistical Monte Carlo analysis create another challenge dimension for giga-scale simulations.

In a circuit designer’s ideal world, the next-generation SPICE circuit simulator would be highly accurate with full SPICE analysis features and support for industry-standard inputs and outputs. It would be much, much faster than traditional SPICE simulators and able to handle all circuit types. The ability to simulate giga-scale circuits and challenging post-layout designs is mandatory. Building parallelization in a SPICE simulator from the ground up instead of patched-on solutions is the key to handling giga-scale simulations with good performance and memory consumption, while still offering SPICE accuracy. Most aging circuit simulators will soon show their limitations.

Ideally, the new SPICE simulator also will have native capabilities to handle process variations from 3-sigma to high-sigma Monte Carlo simulations, where hundreds or even thousands of simulations are needed. Circuit designers have begun to search for Design-for-Yield (DFY) solutions and not just cobbled-together point tools. A total DFY solution starts with a high-capacity, high-performance SPICE simulator as its engine. A simulator designed for DFY with built-in statistical simulation capabilities can provide incomparable simulation performance when compared to ad-hoc variation analysis with external circuit simulators.

And, of course, the SPICE simulation engine should be tightly integrated with statistical transistor model extraction and yield prediction/improvement software. Those components make a total DFY solution, and enable the efficiency and consistency of yield-analysis results.

Giga-scale simulation isn’t the future, it’s here today and needs viable solutions to meet the challenges it has created. SPICE simulators have served the circuit design industry for 40 years, and it’s time for the next generation, essential for deep nanometer technology designs.

SRC TECHCON 2013: Design techniques for scalable transceivers

Friday, September 27th, 2013
YouTube Preview Image

From SEMICON West 2013: Luc Van den hove of imec

Tuesday, July 30th, 2013
YouTube Preview Image

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.