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Posts Tagged ‘DAC’

Mentor Graphics Offers Tanner Calibre One Verification Suite for the Tanner Analog/Mixed-Signal IC Design Environment

Monday, June 6th, 2016

Mentor Graphics® Corporation announced the Tanner Calibre One IC verification suite as an integral part of the Tanner™ analog/mixed-signal (AMS) physical design environment, creating an easy path to the proven capabilities of Calibre® verification tools for Tanner EDA’s user base. This results in a dramatically-improved IC design and verification solution for Tanner customers by providing tightly-integrated access to Calibre’s physical and circuit verification, exclusively within the Tanner L-Edit™ layout environment.

The Calibre platform is the industry-leader for physical verification and is qualified for sign-off by every major IC foundry and the Tanner Calibre One verification suite uses the same Calibre design kits. Customers that already have stand-alone Calibre licenses, and would like to consider the Tanner design environment, can continue to use the pre-existing Calibre-Tanner interfaces. However, offering an additional, custom integration between Calibre and the Tanner AMS IC design flow provides an invaluable option for Tanner IC designers, giving design teams the access they need to confidently tape out their designs.

“We’ve seen a dramatic increase in the productivity of our layout team thanks to the seamless interaction of L-Edit and the Tanner Calibre One verification suite,” said Stefan Lauxtermann, President of Sensor Creations Inc. “Our customers greatly value that we employ Calibre and that there is a one-to-one correspondence between the final DRC by the foundry and the Tanner design process that we use.”

The Tanner Calibre One verification suite includes the following products:

  • Calibre nmDRC™ (hierarchical design rule checking) ensures the physical layout can be manufactured. This industry-leading tool provides fast cycle times and innovative design rule capabilities.
  • Calibre nmLVS™ (hierarchical layout versus schematic) checks that the physical layout is electrically and topographically the same as the schematic. It improves designer productivity by providing actual device geometry measurement and sophisticated interactive debugging capabilities to ensure accurate verification.
  • Calibre xRC™ (parasitic extraction) verifies that layout-dependent effects do not adversely affect the electrical performance of the design, delivering accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

In addition, the Calibre RVE™ tool brings the solution together, providing a graphical results viewing environment that reduces debug time by visually identifying design issues instantly and cross-selecting the associated issue in Tanner’s layout and schematic capture tool.

The Tanner IC design suite supports analog, mixed-signal, and MEMS design in one complete, highly-integrated, end-to-end flow. Designers capture the schematic, perform analog and mixed-signal simulation, and lay out the physical design within this unified flow. With the addition of the Tanner Calibre One verification suite, each designer using the Tanner IC flow can interactively invoke an individual Calibre tool in order to verify the design.

“Tanner Calibre One gives designers using L-Edit the highest confidence possible that their tape outs will be successful,” says Greg Lebsack, General Manager of Tanner operations at Mentor Graphics. “We are thrilled that key capabilities of the industry-leading Calibre suite are now available to everyone in our global Tanner customer base.”

The Tanner Calibre One design flow will be demonstrated at the 2016 Design Automation Conference (DAC) in the Tanner EDA booth (#1828).

Pattern Matching Tackles IC Verification and Manufacturing Problems

Monday, June 6th, 2016

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Mentor Graphics Corporation announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems. The solution is integrated into the Mentor® Calibre nmPlatform solution, creating a synergy that drives these new applications at IC design companies and foundries, across multiple process nodes.

Calibre Pattern Matching technology supplements multi-operational text-based design rules with an automated visual geometry capture and compare process. This visual approach is both very powerful in its ability to capture complex pattern relationships, and to work within mixed tool flows, making it much easier for Mentor customers to create new applications to solve difficult problems. Because it is integrated into the Calibre nmPlatform toolset, the Calibre Pattern Matching functionality can leverage the industry-leading performance and accuracy of all Calibre tools and flows to create new opportunities for design-rule checking (DRC), reliability checking, DFM, yield enhancement, and failure analysis.

“Our customers count on eSilicon’s design services, IP, and ecosystem management to help them succeed in delivering market-leading ICs,” said Deepak Sabharwal, general manager, IP products & services at eSilicon. “We use Calibre Pattern Matching to create and apply a Calibre-based yield-detractor design kit that helps identify and eliminate design patterns that impact production ramp-up time.”

Since its introduction, use models for Calibre Pattern Matching technology have rapidly expanded, solving problems that were previously too complex or time-consuming to be implemented. New use cases include the following:

  • Physical verification of IC designs with curved structures—for analog, high-power, radio frequency (RF) and microelectromechanical (MEMS) circuitry—is extremely difficult with products designed to work with rectilinear design data. Calibre customers are automating that verification using a combination of Calibre Pattern Matching technology and other Calibre tools for much greater efficiency and accuracy, especially when compared to manual techniques.
  • Calibre Pattern Matching technology can be used to quickly locate and remove design patterns that are known or suspected of  being difficult to manufacture (“yield detractors”). Foundries or design companies create libraries of yield detractor patterns that are specific to a process node or a particular design methodology. Samsung Foundry used this approach in its Closed-Loop DFM solution to help its customers ramp to volume faster, and reduce process-design variability.
  • Some customers use Calibre Pattern Matching technology with Calibre Auto-Waivers™ functionality to define a specific context for waiving a DRC violation. This enhancement allows for automatic filtering of those violations for significant time savings and improved design quality.

“To help our customers create manufacturing-ready designs, we use Calibre Pattern Matching to create and use a yield detractor database to fix most of the litho hotspots in the block level. Then we perform fast signoff DFM litho checking at the chip level using an integrated solution with Calibre Pattern Matching and Calibre LFD” said Min-Hwa Chi, senior vice president, SMIC. “By offering a solution for manufacturability robustness that is built on the Calibre platform, we are seeing ready customer adoption of SMIC’s DFM solution.”

With the Calibre Pattern Matching tool, design companies can now optimize their physical verification checking to their unique design styles. The tool is easy to adopt because it doesn’t rely on expertise in scripting languages. Instead, any engineer can readily define a visual pattern that captures the designer’s expertise in the critical geometries and context for that configuration.

“With the growing adoption of Calibre Pattern Matching technology, Mentor continues to help our customers address increasing design complexity, regardless of the process node they are targeting,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “By incorporating the Calibre Pattern Matching tool, the Calibre platform becomes an even more valuable bridge between design and manufacturing for the ecosystem.”

At the 2016 Design Automation Conference, Mentor has a Calibre Pattern Matching presentation on Tuesday, June 7 at 3PM in the Mentor booth #949. Register for the session using the registration form.

https://www.mentor.com/events/design-automation-conference/schedule

Veloce Redefines Power Analysis Flow

Tuesday, June 9th, 2015

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Mentor Graphics Corp. released the Veloce® Power Application software that enables accurate, timely and efficient power analysis at the system, RTL and gate level for complex SoC designs.

Power continues to be a primary concern for handheld and smart devices with high resolutions screens that require long battery life, and even wall-plugged equipment in a datacenter or in a network configuration needs to reduce operation costs. Using FinFET process technology reduces static leakage, yet dynamic power remains a challenge.

A new usage model for handheld and smart devices is driving a methodology shift in the way power is analyzed.  One primary driver in this shift is the fact that complex SoC designs are now verified using live applications that require booting the OS and running software applications on an emulator. It is more effective to use the power switching activity plot, generated during emulation, to pass real-time switching activity information to power analysis tools where potential power issues can be evaluated.

“The ITRS report, one of my many primary research projects, has emphasized the issues related to dynamic power for several years,” said Gary Smith, founder and chief analyst, Gary Smith EDA. “A new approach to the transfer of power switching activity data captured during emulation is the right direction for the industry.”

When designs with significant software content are run on an emulator, the current method of generating activity data creates files (like FSDB) that are too large for power analysis tools to handle practically.

The Veloce Power Application replaces the file-based power analysis flow with a Dynamic Read Waveform API integration to power analysis tools.  This Dynamic Read Waveform API approach captures the information from the power switching activity plot and transfers that data to power analysis tools. This enables accurate power calculation at the system level, better power exploration at RTL for power budgeting and tradeoffs as well as more accurate power analysis and sign-off at the gate level.

The result is a significant boost in runtime and performance. The typical approach of running the emulator, creating the file, reading the file into the power analysis tool and running the power analysis tool is now, with this new approach, reduced to the emulator and power analysis runtimes.

Current early access partners and customers have seen up to a 4.5X runtime performance improvement.

“Today we have redefined the power analysis flow,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “The Veloce Power Application is a proof point to show that a new methodology that captures real power consumption during emulation and effectively passes that information to power analysis tools is more efficient.”

Delivering this integration with an ecosystem of industry-recognized power analysis tool providers is essential to redefining the power analysis flow. The first Veloce Power Application ecosystem partner is ANSYS® with PowerArtist™.

“This collaboration addresses the challenges for designers of energy-efficient IP and SoC designs in various IoT verticals,” said Vic Kulkarni, Sr. vice president and general manager, RTL power business, at Apache division of ANSYS. “With our industry leading PowerArtist solution, we are delighted to be the premier partner in the Veloce Power Application ecosystem, and to work so closely with a technology leader in hardware emulation.”

The Veloce Power Application integration with ANSYS PowerArtist is available to mutual customers on a limited basis.  Full production release is scheduled for early Q4/CY 2015.

For a technical whitepaper visit: http://www.mentor.com/products/fv/techpubs/download/?id=90538

Tackling Parameter Extraction for 16nm and Below

Monday, June 8th, 2015

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There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.

With Calibre xACT, Mentor Graphics has a solution that is part equation-based and part field solver, giving high accuracy and high throughput. Customers using the Calibre xACT platform for parasitic extraction have experienced improvements in turnaround time as high as 10X, while meeting the most stringent accuracy requirements.

At DAC this week, Carey Robertson, product marketing director of Calibre xACT, will be presenting an optimized extraction flow for RF-SOI processes, based on work with STMicroelectronics, today (Monday June 8th) between 4-5 pm at the Mentor Graphics booth #1432. Register at the Mentor Graphics website: http://www.mentor.com/events/design-automation-conference/schedule

Robertson explained the new challenges facing the industry. “We have new types of devices that are three-dimensional in nature. There is a very profound electrical field that is three dimensional in nature, and very difficult to capture with traditional techniques, such as equations or tables,” he said. In addition to the device itself, there’s going to be local interconnect, there’s going to be contacts that need to be modeled.

Parasitic electrical fields around a 3D finFET device.

Double- and multi-patterning adds to the complexity.  “In the area of parasitic extraction, double patterning essentially means that we have geometries on the same layer on different masks. As those masks shift, that will incur additional sources of parasitic variation that we have to consider,” Robertson explained.

In addition, foundries such as Samsung, TSMC and GLOBALFOUNDRIES are pushing tighter and tighter criteria. “Foundries are pushing EDA vendors to bring the accuracy of their parasitic tools to a much tighter level vs their golden reference,” Robertson said. “At 20nm, if we felt like our accuracy was within 5-10% of the golden reference, that was typically fine. What we’re seeing at 16, 14 and 10nm is that foundries are requiring that the accuracy be within 2%, many times 1% with a sigma of 2%,” Robertson said. “It’s very, very tight criteria, tighter than we’ve ever seen before.

The other challenge is that in years past, EDA vendors would get a lot of data to use to develop their tools. “We’d get a lot of structures and a lot of things to go check against. We’d get those inside Mentor Graphics and R&D could play with that and figure out the best models to accommodate them,” Robertson said. He described today’s situation as an arms race between foundries and designers, where secrecy was paramount. “It’s an arms race to see who comes up with the best process, and it’s a race amongst designers to come up with who has the best designs. They don’t let their design data go outside of their respective companies. We have to figure out how to model these with more complex interactions, tighter criteria and much less access to data,” he said.

Enter the new Calibre® xACT™ parasitic extraction platform that addresses a wide spectrum of analog and digital extraction needs, including 14nm FinFET, while minimizing guesswork and setup efforts for IC designers. The Calibre xACT platform delivers a combination of accuracy and turnaround time (TAT) by automatically optimizing its extraction techniques for the customer’s specific process node, application, design size, and extraction objectives.

Samsung has worked extensively with Mentor Graphics on the development and qualification of the Calibre xACT platform for 14nm, and used it during technology development because of the high accuracy it provides. The Calibre xACT product’s ability to employ a single rule deck for a range of extraction applications allows customers to get the accuracy and fast TAT they need without having to manually modify their rule decks or tool configuration.

“After careful benchmarking of the leading extraction products, we selected Calibre xACT to be our reference signoff extraction tool for all of our next generation designs,” said Dragomir Nikolic, CAD Director, Cypress Semiconductor. “This includes products at the 90nm and 65nm process nodes. We found Calibre xACT to have the best combination of high accuracy and fast turnaround available among extraction products targeting leading-edge nodes. We also see great value in the ability to use a single extraction tool to produce optimum results across a wide variety of applications, from transistor level to full chip digital extraction.””

Circuit designers have to wrestle with performance versus accuracy throughout the design cycle. Parasitic extraction is no different. With the leading process nodes using more complex FinFET devices, design engineers are pushing for tighter accuracy, while also needing higher performance and capacity for billion transistor designs. In fact, all process nodes are seeing growing complexity with the mix of memory, analog, standard cell, and custom digital content in modern IC’s. This complexity poses a range of different challenges for extraction tools. To meet these requirements the Calibre xACT platform uses a combination of compact model, field solver and efficient multi-CPU scaling technologies to ensure robust accuracy as well as turnaround performance needed to meet schedule deadlines.

The Calibre xACT extraction platform is integrated with the entire Calibre product line for a seamless verification flow, including the Calibre nmLVS™ product for complete transistor-level modeling, and the Calibre xACT 3D product for targeted, extreme-accuracy extraction applications. It also interoperates with third-party design environments and formats to ensure compatibility with existing design and simulation flows.

“It’s an environment that has all of the necessary integration and accuracy techniques that the custom IP designer needs, as well as the throughput, turnaround time and scalability the signoff/extraction needs,” Robertson said.

At DAC this week, Robertson will be presenting an optimized extraction flow for RF-SOI processes, based on work with STMicroelectronics, today (Monday June 8th) between 4-5 pm. Register at the Mentor Graphics website: http://www.mentor.com/events/design-automation-conference/schedule

Robertson says to enable RF design optimization with high correlation to actual silicon, simulation of RF-SOI designs must include extraction and modeling of the silicon substrate. Conventional silicon substrate extractions are cumbersome to use or lack the accuracy and performance required to produce a full-chip post-layout netlist.

STMicroelectronics, Mentor Graphics and Coupling Wave Solutions are working on a new flow that generates silicon substrate parasitics in just a few minutes. These can be added to a conventional post-layout netlist to produce a complete and accurate parasitic model for RF SOI designs. Carey’s presentation will give an overview of RF-SOI technology, and describe how the new extraction flow delivers parasitics accuracy, performance and ease-of-use.

Mentor Graphics Technical Sessions are held at booth #1432.

SOI: Revolutionizing RF and expanding in to new frontiers

Friday, April 17th, 2015

By Peter A. Rabbeni, Director, RF Segment Marketing and Business Development, GLOBALFOUNDRIES

Faster connections and greater network capacity for wireless technologies such as LTE, WiFi, and the Internet of Things is driving the demand for more complex radio circuit designs and multi-band operation.  In addition the emergence of wirelessly connected smart wearables is not only driving localized high performance processing power but also extended battery life, two goals which are often in conflict. The predicted explosion in the IoT is shown in Figure 1.

Figure 1. More than 30 billion devices are forecast to be connected to the internet by 2018 (Source: BI Intelligence).

The rapid growth in smartphones and tablet PCs and other mobile consumer applications has created an opportunity and demand for chips based on RF-SOI technology, particularly for antenna interface and RF front end components such as RF switches and antenna tuners.  As a low cost and more flexible alternative to expensive gallium arsenide (GaAs) technologies, the vast majority of RF switches today are built on RF-SOI.

To address the highly complex, multi-band and multi-standard designs, RF front-end modules (RF FEM) require integration of multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management. Today these functions are addressed by different technologies. The RF SOI process technology enables design flexibility by integrating multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management to be integrated—all on the same die. The benefit of integrated radios is they consume   less power and smaller area than traditional radios. Therefore, mobile devices that exploit radio integration using RFSOI can offer more functions with better RF performance at competitive cost.

Mobile devices that implement RF SOI for RF Front End module functions benefit from higher levels of integration that combine with improved linearity and insertion loss, which translates to better transmitter efficiency and thus longer battery life enabling longer talk times (lower power) and faster downloads (higher signal-to-noise ratio).

Emerging technologies like RF-SOI and even FD-SOI have unique properties and capabilities beneficial in enabling RF circuit innovation and integration levels never before seen in silicon-based technologies.  Device ft, gm/I, well bias control and inherent isolation of the substrate all contribute to improved system level performance over competing technology resulting in the ability to achieve higher linearity, lower power, low loss, and low cost/small size.

Innovative solutions

An innovative technology that is currently addressing the ever-increasing challenges of RF front-end design is UltraCMOS 10 (Figure 2). This customer specific process, co-developed by GLOBALFOUNDRIES and Peregrine Semiconductor, demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions. For designers, it dramatically reduces the required engineering and validation time. And, for the end-user, they benefit from longer battery life, better reception, faster data rates and wider roaming range. With the qualification process complete, UltraCMOS 10 technology is now a fully qualified technology platform.

Figure 2. UltraCMOS 10 technology demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions (Source: Peregrine Semiconductor).

High speed digital-to-analog converters (DAC) are an essential component for direct-to-RF conversion architectures. Faster converter sampling speeds and greater peak-to-peak signal fidelity hold high promise in moving mobile digital signal processing closer to the antenna. It has been demonstrated that DACs on fully depleted SOI, achieve high linearity and very low power for nyquist bandwidths as wide as 5.5GHz. The RF architecture with a high-performance DAC results in lower power dissipation while synthesizing very wideband signals (Figure 3). This further demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna.

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Figure 3. Low power RF DAC demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna [1

Agile radio architectures are another key area that can address mobile architecture challenges and cost. Today, the analog RF frontend duplicates much of the circuitry for each band. To simplify, new advancements (Figure 4) in tunable structures and filters are being made to provide a single radio for multi-band/multi-mode frequency. SOI technology offers the possibility to develop tunable/reconfigurable RF FEMs to improve RF performance at competitive cost.

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Figure 4. Cutting-edge developments in tunable filters [2

Creating an Ecosystem to Extend SOI to RF

As RF FEM architectures and design challenges become more and more complex, it becomes necessary to relieve some of the increased burden at all levels of the value chain. In order to provide better RF products—from system design and RF integrated circuits down to engineered substrate design—development teams can no longer expect to design in silos and be successful. Collaboration and co-optimization are becoming much more important as a result of the changing dynamics of the design-technology landscape.

Investing in the future is critical to address certain RF challenges such as radio architecture design in multiband, multimode mobile radios and ultra-low power (ULP) wireless devices. Successful collaboration will require adherence to standards to enable interoperability, otherwise, in this fragmented market, the industry won’t see the full benefit of all of the technology innovation. To succeed, we need collaboration at different levels, from R&D to ensure we have the world’s best talent trying to solve all of these problems, all the way through to business models.

There is no doubt that demand on our networks will continue grow and there are advanced chip technology challenges the industry needs to address to enable a higher level of integration and lower power consumption for future wireless communication. GLOBALFOUNDRIES is committed to enabling an SOI portfolio and ecosystem—from process, device, and circuit through system level IP— to lower customer design barriers and complexity and introduce new RF architectures that leverage SOI-based technologies.

References

1. E. Olieman, A.-J. Annema and B. Nauta, “A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist,,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium on , Honolulu, 2014.

2. Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumpernik, Bram Nauta, “A Forward-Body-Bias Tuned 450MHz Gm-C 3rd-Order Low Pass Filter in 28nm UTBB FD-SOI with >1VdBVp IIP3 over a 0.7 to 1V Supply”, ISSCC, San Francisco, 2015.