Part of the  

Solid State Technology


The Confab


About  |  Contact

Posts Tagged ‘cost’

Silicon Photonics Technology Developments

Thursday, April 6th, 2017


By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.


Lithographic Stochastic Limits on Resolution

Monday, April 3rd, 2017


By Ed Korczynski, Sr. Technical Editor

The physical and economic limits of Moore’s Law are being approached as the commercial IC fab industry continues reducing device features to the atomic-scale. Early signs of such limits are seen when attempting to pattern the smallest possible features using lithography. Stochastic variation in the composition of the photoresist as well as in the number of incident photons combine to destroy determinism for the smallest devices in R&D. The most advanced Extreme Ultra-Violet (EUV) exposure tools from ASML cannot avoid this problem without reducing throughputs, and thereby increasing the cost of manufacturing.

Since the beginning of IC manufacturing over 50 years ago, chip production has been based on deterministic control of fabrication (fab) processes. Variations within process parameters could be controlled with statistics to ensure that all transistors on a chip performed nearly identically. Design rules could be set based on assumed in-fab distributions of CD and misalignment between layers to determine the final performance of transistors.

As the IC fab industry has evolved from micron-scale to nanometer-scale device production, the control of lithographic patterning has evolved to be able to bend-light at 193nm wavelength using Off-Axis Illumination (OAI) of Optical-Proximity Correction (OPC) mask features as part of Reticle Enhancement Technology (RET) to be able to print <40nm half-pitch (HP) line arrays with good definition. The most advanced masks and 193nm-immersion (193i) steppers today are able to focus more photons into each cubic-nanometer of photoresist to improve the contrast between exposed and non-exposed regions in the areal image. To avoid escalating cost and complexity of multi-patterning with 193i, the industry needs Extreme Ultra-Violet Lithography (EUVL) technology.

Figure 1 shows Dr. Britt Turkot, who has been leading Intel’s integration of EUVL since 1996, reassuring a standing-room-only crowd during a 2017 SPIE Advanced Lithography ( keynote address that the availability for manufacturing of EUVL steppers has been steadily improving. The new tools are close to 80% available for manufacturing, but they may need to process fewer wafers per hour to ensure high yielding final chips.

Figure 1. Britt Turkot (Intel Corp.) gave a keynote presentation on "EUVL Readiness for High-Volume Manufacturing” during the 2017 SPIE Advanced Lithography conference. (Source: SPIE)

The KLA-Tencor Lithography Users Forum was held in San Jose on February 26 before the start of SPIE-AL; there, Turcot also provided a keynote address that mentioned the inherent stochastic issues associated with patterning 7nm-node device features. We must ensure zero defects within the 10 billion contacts needed in the most advanced ICs. Given 10 billion contacts it is statistically certain that some will be subject to 7-sigma fluctuations, and this leads to problems in controlling the limited number of EUV photons reaching the target area of a resist feature. The volume of resist material available to absorb EUV in a given area is reduced by the need to avoid pattern-collapse when aspect-ratios increase over 2:1; so 15nm half-pitch lines will generally be limited to just 30nm thick resist. “The current state of materials will not gate EUV,” said Turkot, “but we need better stochastics and control of shot-noise so that photoresist will not be a long-term limiter.”

TABLE:  EUVL stochastics due to scaled contact hole size. (Source: Intel Corp.)


From the LithoGuru blog of gentleman scientist Chris Mack (

One reason why smaller pixels are harder to control is the stochastic effects of exposure:  as you decrease the number of electrons (or photons) per pixel, the statistical uncertainty in the number of electrons or photons actually used goes up. The uncertainty produces line-width errors, most readily observed as line-width roughness (LWR). To combat the growing uncertainty in smaller pixels, a higher dose is required.

We define a “stochastic” or random process as a collection of random variables (, and a Wiener process ( as a continuous-time stochastic process in honor of Norbert Wiener. Brownian motion and the thermally-driven diffusion of molecules exhibit such “random-walk” behavior. Stochastic phenomena in lithography include the following:

  • Photon count,
  • Photo-acid generator positions,
  • Photon absorption,
  • Photo-acid generation,
  • Polymer position and chain length,
  • Diffusion during post-exposure bake,
  • Dissolution/neutralization, and
  • Etching hard-mask.

Figure 2 shows the stochastics within EUVL start with direct photolysis and include ionization and scattering within a given discrete photoresist volume, as reported by Solid State Technology in 2010.

Figure 2. Discrete acid generation in an EUV resist is based on photolysis as well as ionization and electron scattering; stochastic variations of each must be considered in minimally scaled areal images. (Source: Solid State Technology)

Resist R&D

During SPIE-AL this year, ASML provided an overview of the state of the craft in EUV resist R&D. There has been steady resolution improvement over 10 years with Photo-sensitive Chemically-Amplified Resists (PCAR) from 45nm to 13nm HP; however, 13nm HP needed 58 mJ/cm2, and provided DoF of 99nm with 4.4nm LWR. The recent non-PCAR Metal-Oxide Resist (MOR) from Inpria has been shown to resolve 12nm HP with  4.7 LWR using 38 mJ/cm2, and increasing exposure to 70 mJ/cm2 has produced 10nm HP L/S patterns.

In the EUVL tool with variable pupil control, reducing the pupil fill increases the contrast such that 20nm diameter contact holes with 3nm Local Critical-Dimension Uniformity (LCDU) can be done. The challenge is to get LCDU to <2nm to meet the specification for future chips. ASML’s announced next-generation N.A. >0.5 EUVL stepper will use anamorphic mirrors and masks which will double the illumination intensity per cm2 compared to today’s 0.33 N.A. tools. This will inherently improve the stochastics, when eventually ready after 2020.

The newest generation EUVL steppers use a membrane between the wafer and the optics so that any resist out-gassing cannot contaminate the mirrors, and this allow a much wider range of materials to be used as resists. Regarding MOR, there are 3.5 times more absorbed photons and 8 times more electrons generated per photon compared to PCAR. Metal hard-masks (HM) and other under-layers create reflections that have a significant effect on the LWR, requiring tuning of the materials in resist stacks.

Default R&D hub of the world imec has been testing EUV resists from five different suppliers, targeting 20 mJ/cm2 sensitivity with 30nm thickness for PCAR and 18nm thickness for MOR. All suppliers were able to deliver the requested resolution of 16nm HP line/space (L/S) patterns, yet all resists showed LWR >5nm. In another experiment, the dose to size for imec’s “7nm-node” metal-2 (M2) vias with nominal pitch of 53nm was ~60mJ/cm2. All else equal, three times slower lithography costs three times as much per wafer pass.


Indium-free Perovskite TCOs Could Save Costs

Monday, January 4th, 2016


By Ed Korczynski, Sr. Technical Editor

Lei Zhang, et al. from Pennsylvania State University—with collaborators from Rutgers University and University of Toledo—have found two new families of transparent conductive oxides (TCO) based on “correlated” electrons in ternary oxides of vanadium. From reported first principles, the co-authors are confident they will find many other correlated materials that behave like strontium vanadate (SrVO3) and calcium vanadate (CaVO3), which could make flat panel displays (FPD) and photovoltaic (PV) modules more affordable.

The correlation relies on strong electron–electron interactions resulting in an enhancement in the carrier effective mass. Both SrVO3 and CaVO3 demonstrate high carrier concentration (>2.2 ×1022 cm−3), and have low screened plasma energies (<1.33 eV). The Figure shows that there is a transparency trade-off in using these new TCOs, since at nominal 10nm thickness they are more than twice as opaque as Indium tin oxide (ITO).

Optical transmission of free standing conductive oxide films at 550nm wavelength, accounting for reflection and interference, and averaged over the range of the visible spectra. (Source: Nature Materials)

ITO has been the dominant TCO used in FPD manufacturing, but the price of indium metal has varied over the range of $100-1000/kg in the last 15 years. Consequently, industry has long searched for a TCO made of less expensive and less variable direct materials. Currently vanadium sells for ~$25/Kg, while strontium is even cheaper. Lei Zhang, lead author of the Nature Materials article ( and a graduate student in assistant professor Roman Engel-Herbert’s group, was the first to recognize the application.

“I came from Silicon Valley where I worked for two years as an engineer before I joined the group,” says Zhang. “I was aware that there were many companies trying hard to optimize those ITO materials and looking for other possible replacements, but they had been studied for many decades and there just wasn’t much room for improvement.” Engel-Herbert and Zhang have applied for a patent on this technology.

The U.S. Office of Naval Research, the National Science Foundation, and the Department of Energy funded this R&D. “Now, the question is how to implement these new materials into a large-scale manufacturing process,” said Engel-Herbert. “From what we understand right now, there is no reason that strontium vanadate could not replace ITO in the same equipment currently used in industry.”

Electrons flow like a liquid

Correlated oxides are defined as metals in which the electrons flow like a liquid, unlike conventional metals such as copper and gold in  which electrons flow like a gas. “We are trying to make metals transparent by changing the effective mass of their electrons,” Engel-Herbert says. “We are doing this by choosing materials in which the electrostatic interaction between negatively charged electrons is very large compared to their kinetic energy. As a result of this strong electron correlation effect, electrons ‘feel’ each other and behave like a liquid rather than a gas of non-interacting particles. This electron liquid is still highly conductive, but when you shine light on it, it becomes less reflective, thus much more transparent.”

In the November 2007 issue of the prestigious Physical Review B (DOI:  10.1103/PhysRevB.76.205110), F. Rivadulla et al. reported on “VO: A strongly correlated metal close to a Mott-Hubbard transition.” Vanadium oxide (VO) has a rocksalt cubic crystal structure, and displays strongly correlated metallic properties with non-Fermi-liquid thermodynamics and an unusually strong spin-lattice coupling. The structural and electronic simplicity of 3D monoxides provides a basic understanding of highly correlated electron systems, while this new work with 2D ternary oxides is inherently more complex.

One positive aspect of the more complex perovskite structure of SrVO3 and CaVO3 is that it provides for intriguing device integration possibilities with other functional perovskite materials. PV devices based on thin-films of complex perovskites have demonstrated excellent photon-electron conversion efficiencies in labs, but commercial manufacturing has so far been limited by the lack of an inexpensive TCO that can be integrated into a moisture barrier. The templating effect of underlayers could allow for faster deposition of more ideal SrVO3.


Safe CMP slurries for future IC materials

Wednesday, April 29th, 2015


By Ed Korczynski, Sr. Technical Editor, Solid State Technology

New chemical-mechanical planarization (CMP) processes for new materials planned to be used in building future IC devices are now in research and development (R&D). Early data on process trade-offs as well as on environmental, health, and safety (EHS) aspects were presented at the CMP Users Group (of the Northern California Chapter of The American Vacuum Society) meeting, held in Albany, New York on April 16 of this year in collaboration with the College of Nanoscale Science and Engineering (CNSE) SUNY Polytechnic Institute and SEMATECH.

Mike Corbett, principle with Linx Consulting, presented his company’s forecast on CMP consumable materials growth for both logic and memory. “We’re no longer in the era of 2D scaling. Right now the semiconductor industry is scaling through the use of novel materials and 3D structures. It started with memory cells going vertical for storage structures. All of these technologies rely on CMP as a key enabler:  for 3D NAND there’ll be new tungsten, TSV need new copper, and transistors need CMP for high-k/metal-gate processing.”

Corbett estimates the current global market for pre-interconnect CMP consumables—slurries, pads, and conditioning disks—at >$US1.5B annually with steady growth on the horizon. While the fabricated cost/wafer at the leading edge is estimated to increase by 25-60% when moving to the next leading-edge node, the cost of CMP consumables should only increase by 12-14%. The Figure shows the specific example of 2D NAND wafer cost increasing by 60% in moving from 20nm- to 16nm-node production, while the fab’s CMP costs increase just ~12%. Until the IC HVM industry begins using materials other than Si/SiGe for transistor channels it seems that CMP costs will be well controlled.

Fig.1: Cost modeling shows that 2D NAND memory fab cost/wafer increases 65% when moving from 20nm- to 16nm-node production, while the cost of CMP consumable materials may increase only 12% for that fab. (Source: Linx Consulting)

Alternate channel materials toxicity in CMP

With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Hsi-An Kwong, SEMATECH EHS Program Manager, provided an important overview of these issues in his presentation on “Out-gassing from III-V Wafer Processing.” Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.

With 1.5% H2O2 in a relatively low-pH slurry, phosphine was measured on the tool from InP but not from GaInP. Use of higher pH with the same 1.5% H2O2 resulted in no phosphine from InP, but arsine outgassing from GaAs. Use of the highest pH resulted in no outgassing of phosphine or arsine. “When we develop the CMP process, particularly when moving to HVM we need to study the layers on the wafer and the slurry used to evaluate if outgassing will be an issue,” explained Kwong. “FTIR is the metrology instrument needed to be able to distinguish between different evolved hydride species.” HVM fab personnel working on or near CMP tools would have to wear personal breathing apparatus if processes evolve hydrides; for example, the SEMATECH/CNSE continuous exposure EHS specification allows a maximum human exposure level of just 1.25 ppb arsine.

In technical sessions at SEMICON West in San Francisco last year, SEMATECH presented on EHS issues with CMP of III-V materials in high-volume manufacturing (HVM). Toxic hydride gases evolve during direct CMP and during over-polish of contacts. Metallic arsenic could potentially build-up on tools over time, and will have to be treated in CMP waste water. To minimize risks, dedicated CMP tools will likely be needed for R&D and for HVM.