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Posts Tagged ‘cobalt’

Companies Ready Cobalt for MOL, Gate Fill

Thursday, December 21st, 2017

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By Dave Lammers

Cobalt for middle-of-the-line and trench contacts emerged at the International Electron Devices Meeting, as Intel, GlobalFoundries, and Applied Materials discussed how to best take advantage of cobalt’s properties.

For its forthcoming 10nm logic process, Intel Corp. used cobalt for several of the lower metal levels, including a cobalt fill at the trench contacts and cobalt M0 and M1 wiring levels. The result was much-improved resistivity and reliability, compared with the traditional metallization at those levels.

Cobalt was used for the local interconnects of the Intel 10nm process, improving line resistance by 60 percent. (Source: Intel)

Chris Auth, director of logic technology at Intel’s Portland Technology Center, said the contacted line resistance “provides a good indicator of the benefits of cobalt versus tungsten,” with a 60 percent reduction in line resistance and a 1.5X reduction in contact resistance.

While cobalt was used for the local interconnects, the upper 10 metal layers were copper, with a cobalt cap used for layers M2-M5 to provide a 50X improvement in electro-migration. Intel continued to use tungsten for the gate fill.

John Pellerin, a vice president at GlobalFoundries who directs global research and development, said GlobalFoundries decided that for its 7nm logic technology, ramping in mid-2018, it would replace tungsten with cobalt at the trench contact level, which is considered the first level of the middle-of-the-line (MOL).

“We are evaluating it for implementation into the next level of contact above that. Cobalt trench level contacts are process of record (POR) for the 7nm technology,” Pellerin said in an interview at the 2017 IEDM, held Dec. 2-6 in San Francisco.

High performance logic often involves four-fin logic cells to drive the maximum amount of current from the largest transistor width. “You have to get that current out of the transistor. That is where the MOL comes into play. Junction and MOL resistance optimization is key to taking advantage of a four-fin footprint, and it takes a multi-front optimization to take advantage of that equation.

Pellerin said the biggest challenge with tungsten trench contacts is that the CVD process tends to leave a seam void. “We are always fighting seam voids. With cobalt deposition we get an intrinsic resistance improvement, and don’t get seam voids by pushing tungsten down in there,” Pellerin said.

Tighter Metal Pitches

Scotten Jones, president of consultancy IC Knowledge (Boston), said semiconductor vendors will introduce cobalt when it makes sense. Because it is a new material, requiring considerable costs prior to insertion, companies will use it when they need it.

“Global has trench contacts, while Intel uses cobalt at three levels. But the reason is that Intel has a 36nm minimum metal pitch with its 10nm process, while Global is at 40nm with its 7nm process. It is only at the point where the line gets narrow enough that cobalt starts to make sense.”

Applied Cobalt Solutions

As cobalt begins to replace tungsten at the smaller-dimension interconnect layers, Applied Materials is readying process flows and E-beam inspection solutions optimized for cobalt.

Namsung Kim, senior director of engineering management at Applied Materials, said cobalt has a bulk resistivity that is similar to tungsten, but the barrier thickness required for tungsten at leading-edge transistors is swinging the advantage to cobalt as dimensions shrink.

Line resistance probability plot of cobalt versus tungsten at 12nm critical dimensions. (Source: Applied Materials)

“Compared with tungsten, cobalt has a very thin barrier thickness, so you can fill up with more material. At our Maydan Technology Center, we’ve developed a reflow process for cobalt that is unique,” Kim said. The cobalt reflow process uses an annealing step to create larger cobalt grain sizes, reducing the resistance. And because there is no source of fluorine in the cobalt deposition steps, a thin barrier layer can suffice.

At IEDM, Naomi Yoshida, a distinguished member of the technical staff at Applied, presented a paper describing Applied’s research using cobalt to fill a 5nm-logic-generation replacement metal gate (RMG). The fill is deposited above the high-k dielectric and work function metals, and at the 5nm node and beyond there is precious little room for the gap fill metal.

Yoshida said modern transistors use multiple layers of work-function metals to control threshold voltages, with high-performance logic requiring low Vt’s and IoT devices requiring relatively high Vt’s. After the different work function layers are deposited, the fill material is deposited.

At the 5nm node, Applied Materials estimates that the contacted poly pitch (CPP) will shrink to about 42nm, while the gate length (Lg) will be less than 12nm. “There is very limited space for the fill materials, so customers need a more conductive metal in a limited space. That is the major challenge,” Yoshida said in an interview at the IEDM.

Work Function Maintained

Naomi Yoshida: room for gate fill disappearing

The Applied R&D work showed that if the barrier layer for a tungsten fill is reduced too much, to a 2nm or 3nm TiN layer for example, the effective work function (eWF) degrades by as much as 500mV eWF and the total gate conductance suffers. With the CVD process used to deposit a tungsten RMG fill, there was “significant fluorine diffusion” into the work function metal layer in the case of a 2nm TiN barrier.

By contrast, the cobalt fill maintained the NMOS band-edge eWF with the same 2nm TiN barrier.

Gradually, cobalt will be adopted more widely for the contacts, interconnects, and RMG gate fill steps. “It is time to think about how to achieve more conductance in the gate material. Previously, people said there was a negligible contribution from the gate material, but now with the smaller gates at 5nm, gate fill metal makes a huge contribution to resistance, and barrier thickness reduction is important as well,” Yoshida said.

E-beam Inspection

Nicolas Breil: E-beam void inspection useful for cobalt contacts

Applied Materials also has developed an e-beam inspection solution, ProVision, first introduced in mid-2016, and has optimized it for inspecting cobalt voids. Nicolas Breil, a director in the company’s contact module division, said semiconductor R&D organizations are busy developing cobalt contact solutions, optimizing the deposition, CMP, and other steps. “For such a dense and critical level as the contact, it always needs very careful engineering. They key is to get results as fast as possible, but being fast can be very expensive.”

Amir Wachs, business development manager at Applied’s process diagnostics and control business unit in Rehovat, Israel, said the ProVision e-beam inspection system has a resolution of 1nm, at 10,000-20,000 locations per hour, taking a few hundred measurements on each field of view.

“Voids form when there are adhesion issues between the cobalt and TiN. One of the key issues is the correct engineering of the Ti nitride and PVD cobalt and CVD cobalt. To detect embedded voids requires a TEM inspection, but then customers get very limited statistics. There might be a billion contacts per chip, and with conventional TEM you might get to inspect two.”

The ProVision system speeds up the feedback loop between inspection and co-optimization. “Customers can assess the validity of the optimization. With other inspection methods, co-optimization might take five days to three weeks. With this type of analysis, using ProVision, customers can do tests early in the flow and validate their co-optimization within a few hours,” Wachs said.

Innovations at 7nm to Keep Moore’s Law Alive

Thursday, January 19th, 2017

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By Dave Lammers, Contributing Editor

Despite fears that Moore’s Law improvements are imperiled, the innovations set to come in at the 7nm node this year and next may disprove the naysayers. EUV lithography is likely to gain a toehold at the 7nm node, competing with multi-patterning and, if all goes well, shortening manufacturing cycles. Cobalt may replace tungsten in an effort to reduce resistance-induced delays at the contacts, a major challenge with finFET transistors, experts said.

While the industry did see a slowdown in Moore’s Law cost reductions when double patterning became necessary several years ago, Scotten Jones, who runs a semiconductor consultancy focused on cost analysis, said Intel and the leading foundries are back on track in terms of node-to-node cost improvements.

Speaking at the recent SEMI Industry Strategy Symposium (ISS), Jones said his cost modeling backs up claims made by Intel, GlobalFoundries, and others that their leading-edge processes deliver on die costs. Cost improvements stalled at TSMC for the16nm node due to multi-patterning, Jones said. “That pause at TSMC fooled a lot of people. The reality now may surprise those people who said Moore’s Law was dead. I don’t believe that, and many technologists don’t believe that either,” he said.

As Intel has adopted a roughly 2.5-year cadence for its more-aggressive node scaling, Jones said “the foundries are now neck and neck with Intel on density.” Intel has reached best-ever yield levels with its finFET-based process nodes, and the foundries also report reaching similar yield levels for their FinFET processes. “It is hard, working up the learning curve, but these companies have shown we can get there,” he said.

IC Knowledge cost models show the chip industry is succeeding in scaling density and costs. (Source: Scotten Jones presentation at 2017 SEMI ISS)

TSMC, spurred by its contract with Apple to supply the main iPhone processors, is expected to be first to ship its 7nm products late this year, though its design rules (contacted poly pitch and minimum metal pitch) are somewhat close to Intel’s 10nm node.

While TSMC and GlobalFoundries are expected to start 7nm production using double and quadruple patterning, they may bring in EUV lithography later. TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node. Samsung has put its stake in the ground to use EUV rather than quadruple patterning in 2018 for critical layers of its 7nm process. Jones, president of IC Knowledge LLC, said Intel will have the most aggressive CPP and MPP pitches for its 7nm technology, and is likely to use EUV in 2019-2020 to push its metal pitches to the minimum possible with EUV scanners.

EUV progress at imec

In an interview at the 62nd International Electron Devices Meeting (IEDM) in San Francisco in early December, An Steegen, the senior vice president of process technology at Imec (Leuven, Belgium), said Imec researchers are using an ASML NXE 3300B scanner with 0.3 NA optics and an 80-Watt power supply to pattern about 50 wafers per hour.

“The stability on the tool, the up time, has improved quite a lot, to 55 percent. In the best weeks we go well above 70 percent. That is where we are at today. The next step is a 125-Watt power supply, which should start rolling out in the field, and then 250 Watts.”

Steegen said progress is being made in metal-containing EUV resists, and in development of pellicles “which can withstand hydrogen in the chamber.”

If those challenges can be met, EUV would enable single patterning for vias and several metal layers in the middle of the line (MOL), using cut masks to print the metal line ends. “For six or seven thin wires and vias, at the full (7nm node) 32nm pitch, you can do it with a single exposure by going to EUV. The capability is there,” Steegen said.

TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.”

Huiming Bu was peppered with questions following a presentation of the IBM Alliance 7nm technology at IEDM.

Huiming Bu, who presented the IBM Alliance 7nm paper at IEDM, said “EUV delivers significant depth of field (DoF) improvement” compared with the self-aligned quadruple (SAQP) required for the metal lines with immersion scanners.

A main advantage for EUV compared with multi-patterning is that designs would spend fewer days in the fabs. Speaking at ISS, Gary Patton, the chief technology officer at GlobalFoundries, said EUV could result in 30-day reductions in fab cycle times, compared with multiple patterning with 193nm immersion scanners, based on 1.5 days of cycle time per mask layer.

Moreover, EUV patterns would produce less variation in electrical performance and enable tighter process parameters, Patton said.

Since designers have become accustomed to using several colors to identify multi-patterning layers for the 14nm node, the use of double and quadruple patterning at the 7nm node would not present extraordinary design challenges. Moving from multi-patterning to EUV will be largely transparent to design teams as foundries move from multi-patterning to EUV for critical layers.

Interconnect resistance challenges

As interconnects scale and become more narrow, signals can slow down as electrons get caught up in the metal grain boundaries. Jones estimates that as much as 85 percent of parasitic capacitance is in the contacts.

For the main interconnects, nearly two decades ago, the industry began a switch from aluminum to copper. Tungsten has been used for the contacts, vias, and other metal lines near the transistor, partly out of concerns that copper atoms would “poison” the nearby transistors.

Tungsten worked well, partly because the bi-level liner – tantalum nitride at the interface with the inter-level dielectric (ILD) and tantalum at the metal lines – was successful at protecting against electromigration. The TaN-Ta liner is needed because the fluorine-based CVD processes can attack the silicon. For tungsten contacts, Ti serves to getter oxygen, and TiN – which has high resistance — serves as an oxygen and fluorine barrier.

However, as contacts and MOL lines shrunk, the thickness of the liner began to equal the tungsten metal thicknesses.

Dan Edelstein, an IBM fellow who led development of IBM’s industry-leading copper interconnect process, said a “pinch point” has developed for FinFETs at the point where contacts meet the middle-of-the-line (MOL) interconnects.

“With cobalt, there is no fluorine in the deposition process. There is a little bit of barrier, which can be either electroplated or deposited by CVD, and which can be polished by CMP. Cobalt is fairly inert; it is a known fab-friendly metal,” Edelstein said, due to its longstanding use as a silicide material.

As the industry evaluated cobalt, Edelstein said researchers have found that cobalt “doesn’t present a risk to the device. People have been dropping it in, and while there are still some bugs that need to be worked out, it is not that hard to do. And it gives a big change in performance,” he said.

Annealing advantages to Cobalt

Contacts are a “pinch point” and the industry may switch to cobalt (Source: Applied Materials)

An Applied Materials senior director, Mike Chudzik, writing on the company’s blog, said the annealing step during contact formation also favors cobalt: “It’s not just the deposition step for the bulk fill involved – there is annealing as well. Co has a higher thermal budget making it possible to anneal, which provides a superior, less granular fill with no seams and thus lowers overall resistance and improves yield,” Chudzik explained.

Increasing the volume of material in the contact and getting more current through is critical at the 7nm node. “Pretty much every chipmaker is working aggressively to alleviate this issue. They understand if it’s not resolved then it won’t matter what else is done with the device to try and boost performance,” Chudzik said.

Prof. Koike strikes again

Innovations underway at a Japanese university aim to provide a liner between the cobalt contact fill material and the adjacent materials. At a Sunday short course preceding the IEDM, Reza Arghavani of Lam Research said that by creating an alloy of cobalt and approximately 10 percent titanium, “magical things happen” at the interfaces for the contact, M0 and M1 layers.

The idea for adding titanium arose from Prof. Junichi Koike at Tohoku University, the materials scientist who earlier developed a manganese-copper solution for improved copper interconnects. For contacts and MOL, the Co-Ti liner prevents diffusion into the spacer oxide, Arghavani said. “There is no (resistance) penalty for the liner, and it is thermally stable, up to 400 to 500 degrees C. It is a very promising material, and we are working on it. W (tungsten) is being pushed as far as it can go, but cobalt is being actively pursued,” he said.

Stressor changes ahead

Presentations at the 2016 IEDM by the IBM Alliance (IBM, GlobalFoundries, and Samsung) described the use of a stress relaxed buffer (SRB) layer to induce stress, but that technique requires solutions for the defects introduced in the silicon layer above it. As a result of that learning process, SRB stress techniques may not come into the industry until the 5 nm node, or a second-generation 7nm node.

Technology analyst Dick James, based in Ottawa, said over the past decade companies have pushed silicon-germanium stressors for the PFET transistors about as far as practical.

“The stress mechanisms have changed since Intel started using SiGe at the 90nm node. Now, companies are a bit mysterious, and nobody is saying what they are doing. They can’t do tensile nitride anymore at the NFET; there is precious little room to put linear stress into the channel,” he said.

The SRB technique, James said, is “viable, but it depends on controlling the defects.” He noted that Samsung researchers presented work on defects at the IEDM in December. “That was clearly a research paper, and adding an SRB in production volumes is different than doing it in an R&D lab.”

James noted that scaling by itself helps maintain stress levels, even as the space for the stressor atoms becomes smaller. “If companies shorten the gate length and keep the same stress as before, the stress per nanometer at least maintains itself.”

Huiming Bu, the IBM researcher, was optimistic, saying that the IBM Alliance work succeeded at adding both compressive and tensile strain. The SRB/SSRW approach used by the IBM Alliance was “able to preserve a majority – 75 percent – of the stress on the substrate.”

Jones, the IC Knowledge analyst, said another area of intense interest in research is high-mobility channels, including the use of SiGe channel materials in the PMOS FinFETS.

He also noted that for the NMOS finFETs, “introducing tensile stress in fins is very challenging, with lots of integration issues.” Jones said using an SRB layer is a promising path, but added: “My point here is: Will it be implemented at 7 nm? My guess is no.”

Putting it in a package

Steegen said innovation is increasingly being done by the system vendors, as they figure out how to combine different ICs in new types of packages that improve overall performance.

System companies, faced with rising costs for leading-edge silicon, are figuring out “how to add functionality, by using packaging, SOC partitioning and then putting them together in the package to deliver the logic, cache, and IOs with the right tradeoffs,” she said.

Blog review June 2, 2014

Monday, June 2nd, 2014

The Internet of Things alone will surpass the PC, tablet and phone market combined by 2017, with a global internet device installed base of around 7,500,000,000 devices. Speaking at ASMC, TSMC’s John Lin said in addition to a continued push to smaller geometries and ultra-low power, the company will focus on “special” technologies such as image sensor, embedded DRAMs, high-voltage power ICs, RF, analog, and embedded flash. “All this will support all of the future Internet of Things,” he said.

Kavita Shah of Applied Materials blogs about the company’s new Volta system. She says desighed to alleviate roadblocks to copper interconnect scaling beyond the 2Xnm node through two enabling applications—a conformal cobalt liner and a selective cobalt capping layer, which together completely encapsulate the copper wiring.

In an interview, Christophe Maleville, Senior Vice President of Soitec’s Microelectronics Business Unit, talks about why FD-SOI provides a much better combination of power consumption, performance and cost than any alternative. Talking about Samsung’s move to FDSOI, he said “at 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node.”

Phil Garrou continues his analysis of presentations from the recent SEMI 2.5/3D IC forum in Singapore. In his third blog post on the topic, he reviews Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” which focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology.

Vivek Bakshi blogs that it takes a large infrastructure to make EUVL a manufacturing technology. So many tool suppliers, large and small, want to know when EUVL will be inserted into fabs for production and how and how much it will be used. Their business depends on these answers and some, especially smaller suppliers, are getting cold feet as delays in EUVL readiness continue. The answers to these questions mostly depend on knowing what we can expect from sources in the short- and near term, but there are many additional questions one must ask as well.

Karen Lightman of the MEMS Industry Group blogs about recent events in Japan, including the MIG Conference Japan. The focus of the conference was on navigating the challenges of the global MEMS supply chain. Several of the speakers gave their no-holds-barred view of these challenges, including the keynote from Sony Communications, Takeshi Ito, Chief Technology Officer, Head of Technology, Sony Mobile Communications.

Solid State Watch: May 9-15, 2014

Friday, May 16th, 2014
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