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Posts Tagged ‘CMOS’

IEDM: Thanks for MEMS-ories

Tuesday, December 16th, 2014

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By Jeff Dorsch, Contributing Editor

At the 60th annual International Electron Devices Meeting this week in San Francisco, there was much buzz about the 14-nanometer FinFET papers being presented by IBM and Intel. Those papers were the subject of a press release two months in advance.

Getting less attention at IEDM 2014 were the papers on sensors, microelectromechanical systems (MEMS) devices and bio-MEMS. This technology generates fewer headlines, although it is present in smartphones, fitness trackers, and many other electronic products.

Monday afternoon, December 15, saw the first MEMS-related papers presented at the conference, on nanoelectromechanical systems (NEMS) and energy harvesters. Donald Gardner of Intel, an IEEE Fellow, presented a paper on “Integrated On-Chip Energy Storage Using Porous-Silicon Electrochemical Capacitors,” which was supported by research at Florida International University and the University of Turku.

Gardner described how porous-silicon nanostructures were synthesized and passivated with titanium nitride through atomic-level deposition or with carbon through chemical vapor deposition. These coatings helped keep the porous silicon from oxidizing, he explained.

These electrochemical capacitors, an alternative to batteries, produced with the porous silicon could be used in energy harvesting and some applications in energy storage, according to the authors of the paper.

Session 8 of the IEDM conference also included a paper authored by France’s Institute of Electronics, Microelectronics and Nanotechnology (IEMN) and STMicroelectronics, “Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements.” Maciej Haras presented the paper. He noted that 55 percent to 60 percent of energy used is released as waste heat. Harvesting energy from such heat could be a significant source of power generation in the future.

“Thermoelectricity is quite unpopular on the market,” Haras noted. Toxic materials, such as antimony, bismuth, lead, and tellurium, could be replaced by silicon, germanium or silicon germanium (SiGe) could to produce CMOS-compatible thermoelectrics, he said.

In energy conversion efficiency, silicon that is only 10 nanometers thick is 10 times more efficient than bulk silicon, Haras said.

Session 15 on Tuesday morning, December 16, was devoted to “Graphene Devices, Biosensors and Photonics.” This session featured some of the longest paper titles at the conference, such as “An Ultra-Sensitive Resistive Pressure Sensor Based on the V-Shaped Foam-like Structure of Laser-Scribed Graphene,” “A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development,” and “Label-Free Optical Biochemical Sensor Realized by a Novel Low-Cost Bulk-Silicon-based CMOS Compatible 3-Dimensional Optoelectronic IC (OEIC) Platform.”

Other papers were more direct, with shorter titles, such as “Flexible, Transparent Single-Layer Graphene Earphone,” which was about exactly that, and “An Integrated Tunable Laser Using Nano-Silicon-Photonic Circuits.”

Coming up on Tuesday afternoon is Session 22, devoted to MEMS and resonator technology, with six papers scheduled.

The nuts and bolts of MEMS and NEMS technology can be quite esoteric, yet such devices are crucial to the future of electronics.

Germanium Junctions for CMOS

Tuesday, November 25th, 2014

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By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases.  Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Fig.1: Sheet-resistance (Rs) versus RTA temperatures for P, As, and Sb implanted dopants into Ge and Si. (Source: Borland)

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Fig. 2: Cross-section TEM of 1µm Ge-epi after 625°C and 900°C RTA, showing great reduction in stacking-faults with the higher annealing temperature. (Source: Borland)

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

— E. K.

Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D

Monday, June 16th, 2014

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Karim Arabi, Qualcomm VP of Engineering, voiced the strongest support and provided many details of monolithic 3D’s role, in his keynote at this year’s DAC. A good summary was posted at the Tech Design Forums site under the title “3D and EDA need to make up for Moore’s Law, says Qualcomm.” In this blog, I’ll highlight some of the very interesting quotes from Arabi’s keynote: “Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase. One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore”

Qualcomm is not the only fabless company voicing its concern with cost. Early in 2013 Nvidia said it is “deeply unhappy” and executives of Broadcom followed suite. The following chart, presented by ARM, illustrates it nicely.

But it seems that the problem is even more severe than that. In our blog Moore’s Law has stopped at 28nm we examined the expected increase of SoC cost due to poor scaling of embedded SRAM (eSRAM). We should note that the chart above, like many others, is about the cost per transistor associated with dimensional scaling. Escalating lithography cost causes escalating wafer cost, which neutralizes the 2X transistor density increases.

Yet eSRAM scales far less than 2X and, accordingly, for most SOCs, scaling would be even more costly. This issue has been confirmed again with the recent VLSI 2014 paper “10-nm Platform Technology Featuring FinFET on Bulk and SOI” by Samsung, IBM, STMicroelectronics, GLOBALFOUNDRIES and UMC. They presented that the size of their 10nm bitcell is 0.053 µm², which is only 25 percent smaller than the 0.07 µm² reported for 14nm bitcell size. One should expect that an additional area penalty would occur for effective use in large memory blocks, as reported even for 14nm, which could bring the effective SRAM scaling to only about 15 percent, a long way from the 50 percent required to neutralize the escalating wafer costs.

However, cost is not the only issue that forced Qualcomm to consider monolithic 3D. Quoting Arabi:

“Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs. Through-silicon vias and micro bumps are useful where you need I/Os … But they are not really solving the interconnect issue I’m talking about … So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller.”

The interconnect issue was also addressed at IEDM 2013 by Geoffrey Yeap, Qualcomm VP of Technology, in his invited talk:

“As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.”

Yeap provided the following chart for the growing gap between transistor delay and interconnect delay:

Arabi DAC 2014 keynote was also reported on Cadence’s website, which provides our final Arabi quote for this blog: Qualcomm is looking at “monolithic” 3D-ICs that use normal vias between stacked dies. This can provide a one-process-node advantage along with a 30 percent power savings, 40 percent performance gain, and 5-10 percent cost savings.

Clearly, monolithic 3D integration has a very important role in the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3DIC, and researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

The Week in Review: May 9, 2014

Friday, May 9th, 2014

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.

Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.

BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.

Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.

Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.

Research Alert: Dec. 3, 2013

Tuesday, December 3rd, 2013

Imec integrates CCD and CMOS technology to improve performance of CMOS imagers

Imec, the Belgian nanoelectronics research center, will present at this week’s ‘CMOS Image Sensors for High Performance Applications’ workshop in Toulouse (France) a prototype of a high-performance, time-delay-integration (TDI) image sensor. The image sensor is based on imec’s proprietary embedded charge-coupled device (CCD) in CMOS technology. Imec developed and fabricated the sensor for the French Space Agency, CNES, which plans to utilize the technology for space-based earth observation.

The prototype image sensor combines a light-sensitive, CCD-based TDI pixel array with peripheral CMOS readout electronics. By integrating CCD with CMOS technology, imec combined the best of both worlds. The CCD pixel structure delivers low-noise TDI performance in the charge domain, while CMOS technology enables low-power, on-chip integration of fast and complex circuitry readouts.

A TDI imager is a linear device that utilizes a clever synchronization of the linear motion of the scene with multiple samplings of the same image, thereby increasing the signal to noise ratio. CCDs fit extremely well with the TDI application since they operate in the charge domain, enabling the movement of charges without creating excess noise. By combining the TDI pixels array with CMOS readout circuitry on the same die, imec produced a camera-on-a-chip or system-on-a-chip (SOC) imager, which reduces the overall system complexity and cost. The CMOS technology enables on-chip readout electronics, such as clock drivers and analog-to-digital convertors (ADCs), operating at higher speeds and lower power consumption not possible with traditional CCD technology.

The prototypes were fabricated using imec’s 130nm process with an additional CCD process module. An excellent charge transfer efficiency of 99.9987 % has been measured ensuring almost lossless transport of charges in the TDI array, and guaranteeing high image quality. Imec’s specialty imaging platform combines custom design (i.e., specialized pixels, high-performance readout circuits and chip architectures) with optimized silicon processing, such as dedicated implants and backside thinning, to achieve high-end specialized imagers.

New thermoelectronic generator

Through a process known as thermionic conversion, heat energy — such as light from the sun or heat from burned fossil fuels — can be converted into electricity with very high efficiency. Because of its promise, researchers have been trying for more than half a century to develop a practical thermionic generator, with little luck. That luck may soon change, thanks to a new design — dubbed a thermoelectronic generator — described in AIP Publishing’s Journal of Renewable and Sustainable Energy (JRSE).

Thermionic generators use the temperature difference between a hot and a cold metallic plate to create electricity. “Electrons are evaporated or kicked out by light from the hot plate, then driven to the cold plate, where they condense,” explained experimental solid-state physicist Jochen Mannhart of the Max Planck Institute for Solid State Research in Stuttgart, Germany, the lead author of the JRSE paper. The resulting charge difference between the two plates yields a voltage that, in turn, drives an electric current, “without moving mechanical parts,” he said.

Nanoscale coating improves stability and efficiency of devices for renewable fuel generation

Splitting water into its components, two parts hydrogen and one part oxygen, is an important first step in achieving carbon-neutral fuels to power our transportation infrastructure – including automobiles and planes.

Now, North Carolina State University researchers and colleagues from the University of North Carolina at Chapel Hill have shown that a specialized coating technique can make certain water-splitting devices more stable and more efficient.

Atomic layer deposition, or “ALD,” coats three-dimensional structures with a precise, ultra-thin layer of material. “An ALD coating is sort of like the chocolate glaze on the outside of a Klondike bar – just much, much thinner,” explains Dr. Mark Losego, research assistant professor of chemical and biomolecular engineering at NC State and a co-author on the work. “In this case, the layers are less than one nanometer thick – or almost a million times thinner than a human hair.”

A graphic representation of how atomic layer deposition can aid renewable hydrogen fuel generation. Two papers published in Proceedings of the National Academy of Sciences show how atomic layer deposition can make water-splitting devices more stable and more efficient.

Although extremely thin, these coatings improve the attachment and performance of surface-bound molecular catalysts used for water-splitting reactions in hydrogen-fuel-producing devices.

In the first paper, “Solar water splitting in a molecular photoelectrochemical cell,” the researchers used ALD coatings on nanostructured water-splitting cells to improve the efficiency of electrical current flow from the molecular catalyst to the device. The findings significantly improved the hydrogen generating capacity of these molecular-based solar water-splitting cells.

In the second paper, “Crossing the divide between homogeneous and heterogeneous catalysis in water oxidation,” the researchers used ALD to “glue” molecular catalysts to the surface of water-splitting electrodes in order to make them more impervious to detachment in non-acidic water solutions. This improved stability at high pH enabled a new chemical pathway to water splitting that is one million times faster than the route that had been previously identified in acidic, or low pH, environments. These findings could have implications in stabilizing a number of other molecular catalysts for other renewable energy pathways, including the conversion of carbon dioxide to hydrocarbon fuels.

“In these reports, we’ve shown that nanoscale coatings applied by ALD can serve multiple purposes in water-splitting technology, including increasing hydrogen production efficiency and extending device lifetimes,” Losego said. “In the future, we would like to build devices that integrate both of these advantages and move us toward other fuels of interest, including methanol production.”

Blog Review: November 25, 2013

Monday, November 25th, 2013

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs about a recent announcement by Intel CEO Brian Krzanich on company expansion focused on a foundry plan. Or-Bach said that if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of the other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

Vivek Bakshi, EUV Litho, Inc. reports on work presented at the 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland), including data on the readiness of 50 W EUV sources to support EUVL scanners. At the meeting, keynoter Vadim Banine of ASML said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field. ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

At the GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Phil Garrou reports on the workshop, including presentations from Ron Huemoeller of Amkor and David McCann of GLOBALFOUNDRIES.

Pete Singer provides a preview of a special focus session at the upcoming IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013. The session covers many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Dr. Lianfeng Yang of ProPlus Design Solutions, Inc., blogs that these days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

Research News: Nov. 5, 2013

Tuesday, November 5th, 2013

Imec, a nanoelectronics research center, announced today that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon. The breakthrough not only enables continual CMOS scaling down to 7nm and below, but also enables new heterogeneous system opportunities in hybrid CMOS-RF and CMOS-optoelectronics. “To our knowledge, this is the world’s first functioning CMOS compatible IIIV FinFET device processed on 300mm wafers,” stated An Steegen, senior vice president core CMOS at imec. “This is an exciting accomplishment, demonstrating the technology as a viable next-generation alternative for the current state-of-the-art Si-based FinFET technology in high volume production.”

Columbia Engineering researchers have experimentally demonstrated for the first time that it is possible to electrically contact an atomically thin two-dimensional (2D) material only along its one-dimensional (1D) edge, rather than contacting it from the top, which has been the conventional approach. With this new contact architecture, they have developed a new assembly technique for layered materials that prevents contamination at the interfaces, and, using graphene as the model 2D material, show that these two methods in combination result in the cleanest graphene yet realized. The study is published in Science on November 1, 2013. The researchers fully encapsulated the 2D graphene layer in a sandwich of thin insulating boron nitride crystals, employing a new technique in which crystal layers are stacked one-by-one. Once they created the stack, they etched it to expose the edge of the graphene layer, and then evaporated metal onto the edge to create the electrical contact. By making contact along the edge, the team realized a 1D interface between the 2D active layer and 3D metal electrode. And, even though electrons entered only at the 1D atomic edge of the graphene sheet, the contact resistance was remarkably low, reaching 100 Ohms per micron of contact width—a value smaller than what can be achieved for contacts at the graphene top surface.

UPV/EHU-University of the Basque Country researchers have developed and patented a new source of light emitter based on boron nitride nanotubes and suitable for developing high-efficiency optoelectronic devices. Scientists are usually after defect-free nano-structures. Yet in this case the UPV/EHU researcher Angel Rubio and his collaborators have put the structural defects in boron nitride nanotubes to maximum use. The outcome of his research is a new light-emitting source that can easily be incorporated into current microelectronics technology. The research has also resulted in a patent.

Crossbar Unveils Resistive RAM with Simple, Three-Layer Structure

Sunday, September 1st, 2013

By Pete Singer

Crossbar, Inc., a start-up company, unveiled a new Resistive RAM (RRAM) technology that will be capable of storing up to one terabyte (TB) of data on a single 200mm2 chip. A working memory was produced array at a commercial fab, and Crossbar is entering the first phase of productization. “We have achieved all the major technical milestones that prove our RRAM technology is easy to manufacture and ready for commercialization,” said George Minassian, chief executive officer, Crossbar, Inc. The company is backed by Artiman Ventures, Kleiner Perkins Caufield & Byers and Northern Light Venture Capital.

The technology, which was conceived by Professor Wei Lu of the University of Michigan, is based on a simple three-layer structure of silver, amorphous silicon and silicon (FIGURE 1). The resistance switching mechanism is based on the formation of a filament in the switching material when a voltage is applied between the two electrodes. Minassian said the RRAM is very stable, capable of withstanding temperature swings up to 125°C, with up to 10,000 cycles, and a retention of 10 years. “The filaments are rock solid,” he said.

Crossbar has filed 100 unique patents, with 30 already issued, relating to the development, commercialization and manufacturing of RRAM technology.

After completing the technology transfer to Crossbar’s R&D fab and technology analysis and optimization, Crossbar has now successfully developed its demonstration product in a commercial fab. This working silicon is a fully integrated monolithic CMOS controller and memory array chip. The company is currently completing the characterization and optimization of this device and plans to bring its first product to market in the embedded SOC market.

Sherry Garber, Founding Partner, Convergent Semiconductors, said: “RRAM is widely considered the obvious leader in the battle for a next generation memory and Crossbar is the company most advanced to show working demo that proves the manufacturability of RRAM. This is a significant development in the industry, as it provides a clear path to commercialization of a new storage technology, capable of changing the future landscape of electronics innovation.”

FIGURE 1. The resistance switching mechanism of Crossbar’s technology is based on the formation of a filament in the silicon-based switching material when a voltage is applied between the two electrodes.

Crossbar technology can be stacked in 3D, delivering multiple terabytes of storage on a single chip. Its simplicity, stackability and CMOS compatibility enables logic and memory to be integrated onto a single chip at the latest technology node (FIGURE 2).

Crossbar’s technology will deliver 20x faster write performance; 20x lower power consumption; and 10x the endurance at half the die size, compared to today’s best-in-class NAND Flash memory. Minassian said the biggest advantage of the technology is its simplicity. “That allowed us in three years time to get from technology understanding, characterization, cell array and put a device together,” he said.

Minassian said RRAM compares favorably with NAND, which is getting more complex and expensive. “In 3D NAND, you put all of these thing layers of top of each other – 32 layers, or 64 or 128 in some cases – then you have to etch them, you have to slice them all at once and the equipment required for that accuracy and that geometry is very expensive. This is one of the reasons that 3D has been very difficult for NAND to be introduced.” With the Crossbar approach, “you’re always dealing with three layers. It’s much easier to stack these and it gives you a huge density advantage,” Minassian said.

“The switching media is highly resistive,” explains Minassian. “If you try to read the resistance between top and bottom electrode without doing anything, it’s a high resistance. That’s the off state. To turn on the device, we apply a positive voltage to the top electrode. That ionizes the metal on the top layer and puts the metal ions into the switching media. The metal ions form a filament that connect the top and bottom electrode. The moment they hit the bottom electrode, you have a short, which means that the top and bottom electrode are connected which means they have a low resistance.” The low resistance state is the on state. He said that although silver is not commonly used in front-end CMOS processing, the RRAM memory formation process is a back-end process. “You produce all your CMOS and then right before the device exits the fab, you put the silver on top,” he said. The silver is deposited, encapsulated, etched and then packaged. “That equipment is available, you just have to isolate it at the end,” Minassian said.

FIGURE 2. Crossbar’s simple and scalable memory cell structure enables a new class of 3D RRAM which can be incorporated into the back end of line of any standard CMOS manufacturing fab.

The approach is also CMOS compatible, with processes used to fabricate the memory layers all running at less than 400°C. “This allows you to not only be CMOS compatible, but it allows you to stack more and more of these memory layers on top of each other,” Minassian said. “You can put the logic, the controllers and microprocessors, next to the memory in the same die. That allows you to simplify packaging and increase performance.”

Another advantage compared to NAND is that the controllers used to address the cells can be less complicated. Minassian said that in conventional cells, 30 electrons are required to produce 1 Volt. “If you shrink that to a smaller node, the number of electrons is less. Fewer electrons are much harder to detect. You need a massive controller that does error recovery and complex coding so if the bits are changed, it can still provide you the right program to execute.” Also, because the Crossbar RRAM is capable of 10,000 write cycles, less complicated controllers are needed. Today’s NAND is capable of only 1000 write cycles. “If you write information 1000 times, that cell is destroyed. It will not contain or maintain the information. You have this complex controller that keeps track of how many cells have been written, how many times, to make sure all of them are aged equally,” Minassian said.

Non-volatile memory, expected to grow to become a $60 billion market in 2013, is the most common storage technology used for both code storage (NOR) and data storage (NAND) in a wide range of electronics applications. Crossbar plans to bring to market standalone chip solutions, optimized for both code and data storage, used in place of traditional NOR and NAND Flash memory. Crossbar also plans to license its technology to SOC developers for integration into next-generation systems-on-chips (SOC).

Michael Yang, Senior Principal Analyst, Memory and Storage, IHS, said: “Ninety percent of the data we store today was created in the past two years. The creation and instant access of data has become an integral part of the modern experience, continuing to drive dramatic growth for storage for the foreseeable future. However, the current storage medium, planar NAND, is seeing challenges as it reaches the lower lithographies, pushing against physical and engineering limits. The next generation non-volatile memory, such as Crossbar’s RRAM, would bypass those limits, and provide the performance and capacity necessary to become the replacement memory solution.”


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