Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘CMOS image sensors’

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016

thumbnail

By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

Conference Features “The Year of Stacked Memory” in 2015

Thursday, December 17th, 2015

By Jeff Dorsch, Contributing Editor

The theme of this year’s 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is “The Year of Stacked Memory,” noting how memory die stacked in one package are becoming more commonplace in 2015.

Put on by RTI International, the 3D ASIP conference is in its 12th year. Attendees and presenters are generally people involved in chip packaging, from academia and industry.

One presentation on Wednesday (December 16) was by Teruo Hirayama of Sony, which has a long history of developing CMOS image sensors, dating back to 1998 with the graphics synthesizer for the PlayStation 2 video-game console, employing embedded DRAMs.

Embedded DRAMs present a number of manufacturing challenges, such as requiring four photomasks at the time, compared with three masks for commodity DRAMs and two or so masks for “pure logic” chips, Hirayama noted.

To address the issue, Sony turned to “chip-on-chip” technology, combining the merits of system-on-a-chip devices and system-in-package technology, according to Hirayama. The chipmaker later resorted to stacked CMOS image sensors, which offer a cost advantage over conventional CMOS image sensors.

During fiscal 2014, stacked CMOS image sensors accounted for 64 percent of Sony’s CMOS image sensor shipments, with back-illuminated image sensors representing 31 percent and front-illuminated image sensors 5 percent, Hirayama reported.

For future directions in stacked image sensors, Hirayama pointed to connecting pixels to analog-to-digital converters, with a device that has memory, a microelectromechanical system device, and a radio-frequency chip on the bottom layer, topped with a logic device, the ADC, and pixels, in that order.

The conference also heard Wednesday from Bryan Black of Advanced Micro Devices, a senior AMD fellow who spearheaded development of the company’s Fiji graphics processing unit.

The project started in 2007 and took 8.5 years to complete, Black said. “The industry needed a new memory system,” he commented. “We ended up with a die-stacking solution.”

Virtual prototyping was employed along the way, according to Black.

With a silicon interposer measuring 1,011 square millimeters and an ASIC coming in at 592 square millimeters, with four high-bandwidth memories, the Fiji GPU module is a big device. “We realized the part was going to be much bigger than we expected,” Black recalled. “Then we realized this thing would be huge.”

Wrapping up on Wednesday, the conference also heard presentations by three suppliers of semiconductor production equipment – EV GroupSPTS Technologies, and Rudolph Technologies.

The Week In Review: Jan. 10, 2014

Friday, January 10th, 2014

This week in Las Vegas, the 2014 International Consumer Electronics Show focused on the Internet of Things, displaying many connected gadgets and services. This year’s show featured more than 3,200 exhibitors, many of which were excited to show off new Internet-enable devices.

As of December 2013, Samsung had the most installed wafer capacity with nearly 1.9 million 200mm-equivalent wafers per month.  That represented 12.6 percent of the world’s total capacity and most of it used for the fabrication of DRAM and flash memory devices.  Next in line was the largest pure-play foundry in the world TSMC with about 1.5 million wafers per month capacity, or 10.0% of total worldwide capacity.  Following TSMC were memory IC suppliers Micron, Toshiba/SanDisk, and SK Hynix.

Xicato announced that it has relocated its San Jose headquarters to accommodate a new manufacturing line for the company’s next generation of products. The new 24 thousand-square-foot space is more than double the size of Xicato’s previous San Jose facility. The privately held company has invested millions of dollars in equipment and resources to meet the increasing global demand for its LED modules.

Toshiba Corporation announced the development of “Bright Mode,” a CMOS image sensor technology that allows smartphones and tablets to record full HD video at 240 frames per second (fps), the industry’s highest frame rate. “Bright Mode” realizes high quality slow motion playback.

The TOWA Corporation of Japan, a supplier of packaging equipment for semiconductor, electronics and LED industries, has decided to expand their activities in Europe with an Innovation Center for Packaging Development and announced the launch of TOWA Europe B.V.