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Posts Tagged ‘chip design’

Cadence Adds New Tools for Analog Design, Enhances Layout

Wednesday, April 6th, 2016

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By Jeff Dorsch, Contributing Editor

Cadence Design Systems today is introducing new tools within its Virtuoso Analog Design Environment (ADE), along with enhancements to the Virtuoso Layout Suite.

New to Virtuoso ADE are the Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier.

“The new Virtuoso ADE Verifier technology and the Virtuoso ADE Assembler technology run plan capability make our design teams more productive,” said Yanqiu Diao, deputy general manager of the Turing Processor business unit at HiSilicon Technologies Co., Ltd. “Through our early use of the new Cadence Virtuoso ADE product suite, we’ve found that we can improve analog IP verification productivity by approximately 30 percent and reduce verification issues by one-half. Our smartphone and network chip projects should benefit from these latest capabilities.”

Steve Lewis, product marketing director for Cadence’s Custom IC & PCB Group, said the electronic design automation company’s Virtuoso ADE L, XL, and GXL tools “will be kept, will be maintained, and taking that technology to the next level.”

Virtuoso ADE Verifier is “the brand-new kid on the block,” Lewis said in an interview. The tool advances analog verification technology, according to Cadence, and offers an integrated dashboard for engineers to employ.

Under international standards for automotive vehicles, medical equipment, military/aerospace systems, and other products, suppliers “have to trace every aspect of your design,” he noted. “All has to be documented.”

The digital side of chip design addressed those issues about a decade ago, according to Lewis. Such recordkeeping and documentation are “far less common on the analog,” he said. “It’s no longer okay to say the analog takes care of itself.”

Changes in analog design projects were typically tracked in spreadsheet programs, which don’t connect to the Virtuoso suite, Lewis noted, adding, “Now, I know who’s working on what.”

The new analog design tools “add a little bit more granularity” with real-number models, Lewis said. “It’s not quite SPICE,” he admitted.

Regarding Virtuoso ADE Assembler, “we made it look like ADE XL,” Lewis said, so users should have a shorter learning curve with the new tool. Virtuoso ADE Explorer provides what Cadence calls a complete corners and Monte Carlo environment for finding and correcting variation problems.

Cadence is also offering a Virtuoso Variation Option, providing fast Monte Carlo analysis for FinFET chips with 16-nanometer or smaller dimensions.

The enhancements in Virtuoso Layout Suite are a 10x to 100x improvement in graphics rendering performance, real-time customization of Module Generators with a simpler and more visual approach; and new structured device-level routing capabilities that are said to enhance routing productivity by up to 50 percent.

“We actually made significant changes in layout for L, XL,” addressing “current techniques, current designs,” Lewis commented.

Cadence Virtuoso Analog Design Environment (ADE): Reimagining analog design with emphasis on usability, performance, and innovation

Goodbye, EDAC; Hello, ESD Alliance

Friday, April 1st, 2016

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By Jeff Dorsch, Contributing Editor

The Electronic Design Automation Consortium (EDAC) is no more. The industry organization, founded in 1989, is changing its name to the Electronic System Design Alliance, or ESD Alliance.

The name change is being accompanied by an expansion of the organization’s charter. Having taken on semiconductor intellectual property several years ago, the ESD Alliance will also address advanced packaging and embedded software, according to Robert Smith, who took over last year as executive director of EDAC. The ESD Alliance will also welcome service companies that offer design know-how and resources.

The alliance’s launch was marked by an evening event on Wednesday (March 30) at the SEMI headquarters in San Jose, Calif., where the ESD Alliance has its offices. In attendance at the social gathering were several EDAC directors, including Simon Segars, chief executive officer of ARM Holdings; Wally Rhines, chairman and CEO of Mentor Graphics; Lip-Bu Tan, president and CEO of Cadence Design Systems; and Aart de Geus, chairman and co-CEO of Synopsys.

“We’re part of this large ecosystem,” Bob Smith said Wednesday evening, adding, “Semiconductors – they need design.” He recognized by name many of the people involved in EDAC and now the ESD Alliance.

A slide presentation at the event began with “Kingdom of Rain,” by The The, segueing to “Love Shack” by the B-52’s – two songs dating to 1989, the year EDAC was formed. That also was the year Taylor Swift was born, one slide noted.

In 2016, marked musically by Mark Ronson’s “Uptown Funk” in the slide show, the ESD Alliance is taking the place of the EDA Consortium.

New MEMS Design Contest Encourages Advances in MEMS Technology

Wednesday, March 16th, 2016

Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks. To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge.

The contest seeks companies, entrepreneurs, researchers and students from around the globe. Design teams are encouraged to propose imaginative design concepts that combine MEMS and mixed-signal technologies. The organizers will provide free training workshops to familiarize the participating teams with the design tools, design methodologies and process technologies involved.

A panel of highly experienced industry professionals and respected academics will undertake appraisal of the submissions. Each submission will be judged on the degree of innovation demonstrated in hardware and methodology, the novelty of the application and the value the design provides. Awards for the top three submissions will be presented at Cadence’s annual user conference, CDNLive EMEA 2018, in Munich and the winning team’s solution will be manufactured at X-FAB’s wafer production facilities.

“Supporting innovation and advancement in electronic design is fundamental to what this contest is all about,” said Alexander Duesener, Corporate VP EMEA of Cadence Design Systems. “Creating mixed-signal logic and MEMS designs requires a new process flow and totally new thinking. By enabling the winning design team to turn their concepts into manufactured designs, we highlight the value of MEMS and mixed-signal designs in today’s products.”

“The MEMS Design Contest calls attention to the increasing integration of MEMS and mixed-signal technologies in phones, cars and Internet of Things (IoT) devices,” said Dr. Stephen Breit, Vice President of Engineering at Coventor. “By offering design teams state-of-the-art Cadence and Coventor tools in combination with X-FAB’s latest MEMS and CMOS design kits, we hope to inspire new applications of our combined solution for efficiently designing, integrating and manufacturing MEMS and mixed-signal CMOS technologies.”

“By enabling the winning design team to turn their ideas into manufactured designs, X-FAB is highlighting the value of proven MEMS process technology and design enablement through our design kits,” added Joerg Doblaski, Director Design Support at X-FAB. “We look forward to seeing innovative designs from around the world and helping bring the best of them to life.”

For complete information on the contest and how to enter visit: http://www.cadence.com/MEMS_Design_Contest_2018