By Ed Korczynski, Sr. Technical Editor, SST/SemiMD
On May 14, 2014 it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.
“Building upon the existing solid relationship between ST and Samsung within the framework of the International Semiconductor Development Alliance, this 28nm FD-SOI agreement expands the ecosystem and augments fab capacity for ST and the entire electronics industry,” said Jean-Marc Chery, COO, STMicroelectronics. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”
According to Handel Jones, founder and CEO of International Business Strategies Inc. (IBS), “The 28nm node will be long-lived; we expect it to represent approximately 4.3 million wafers in the 2017 timeframe, and FD-SOI could capture at least 25 percent of this market.”
Table 1 shows IBS data estimating costs for different 28nm fab process technologies.
“We are pleased to announce this 28nm FD-SOI collaboration with ST. This is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Seh-Woong Jeong, executive vice president of System LSI Business, Samsung Electronics. “28nm process technology is a highly productive process technology and expected to have a long life span based on well-established manufacturing capabilities.”
In June 2012, ST announced that GLOBALFOUNDRIES had joined the FD-SOI party for the 28nm and 20nm nodes. However, though the name has since changed from “20nm” to “14nm” (Table 2), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.
“Leti continues its development of further generations and our technology and design results show great promise for the 14nm and 10nm nodes,” said Laurent Malier, CEO of CEA-Leti (Laboratory for Electronics and Information Technology). Leti and ST are not against finFET technology, but sees it as complementary to SOI. In fact the ecosystem plans to add finFETs to the FD-SOI platform for the 10nm node, at which point Taiwanese foundry UMC plans to join.
FD-SOI Substrate Technology
Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, supplies most of the world’s SOI wafers. Paul Boudre, COO of Soitec, commented, “Our FD-SOI wafers represent an incredible technology achievement, resulting from over 10 years of continuous research and high-volume manufacturing expertise. With our two fabs and our licensing strategy, the supply chain is in place and we are very excited by this opportunity to provide the semiconductor industry with our smart substrates in high volume to enable widespread deployment of FD-SOI technology.”
Soitec’s R&D of ultra-thin SOI was partly funded and facilitated by the major French program called “Investments for the Future.” Soitec has collaborated with CEA-Leti on process evolution and characterization, with IBM Microelectronics for device validation and collaboration, and with STMicroelectronics to industrialize and demonstrate the first products.
Boudre, in an exclusive interview with SST/SemiMD, explained, “For 28nm node processing we use a 25+-1nm buried oxide layer, which is reduced in thickness to 20+-1nm when going to the 14nm node and we don’t see any differences in the substrate production. However, for the 10nm node the buried oxide layer needs to be 15nm thin, and we will need some new process steps to be able to embed nMOS strain into substrates.”