Posts Tagged ‘CEA-Leti’
Pete Singer blogs that at The ConFab last week, IBM’s Gary Patton gave us three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.
Tony Chao of Applied Materials writes that Applied Ventures will be participating in the second-annual Silicon Innovation Forum (SIF) held in conjunction with SEMICON West 2014 in San Francisco on Tuesday, July 8. The forum is designed to bring new and emerging innovators together with the semiconductor industry’s top strategic investors and venture capitalists (VCs), in order to enable closer collaboration and showcase the next generation of entrepreneurs in microelectronics.
Adele Hars of ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. Malier said that CEA-Let has been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development.
Phil Garrou blogs that last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core.
By Ed Korczynski, Sr. Technical Editor, SST/SemiMD
On May 14, 2014 it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.
“Building upon the existing solid relationship between ST and Samsung within the framework of the International Semiconductor Development Alliance, this 28nm FD-SOI agreement expands the ecosystem and augments fab capacity for ST and the entire electronics industry,” said Jean-Marc Chery, COO, STMicroelectronics. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”
According to Handel Jones, founder and CEO of International Business Strategies Inc. (IBS), “The 28nm node will be long-lived; we expect it to represent approximately 4.3 million wafers in the 2017 timeframe, and FD-SOI could capture at least 25 percent of this market.”
Table 1 shows IBS data estimating costs for different 28nm fab process technologies.
“We are pleased to announce this 28nm FD-SOI collaboration with ST. This is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Seh-Woong Jeong, executive vice president of System LSI Business, Samsung Electronics. “28nm process technology is a highly productive process technology and expected to have a long life span based on well-established manufacturing capabilities.”
In June 2012, ST announced that GLOBALFOUNDRIES had joined the FD-SOI party for the 28nm and 20nm nodes. However, though the name has since changed from “20nm” to “14nm” (Table 2), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.
“Leti continues its development of further generations and our technology and design results show great promise for the 14nm and 10nm nodes,” said Laurent Malier, CEO of CEA-Leti (Laboratory for Electronics and Information Technology). Leti and ST are not against finFET technology, but sees it as complementary to SOI. In fact the ecosystem plans to add finFETs to the FD-SOI platform for the 10nm node, at which point Taiwanese foundry UMC plans to join.
FD-SOI Substrate Technology
Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, supplies most of the world’s SOI wafers. Paul Boudre, COO of Soitec, commented, “Our FD-SOI wafers represent an incredible technology achievement, resulting from over 10 years of continuous research and high-volume manufacturing expertise. With our two fabs and our licensing strategy, the supply chain is in place and we are very excited by this opportunity to provide the semiconductor industry with our smart substrates in high volume to enable widespread deployment of FD-SOI technology.”
Soitec’s R&D of ultra-thin SOI was partly funded and facilitated by the major French program called “Investments for the Future.” Soitec has collaborated with CEA-Leti on process evolution and characterization, with IBM Microelectronics for device validation and collaboration, and with STMicroelectronics to industrialize and demonstrate the first products.
Boudre, in an exclusive interview with SST/SemiMD, explained, “For 28nm node processing we use a 25+-1nm buried oxide layer, which is reduced in thickness to 20+-1nm when going to the 14nm node and we don’t see any differences in the substrate production. However, for the 10nm node the buried oxide layer needs to be 15nm thin, and we will need some new process steps to be able to embed nMOS strain into substrates.”
The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. Dr. Roawen Chen of Qualcomm says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In a keynote talk at The ConFab, titled “what’s on our mind?” Dr. Chen will deliberate on a number of headwinds and opportunities.
Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti describe how the research group has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.
Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a review of the keynote by AMD’s Bryan Black, titled“Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” Garrou also reviews the newly announced STATSChipPAC FlexLine, which uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.
Karen Savala, president, SEMI Americas, blogs about the sustainable manufacturing imperative, noting that sustainability is increasingly considered a differentiating factor in global competitiveness relative to the technologies and products being provided. In conjunction with SEMICON West and INTERSOLAR North America, SEMI is organizing a four-day Sustainable Manufacturing Forum to share information about the latest technologies, products, and management approaches that promote sustainable manufacturing.
Altera Corporation and Intel Corporation announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s leading-edge programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14nm Tri-Gate process. Altera’s work with Intel will enable the development of multi-die devices that efficiently integrates monolithic 14nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package.
Samsung introduced a new lineup of flip chip LED packages and modules offering enhanced design flexibility and a high degree of reliability. The new offerings, for use in leading-edge LED lighting such as LED bulbs, MR/PAR and downlights, will be available in the market during the second quarter of this year. Samsung’s new flip chip (FC) LED package and flip chip on module (FCOM) solutions feature highly efficient and versatile LED structures, created by flipping over blue LED chips and adhering phosphor film to each of them. Unlike conventional LED packages that dispense phosphor and then place a plastic mold over each chip, Samsung’s FC package technology can produce LED packages down to a chip-scale size without any mold, enabling more compact lighting fixture designs.
eInfochips, a semiconductor and product engineering company, this week launched design services for chips based on 16nm geometry. The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability. eInfochips is one of the few engineering services companies in the world capable of delivering 16nm chip designs which reduce a chip’s power consumption by half, while improving performance by one-third over 28nm technology.
SEMATECH announced this week that Particle Measuring Systems has joined SEMATECH to advance the development of nanoscale particle removal processes and cleaning technologies for next-generation wafers and devices. This collaboration will address many of the profound changes taking place in the semiconductor industry that are impacting fundamental aspects of process and equipment design, including integration of new materials and process technology for sub-20nm node manufacturing, next-generation lithography requirements.
CEA-Leti will demonstrate its new prototype for wireless high data rate Li-Fi (light fidelity) transmission at Light + Building 2014 in Frankfurt, Germany, March 30-April 4. The technology employs the high-frequency modulation capabilities of light-emitting diode (LED) engines used in commercial lighting. It achieves throughputs of up to 10Mb/s at a range of three meters, suitable for HD video streaming or Internet browsing, using light power of less than 1,000 lumens and with direct or even indirect lighting. With this first proof of concept and its expertise in RF communications, Leti forecasts data transmission rates in excess of 100Mb/s with traditional lighting based on LED lamps using this technology approach and without altering the high-performance lighting characteristics.
Toshiba Corporation announced that it has brought a civil suit against Korea’s SK Hynix Inc. at the Tokyo District Court, under Japan’s Unfair Competition Prevention Act. The suit seeks damages for the wrongful acquisition and use of Toshiba’s proprietary technical information related to NAND flash memory, which Toshiba pioneered in 1987 and now jointly develops and produces with SanDisk Corporation of the U.S. SanDisk this week also filed a separate lawsuit against SK Hynix for theft of trade secrets.
This week, imec presented the development of fullerene-free organic photovoltaic (OPV) multilayer stacks achieving a record conversion efficiency of 8.4 percent. The imec team now proposes a simple three-layer stack to improve the spectral responsivity range. This device architecture comprises two fullerene-free acceptors and a donor, arranged as discrete heterojunctions. In addition to the traditional exciton dissociation at the central donor-acceptor interface, the excitons generated in the outer acceptor layer are first relayed by energy transfer to the central acceptor, and subsequently dissociated at the donor interface. This results in a quantum efficiency above 75 percent between 400nm and 720nm. With an open-circuit voltage close to 1V, a remarkable power conversion efficiency of 8.4 percent is achieved. These results confirm that multilayer cascade structures are a promising alternative to conventional donor-fullerene organic solar cells.
STATS ChipPAC, a provider of advanced semiconductor packaging and test services, has designed and implemented an innovative new manufacturing method that is a significant paradigm shift from conventional wafer level manufacturing. This breakthrough approach, known as FlexLine, delivers an unmatched level of flexibility and cost savings for wafer level packaging (WLP).
CEA-Leti announced this week it has fabricated ultra-scaled split-gate memories with gate length of 16nm, and demonstrated their functionality, showing good writing and erasing performances with memory windows over 6V. The devices provide several benefits especially for contactless memory applications, such as enlargement of the memory window and increased functionality. Also because of an optimized fabrication step, the devices allow better control of spacer memory gate shape and length.
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, this week announced that its patented NanoSpray conformal coating technology is now available on its newly introduced EVG150XT resist coating and developing system for high-volume manufacturing (HVM) semiconductor applications. NanoSpray provides conformal coating of structures that have vertical sidewall angles—such as through-silicon vias (TSVs), through-glass vias and through-substrate vias used for 2.5D interposers and 3D-ICs—with thick polymer liners and photoresists.
3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame, CA. Bryan Black, Sr Fellow and 3D program manager at AMD noted that while die stacking has caught on in FPGAs and image sensors “..there is nothing yet in mainstream computing CPUs, GPUs or APUs” but that “HBM (high bandwidth memory) will change this.” Black continued, “Getting 3D going will take a BOLD move and AMD is ready to make that move.” Black announced that AMD is co-developing HBM with SK Hynix which is currently sampling the HBM memory stacks and that AMD “…is ready to work with customers.”
ABI Research verified that Intel has a leading position in the mobile processor technology race; launching the first 22nm mobile application processor. The 22nm quad-core application processor (Intel Z3740D) was found in a Dell tablet that was recently launched for the Christmas season. “2013 saw a number of new processor launches with 32nm and 28nm technology (most from fabless companies) but Intel has used one of its core advantages [process technology] to pass them all,” Jim Mielke, VP of engineering at ABI Research, commented. “The 22nm process node used for the Z3740D is not just the smallest geometry in a mobile device today; it also introduces a new transistor. The core transistor structure used in the 22nm Z3740D is quite different than structures used in previous generations. The core transistor found in the device ABI Research analyzed has a gate that surrounds source/drain diffusion fins on three sides giving it the name tri-gate or 3D transistor.
North America-based manufacturers of semiconductor equipment posted $1.24 billion in orders worldwide in November 2013 (three-month average basis) and a book-to-bill ratio of 1.11, according to the November EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 1.11 means that $111 worth of orders were received for every $100 of product billed for the month. “The continuing rise in equipment bookings clearly points to year-end order activity that is substantially stronger compared to one year ago,” said Denny McGuirk, president and CEO of SEMI. ”This trend supports the current outlook showing a rebound in equipment spending for 2014.”
Soitec and CEA have renewed their partnership for the next five years. This new contract aims to support Soitec’s strategy for the electronics, solar energy and lighting markets. It will focus on engineered substrates and materials offering higher performances and energy savings at a competitive cost. As the new partnership is putting in place a powerful R&D ecosystem, time from research to product will be considerably reduced. Thanks to the strengths of CEA-Leti in electronic materials, multi-domain research and its pre-industrialization infrastructure, competitive R&D sample prototyping will be enabled thru a common platform, reducing time to market and R&D costs for Soitec and its customers.
Micron Technology, Inc. announced its collaboration with Broadcom Corporation to develop the industry’s first solution designed for customers challenged by an intrinsic DDR3 timing parameter called tFAW, or four activate window.
Stacking 2-dimensional materials may lower cost of semiconductor devices; Scientists measure speedy electrons in silicon; Holst Centre and imec develop thin-film hybrid oxide-organic microprocessor
Soitec announces new world record for solar cell efficiency at 46%; High photosensitivity 2-D-few-layered molybdenum diselenide phototransistors; Finding the Achilles’ heel of GaN-based LEDs in harsh radiation environments
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.