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Canon, Toshiba Join eBeam Initiative Group

Wednesday, February 24th, 2016

By Jeff Dorsch, Contributing Editor

The eBeam Initiative announced that Canon and Toshiba are new members of the industry organization, which seeks to promote the use of electron-beam technology in semiconductor manufacturing and design.

Canon Nanotechnologies and Toshiba are closely collaborating on the development of nanoimprint lithography technology. Both companies presented papers on Tuesday morning at the SPIE Advanced Lithography conference in the session devoted to “Nanoimprint Lithography Production Readiness.”

The eBeam Initiative additionally announced that it will expand its education efforts in 2016 to support the development of extreme-ultraviolet lithography, multi-beam mask writing, and nanoimprint lithography, all of which employ e-beam techniques in producing photomasks, or master templates in the case of NIL.

“People believe multi-beam is going to happen,” said Aki Fujimura, chief executive officer of D2S, the managing company sponsor of the e-beam group. He cited the group’s annual survey of industry figures, who last year predicted multi-beam mask-writing tools would be used in high-volume manufacturing for critical-layer photomasks by the end of 2018. This industry acknowledgement of advances in multi-beam mask writing “gives confidence,” Fujimura said at the eBeam Initiative’s annual luncheon at the SPIE Advanced Lithography symposium.

More than 100 luncheon attendees heard presentations by representatives of Dai Nippon Printing, the photomask manufacturer; imec, the research and development organization based in Belgium; and NuFlare Technology, a supplier of e-beam mask writers, mask inspection systems, and epitaxial reactors.

Naoya Hayoshi of DNP reported on the basics of NIL, which he said faces “some challenges, as in mask making.”

Praveen Raghavan of imec spoke about the organization’s development of test chips with 5-nanometer features. One was made with self-aligned quadruple patterning, using a 193i immersion scanner, while the other was fabricated with an EUV scanner.

The EUV technology offers “significant wafer cost benefit and enables 2D BEOL,” Raghavan said.

NuFlare’s Hiroshi Matsumoto spoke about the company’s forthcoming MBM-1000 multi-beam mask-writing system, an alpha version of which is currently in operation at the NuFlare facilities in Yokohama, Japan. NuFlare plans to offer a HVM version of the MBM-1000 by the end of this year, he said, with delivery in the fourth quarter of 2017.

The MBM-1000 is targeted at production of 5nm chips, while its successor, the MBM-2000, will address fabrication of 3nm ICs, according to Matsumoto. The MBM-2000 will be released in 2019, he said.

Blog review February 3, 2014

Monday, February 3rd, 2014

Ira Feldman provides an interesting perspective on last month’s SEMI Industry Strategy Symposium. He notes that numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved.

“Long live the FinFET,” says Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc. In this blog post, he describes how designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements, he writes.

Adele Hars of Advanced Substrate News reports that STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.

Phil Garrou finishes up his review of the IMAPS 2013 meeting, with an analysis of Xilinx/SPIL results from their 2.5D 28nm FPGA program, a review of the Copper TSV work presented by Nanyang/IME, Canon’s FPA-5510iV and FPA-5510iZ TSA steppers designed to support high density processes and the implementation of 2.5 & 3D technology, and a report on the embedded technology being developed by AT&S.