By Mark LaPedus

Japan’s two industrial equipment behemoths — Canon Inc. and Nikon Corp. — are going in opposite directions in fab gear, cameras and other areas, according to a new report.

Canon has not been a factor in the high-end semiconductor lithography market for years, as it exited the 193nm scanner business some time ago. Canon is quietly making a run in the nanoimprint arena. But at the same time, Canon faces a slowdown in the 248nm, i-line and LCD stepper segments, according to David Rubenstein, an analyst with Religare Capital Markets, an investment banking firm.

In contrast, Nikon has moved into the black in its semiconductor equipment business for its most recent fiscal year, which ended March 31, 2012, Rubenstein said in the report. But like Canon, Nikon faces a slowdown in its LCD stepper business, he said. Nikon did not respond to inquiries about the report.

“Canon lost market share in SLR cameras to rival Nikon in 2011, owing to supply constraints following the earthquake,’’ he said. “We estimate that Canon’s share fell to 44 percent from 46 percent in 2011, while Nikon raised its share to 32 percent from 30 percent.”

Nikon’s litho unit moves out of the red

It’s the story of two giants in Japan. Established in 1917, Nikon — known as Nippon Kogaku — started by supplying binoculars, microscopes, telescopes and other products. Today, Nikon is about 20 percent the size of Canon in market capitalization. In contrast to previous years, Nikon’s camera business has become the company’s earnings engine. But unlike Canon, Nikon’s lithography tools still represent a large swing factor in its earnings, according to the analyst.

Nikon’s equipment division, which sells lithography gear for fabs and LCD plants, is projected to be 27 percent of the company’s overall sales and 40 percent of its operating profit in fiscal year 2012, which ended in March 31, according to the report.

Nikon forecasts that it will ship 21 193nm immersion lithography scanners in fiscal year 2012, compared to 22 units in fiscal 2011. It’s the worst kept secret in the industry, but Nikon’s largest lithography customer is Intel Corp. “We estimate that (Nikon’s) IC litho business suffered losses three years in a row (from fiscal year 2009 to 2011), but is in the black this year. However, we project that profits will approximately halve next fiscal year as volumes decline,” Rubenstein said.

“Capex is the key driver for Nikon’s IC steppers. We believe that bookings will decline in 2012, continuing the downturn that began in the summer of 2011. We project that capital spending will fall 12 percent year-over-year in 2012,” he said. “Strategic capex for logic chips in smartphones/tablets and ultrabooks is still firm, but overall the softness in memory appears to be the overriding factor for total equipment spending.”

In total, 193nm immersion shipments are slated to fall to 80-90 units in 2012, from 120 units in 2011, according to the report.

Nikon faces other challenges, namely market share. At one time, the company was the dominant supplier of lithography gear. In 2011, Nikon had a 22 percent share in 193nm immersion tools, meaning that rival ASML Holding NV has a staggering 78 percent share.

“Nikon also faces the threat of extreme ultraviolet (EUV) lithography,” Rubinstein said. Nikon has developed two alpha EUV tools, including one within the company’s headquarters and one at Selete. But unlike rival ASML Holding NV – which has an aggressive EUV roadmap – Nikon shows no signs of developing pre-production or production EUV tools in the near term.

“ASML has taken the lead in EUV, investing over $1 billion in the past several years. Originally the adoption by chipmakers of EUV was projected to be 2013, but this appears to be delayed until 2015 or beyond, which is good news for Nikon. Nikon stands to lose market share in IC litho if EUV is adopted for production,” Rubinstein said.

Both Nikon and Canon face challenges in the LCD stepper market. Overall LCD stepper units were 109 units in 2011, but the market is expected to fall by 40 percent in 2012, the report said. Nikon claims to have 75 percent market share in LCD steppers, with Canon holding the rest.

“LCD panel makers have been in the red since 2010, symbolized by record losses at Panasonic, Sharp, Sony, and others. Thus, capex for large panels for LCD TVs is virtually non-existent. In small panels for mobile applications, capex was robust last year, but has been toned down somewhat in recent months,” he said.

Canon goes nano route

According to the analyst, Canon was established as Precision Optical Instruments in 1933. The company developed a 35mm camera in an apartment room in the Roppongi area of Tokyo in 1934. In 1935, this camera was named the Hansa Canon.Today, Canon is the largest technology company in Japan with a ¥4.7 trillion ($57 billion) market capitalization, according to the analyst.

On the other hand, Canon’s lithography equipment business is much smaller than Nikon’s and has little material impact on its total earnings. “Canon does have a decent market share in lower-priced KrF and i-line IC steppers, but typically struggles to stay out of the red in the division,” he said.

But now, Canon is quietly making a run in the nanoimprint lithography business. The company has an agreement with Molecular Imprints Inc. (MII) under which Canon sells MII’s tools in Japan and other markets. MII has sold a nanoimprint tool to Toshiba.

Others, reportedly including Intel and Samsung, have obtained MII’s tools. But to date, nanoimprint remains a niche in lithography. MII would like chip makers to adopt nanoimprint in the next-generation lithography (NGL) race, but the technology still suffers from throughput, defectivity and infrastructure issues.

The key products for Canon are SLR cameras, laser printers, and copiers. “We believe that camera sales and profits will rebound sharply this year as Canon gains back market share lost last year,” he said.

“A threat to Canon’s profitable SLR camera business is new competition from Nikon, Sony, Samsung, Panasonic, Olympus, etc. in the form of mirrorless and other cheap SLR cameras,” he said. “Mirrorless cameras have already gained 30 percent market share in Japan. This increase in mirrorless SLR camera share has been accompanied by a decrease in average selling prices of SLR cameras.”

SLR cameras use a mechanical mirror and prism to direct light to a viewfinder on the back of the camera. Recently, several rivals including Nikon, Sony, Panasonic, Olympus and Samsung have introduced mirrorless SLR cameras, which employ a mirrorless structure that downsizes the camera body, making it lighter.

Canon’s semiconductor equipment division has launched a back-end lithography tool optimized for TSVs, bump processing, and other forms of next-generation semiconductor packaging.

The FPA-5510iV scanner includes new optics with a dual wavelength capability, and an alignment approach optimized for TSVs. It features a numerical aperture that can be varied between 0.10 and 0.18 for the relatively thick resists used in packaging. It can pattern features sized from 1-50 microns with the high aspect ratios required for TSVs.

Canon said the FPA-5510iV features a large exposure area measuring 52 x 34 mm, compared with the 26 x 33 mm area of front-end exposure tools. The system can overlay two standard, front-end scanner fields in a single exposure for high throughputs, Canon said.

The illumination optics utilizes a 4.5kW high-intensity lamp as the light source. It allows the use of i-line light, or a combination of i-line and h-line light for exposure. The company said the use of dual-wavelengths “can raise exposure intensity to increase stepper throughput for the high-dose rough bump processes.”

Canon said the alignment system for the 10iV “automatically monitors and corrects for baseline and lens magnification changes due to optics and substrate heating,” providing 300nm overlay accuracy.

Canon offers optional units which support bonded wafer handling and the backside alignment required for TSVs. The optional Through-Silicon Alignment (TSA) scope uses infrared light to penetrate silicon to view and measure alignment marks buried in bonded-wafer stacks. The method transmits long-wavelength infrared light to detect alignment marks on a wafer.

The tool aligns directly to front-end alignment marks, which Canon said eliminates the need to form additional marks to support backside processing of the wafer.

The company also offers an optional, non-contact wafer edge shielding (WES) unit that masks a portion of each shot on the edge of the wafer during exposure. Canon said the use of the WES allows negative-tone resist along the wafer perimeter to be stripped away during development.

The FPA-5510iV options support the processing of severely warped wafers that often result from wafer bonding and thinning operations, Canon said.

By David Lammers

Faced with delays to the introduction of imprint lithography for bit patterned media by the hard disk drive industry, Molecular Imprints Inc. (Austin) has begun a reduction in force that will impact about 20 people, multiple sources said. The layoff comes as optimism increases among some sources about imprint’s chances of gaining a foothold in CMOS patterning, particularly for the regular structures of NAND flash where redundancy techniques can be employed.

Molecular Imprints CEO Mark Melliar-Smith said he did not wish to specify the exact number of people being laid off, but he did not dispute the number of 20 employees quoted by several sources. “We are undergoing a small downsizing, but our momentum in the CMOS area is actually increasing. In the disk drive area, it will take two or three years longer than we thought. But in HDD, it is not an if, but a when, situation. We will resize and focus more on the CMOS opportunity,” Melliar-Smith said.

Molecular Imprints (MII) has about 120 employees now, before the layoff goes into effect. For the past several years and throughout the recent economic downturn, it has been hiring: recruiting equipment-savvy engineers, lithography R&D experts, and sales and marketing talent. That track record of growth made the news of this week’s layoff all the more surprising, one source said. The company’s strategy was to begin earning significant revenues from the HDD industry, do an initial public offering (IPO), and then attack the much-larger opportunity of sub-20-nm CMOS patterning.

Melliar-Smith said most of the impacted employees are in non-engineering-related roles, including business functions impacted by the delay in the HDD area. “It involves a relatively modest number of business people, not development people,” he said.

MII had banked on the HDD media companies buying specially-designed imprint lithography tools, optimized to imprint patterns on HDD disks at high throughputs. The HDD industry has continued to develop bit patterned media (BPM), but the capital costs for lithography and etch equipment are relatively high compared with a competing approach, heat assisted magnetic recording, or HAMR. While HAMR requires adding a laser to each drive that would cost several tens of cents, it avoids the up-front capital cost of the BPM approach.

The BPM R&D effort at Hitachi Global Storage Technologies combines two technologies: imprint lithography, and directed self assembly chemistry, to achieve high densities using relatively low-cost capital equipment.

MII has developed three generations of HDD imprint equipment, selling a total of 13 machines. Last year, it shipped one of its NuTera HD7000 high-throughput tools to an HDD customer, raising expectations that dozens more orders would follow this year and next.

Instead, the association of disk drive companies working to boost the density of HDD media announced several weeks ago that it was not ready to commercialize the BPM technology now. When the MII investors heard of that decision, one source said, they insisted that MII cut back on its work force in order weather the delay in investments from the HDD industry.

Melliar-Smith said “we believe that bit patterned media is a very viable technology. Ultimately, both BPM and HAMR will be used together to boost the memory elements to the 1-2 terabits per square inch density.”

A former Bell Labs manager who ran Sematech for several years in the late 1990s, Melliar-Smith said the recent SPIE Advanced Lithography conference included several significant progress reports on CMOS fabrication with imprint techniques. (See the ImPatterning blog on SemiMD for a report on imprint news from SPIE). Toshiba researchers reported that it had achieved a defect density of 0.1 defects per square centimeter, while Sematech’s imprint lithography presentation at SPIE claimed that it had achieved an even lower defect density rate, Melliar-Smith said.

Sources said the Toshiba work was done with an MII imprint module mounted on a Canon stepper platform. Asked about any cooperation with Canon’s lithography operation, Melliar-Smith said MII is working with an equipment partner, but added “I can’t tell you which one. It is not unreasonable to assume that if a major semiconductor IDM is going to use imprint for its leading-edge CMOS process, they are not going to entirely rely on a small lithography company in Texas.”

by Ed Korczynski

Many presentations at SPIE Advanced Lithography this year focused on the need to shift from 2D to essentially 1D layouts in masks as double-patterning is pushed to ever smaller geometries. For the third year in a row Valery Axelrad of Sequoia Design Systems and Michael Smayling of Tela Innovations presented results from collaborations. Canon has been working with both companies for some time now. The update this year was a combined presentation from all three companies entitled, “Optical lithography applied to 20nm CMOS logic and SRAM” [7973-39].

Patterning 20nm node chips with 193nm lithography is difficult even with immersion technology, since the Metal-1 (M1) pitch will be ~64nm, which is well below the 80nm limit for single exposure. Pushing the limits is possible with double-patterning (DP) when each pattern to essentially a 1D layout: Gridded Design Rules (GDR) to make uniform arrays, followed by a “cut” pattern of selectively placed orthogonal line segments. The cut layer thus becomes the most critical in terms of lithographic parameters, with similarities to the hole patterns used in contact layers. For both critical layers, density variations arise due to differences between logic and memory areas.

With Optical Proximity Correction (OPC) now at the limit, source-mask optimization (SMO) improves margins at the resolution limit, but can only make major improvements to small cells or repetitive designs like memory. OPC has been used for full-chip manufacturability improvements at previous technology nodes, but will not converge these days. “Convergence problems always arise when you have near neighbors and correlations between them,” explained Axelrad.

The authors also considered fundamental lithographic manufacturability parameters such as Depth of Focus (DOF), Normalized Illumination Log Slope (NILS), and Mask Error Enhancement Factor (MEEF) before and after SMO. Working with Canon steppers, realistic lens distortions using experimentally obtained Jones-Zernike expansions as well as realistic entrance pupil illumination were obtained as inputs to models.

Co-Optimization of Layout and Lithography

Simultaneous optimization of layout patterns and lithography settings is made possible by the uniformity and repeatability of the lines/cuts patterns. Optimization variables for the cut layer include the cut geometry (width, height, serifs), illumination of the scanner lens entrance pupil, and grouping cuts in similar optical environments to allow for local OPC. The optimization was for the CD error across all cuts, which also reduces variation among cuts by getting all CDs close to the same target value. This reduction of variation substantially simplifies the layout and OPC and produces manufacturable designs including both SRAM and logic.

There are many ways to formalize GDR+cut DP litho, but Tela and partners propose the following 1D rules :

• Highly uniform 1D GDR layouts with sparse identical cuts,
• critical layers are cuts,
• all cuts identical to each other and tripled to ensure yield,
• cuts also on a fixed grid (avoiding difficult neighborhoods),
• interactions between cuts sufficiently small for local iterative OPC to converge using SMO, and
• Use of a M0 layer to reduce the number of cuts and improve uniformity of cut density.

An algorithm was developed to resolve OPC and SMO for critical cut and hole layers:

STEP1: SMO (a.k.a. “co-optimization”) to find optimal cut shape and size, and illumination of the scanner lens entrance pupil (source), using a small representative sample portion of the layout.

STEP2: Local layout correction (pseudo-OPC) using information from Step1 to create the ideal size for the rectangles at each location, some a little smaller and some a little larger. Typically only 3-5 iterations are needed reach <1 nm RMS CD for a 42 nm target CD, which takes 30-60 seconds on a quad-core CPU, for a total simulation time of ~2 hours on a single CPU for ~120 windows.

The test chip is a 100k MOSFET including 50 different standard cells for SRAM and logic, in 50 x 60 microns area, using a 3 x 3 microns SMO sample window. The optimal illumination is a horizontal dipole. Axelrad claimed that after this extensive Source-Mask Optimization (SMO) the critical dimension (CD) error could be <1 nm at best focus conditions for both logic and SRAM cells at the 20nm node.