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Mentor Graphics Extends Offering to Support TSMC 7nm and 16FFC FinFET Process Technologies

Wednesday, September 21st, 2016

Mentor Graphics Corp. (NASDAQ: MENT) today announced further enhancements and optimizations for various products within the Calibre Platform, and Analog FastSPICE (AFS) Platform, as well as the completion of further certifications and reference flows for Taiwan Semiconductor Manufacturing Corporation (TSMC) 16FFC FinFET and 7nm FinFET processes. Moreover, the Calibre offering has been extended on additional established TSMC processes in support of the growing Internet of Things (IoT) design market requirements.

The AFS Platform, including AFS Mega simulation, has been certified for the TSMC 16FFC FinFET and the TSMC 7nm FinFET process technologies through TSMC’s SPICE Simulation Tool Certification Program. The AFS Platform supports TSMC design platforms for mobile, HPC, automotive, and IoT/wearables. Analog, mixed-signal, and RF design teams at leading semiconductor companies worldwide will benefit from using Analog FastSPICE to efficiently verify their chips designed in 16FFC and 7nm FinFET technologies.

Mentor’s Calibre xACT™ extraction offering is now certified for the TSMC 16FFC FinFET and the TSMC 7nm FinFET process technologies. Calibre xACT extraction leverages its built-in deterministic fast field-solver engine to deliver needed accuracy around three-dimensional FinFET devices and local interconnect. Its scalable multiprocessing delivers sufficient punch for large leading-edge digital designs. In addition, both companies continue extraction collaboration in established process nodes, with additional corner variation test cases and tighter criteria to ensure tool readiness for IoT applications.

The Calibre PERC™ reliability platform has also been enhanced to enable TSMC 7nm customers to run point-to-point resistance checks at full chip. This greater capacity allows customers to quickly analyze interconnect robustness at all levels (IP, block, and full chip) while verifying lower resistance paths on critical electrostatic discharge (ESD) circuitry, helping ensure long-term chip reliability. Likewise, Calibre Multi-Patterning functionality has been enhanced for 7nm, including new analysis, graph reduction and visualization capabilities which are essential to customers designing and debugging this completely new multi-patterning technique.

The Calibre YieldEnhancer ECOFill solution, initially developed for 20nm, has now been extended to all TSMC process nodes from 7nm to 65nm. Designers at all process nodes will now be able to minimize fill runtimes, manage fill hierarchy, and minimize shape removal when implementing changes to the initial design.

Mentor’s Nitro-SoC P&R platform has also been enhanced to support advanced 7nm requirements, such as floorplan boundary cell insertion, stacking via routing, M1 routing and cut-metal methodology, tap cell insertion and swapping, and ECO flow methodology. Certification of the flow integration of these N7 features are on-going. For 16FFC, the needed tool features have been validated by TSMC, and Mentor is optimizing its correlation with sign-off analysis.

“Today’s chip design teams are looking at different process nodes to implement their complete solution,” said Joe Sawicki, vice president and general manager of Mentor Graphics Design-to-Silicon Division. “By working with TSMC, Mentor is able to provide mutual customers with a single solution that is not only certified, but also includes the latest tool capabilities, for whichever TSMC process node they choose.”

“TSMC’s long-standing collaboration with Mentor Graphics enables both companies to work together effectively to identify new challenges and develop innovative solutions across all process nodes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The Mentor Analog FastSPICE Platform, AFS Mega, and Calibre xACT tools have successfully met the accuracy and compatibility requirements for 16FFC and 7nm FinFET technologies. That certification, along with the Calibre Platform’s provision of fast, accurate physical verification, and extraction solutions critical to 7nm, ensures mutual customers they have access to EDA tools that are optimized for the newest process technologies.”

Mentor Graphics Offers Tanner Calibre One Verification Suite for the Tanner Analog/Mixed-Signal IC Design Environment

Monday, June 6th, 2016

Mentor Graphics® Corporation announced the Tanner Calibre One IC verification suite as an integral part of the Tanner™ analog/mixed-signal (AMS) physical design environment, creating an easy path to the proven capabilities of Calibre® verification tools for Tanner EDA’s user base. This results in a dramatically-improved IC design and verification solution for Tanner customers by providing tightly-integrated access to Calibre’s physical and circuit verification, exclusively within the Tanner L-Edit™ layout environment.

The Calibre platform is the industry-leader for physical verification and is qualified for sign-off by every major IC foundry and the Tanner Calibre One verification suite uses the same Calibre design kits. Customers that already have stand-alone Calibre licenses, and would like to consider the Tanner design environment, can continue to use the pre-existing Calibre-Tanner interfaces. However, offering an additional, custom integration between Calibre and the Tanner AMS IC design flow provides an invaluable option for Tanner IC designers, giving design teams the access they need to confidently tape out their designs.

“We’ve seen a dramatic increase in the productivity of our layout team thanks to the seamless interaction of L-Edit and the Tanner Calibre One verification suite,” said Stefan Lauxtermann, President of Sensor Creations Inc. “Our customers greatly value that we employ Calibre and that there is a one-to-one correspondence between the final DRC by the foundry and the Tanner design process that we use.”

The Tanner Calibre One verification suite includes the following products:

  • Calibre nmDRC™ (hierarchical design rule checking) ensures the physical layout can be manufactured. This industry-leading tool provides fast cycle times and innovative design rule capabilities.
  • Calibre nmLVS™ (hierarchical layout versus schematic) checks that the physical layout is electrically and topographically the same as the schematic. It improves designer productivity by providing actual device geometry measurement and sophisticated interactive debugging capabilities to ensure accurate verification.
  • Calibre xRC™ (parasitic extraction) verifies that layout-dependent effects do not adversely affect the electrical performance of the design, delivering accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

In addition, the Calibre RVE™ tool brings the solution together, providing a graphical results viewing environment that reduces debug time by visually identifying design issues instantly and cross-selecting the associated issue in Tanner’s layout and schematic capture tool.

The Tanner IC design suite supports analog, mixed-signal, and MEMS design in one complete, highly-integrated, end-to-end flow. Designers capture the schematic, perform analog and mixed-signal simulation, and lay out the physical design within this unified flow. With the addition of the Tanner Calibre One verification suite, each designer using the Tanner IC flow can interactively invoke an individual Calibre tool in order to verify the design.

“Tanner Calibre One gives designers using L-Edit the highest confidence possible that their tape outs will be successful,” says Greg Lebsack, General Manager of Tanner operations at Mentor Graphics. “We are thrilled that key capabilities of the industry-leading Calibre suite are now available to everyone in our global Tanner customer base.”

The Tanner Calibre One design flow will be demonstrated at the 2016 Design Automation Conference (DAC) in the Tanner EDA booth (#1828).

Pattern Matching Tackles IC Verification and Manufacturing Problems

Monday, June 6th, 2016

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Mentor Graphics Corporation announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems. The solution is integrated into the Mentor® Calibre nmPlatform solution, creating a synergy that drives these new applications at IC design companies and foundries, across multiple process nodes.

Calibre Pattern Matching technology supplements multi-operational text-based design rules with an automated visual geometry capture and compare process. This visual approach is both very powerful in its ability to capture complex pattern relationships, and to work within mixed tool flows, making it much easier for Mentor customers to create new applications to solve difficult problems. Because it is integrated into the Calibre nmPlatform toolset, the Calibre Pattern Matching functionality can leverage the industry-leading performance and accuracy of all Calibre tools and flows to create new opportunities for design-rule checking (DRC), reliability checking, DFM, yield enhancement, and failure analysis.

“Our customers count on eSilicon’s design services, IP, and ecosystem management to help them succeed in delivering market-leading ICs,” said Deepak Sabharwal, general manager, IP products & services at eSilicon. “We use Calibre Pattern Matching to create and apply a Calibre-based yield-detractor design kit that helps identify and eliminate design patterns that impact production ramp-up time.”

Since its introduction, use models for Calibre Pattern Matching technology have rapidly expanded, solving problems that were previously too complex or time-consuming to be implemented. New use cases include the following:

  • Physical verification of IC designs with curved structures—for analog, high-power, radio frequency (RF) and microelectromechanical (MEMS) circuitry—is extremely difficult with products designed to work with rectilinear design data. Calibre customers are automating that verification using a combination of Calibre Pattern Matching technology and other Calibre tools for much greater efficiency and accuracy, especially when compared to manual techniques.
  • Calibre Pattern Matching technology can be used to quickly locate and remove design patterns that are known or suspected of  being difficult to manufacture (“yield detractors”). Foundries or design companies create libraries of yield detractor patterns that are specific to a process node or a particular design methodology. Samsung Foundry used this approach in its Closed-Loop DFM solution to help its customers ramp to volume faster, and reduce process-design variability.
  • Some customers use Calibre Pattern Matching technology with Calibre Auto-Waivers™ functionality to define a specific context for waiving a DRC violation. This enhancement allows for automatic filtering of those violations for significant time savings and improved design quality.

“To help our customers create manufacturing-ready designs, we use Calibre Pattern Matching to create and use a yield detractor database to fix most of the litho hotspots in the block level. Then we perform fast signoff DFM litho checking at the chip level using an integrated solution with Calibre Pattern Matching and Calibre LFD” said Min-Hwa Chi, senior vice president, SMIC. “By offering a solution for manufacturability robustness that is built on the Calibre platform, we are seeing ready customer adoption of SMIC’s DFM solution.”

With the Calibre Pattern Matching tool, design companies can now optimize their physical verification checking to their unique design styles. The tool is easy to adopt because it doesn’t rely on expertise in scripting languages. Instead, any engineer can readily define a visual pattern that captures the designer’s expertise in the critical geometries and context for that configuration.

“With the growing adoption of Calibre Pattern Matching technology, Mentor continues to help our customers address increasing design complexity, regardless of the process node they are targeting,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “By incorporating the Calibre Pattern Matching tool, the Calibre platform becomes an even more valuable bridge between design and manufacturing for the ecosystem.”

At the 2016 Design Automation Conference, Mentor has a Calibre Pattern Matching presentation on Tuesday, June 7 at 3PM in the Mentor booth #949. Register for the session using the registration form.

https://www.mentor.com/events/design-automation-conference/schedule

Closed-Loop DFM Solution Accelerates Yield Ramps

Monday, June 6th, 2016

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Mentor Graphics Corp. announced that Samsung Foundry’s closed-Loop design-for-manufacturing (DFM) solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps.

In the Closed-Loop DFM flows, Samsung integrates its DFM kits with its testing and manufacturing expertise to identify integrated circuit design patterns that are most likely to impact manufacturing yield, thereby helping customers improve design quality, yield, and ramp to production.

“We can detect the risks in customer products and prevent them,” said K.K. (Kuang-Kuo) Lin, Director, Foundry Marketing Ecosystem, Samsung Semiconductor. “We have seen yield gain of up to 8.5%. In terms of the post-manufacturing yield analysis, we have seen the benefits of around 2%. These numbers are not guaranteed because each product is different, but from our experience, these are the numbers we have seen.”

The Samsung solution extracts customer yield-averse design patterns, feeds that information forward to optimize manufacturing and testing, and closes the loop with feedback from silicon results for product design and yield improvement. This solution is not only useful to initial customer designs, but it also allows learning from current production designs to be applied to next-generation designs from that same customer across entire product families.

As shown in Figure 1, Samsung’s foundry offerings cover the needs of devices, ranging from the IoT to consumer, mobile computing, high end computing to automotive. The company, which first got into the foundry business in 2005, claims to be the first foundry to have high-k metal gates in production (in 2011), the first foundry to offer FinFET risk production (in 2013) and the first foundry to tape out a 10nm product. “We are also at the forefront of 7nm. We call it 7LPP, which will be based on EUV,” he added.

Figure 1

With the end goal of rapid yield ramp for new production introduction, Samsung turned to Mentor Graphics tools for pre-production DFM, which it calls PRISM (pattern recognition and identity scoring methods), which runs on Mentor’s Calibre platform. For this pre-production phase, “we provide very comprehensive process-aware DFM sign-off kits and optimization flow for the designers so they can double-check and verify, prevent any DFM issues during the design phase,” Lin said.

The other component of closed-loop DFM is in post-manufacturing. Samsung has developed as set of tools called FLARE (Failure analysis And yield Rank Estimation with DFM hotspot database), which runs on Mentor’s Tesset platform.

Figure 2 shows how PRISM and FLARE work together in a closed-loop fashion for pre- and post-production DFM.

Figure 2

“Every design has its idiosyncrasies and its unique signatures because layout designers can be pretty creative,” Lin explained. “We use PRISM to do extensive pattern analysis and then do optimization during the data prep and also use the pattern analysis result to drive in-line inspection.”

Once the wafer is manufactured in the fab, FLARE involves mapping a yield learning database with EDS, (electrical engineering die-sort data). “We’ll combine them to do yield pareto data analysis and also mapping analysis. From those deep learning, we are able to prioritize which part of the fab process we can improve. We can also feedback to the DFM kit which we use in the design phase, which gives the designer feedback on what they can further improve,” Lin said.

At the heard of PRISM is a defect database built from test vehicles and existing products (Figure 3). “We put all the patterns that we know into this defect database,” Lin explained. “We also couple it with some very novel things. We use a layout schematic generator from Mentor to increase the coverage, to enumerate all the possible patterns. And then we also have meta data and simulators to do yield prediction of those known defects from different sources.”

Figure 3

“Once a customer product comes into Samsung foundry, we will check against the known defect database. Then we will do prediction in terms of the process margin and feed-forward this data into the subsequent steps of data prep or retargeting, and in-line inspection so we can prioritize our resources to know what to inspect and what not to in the manufacturing steps,” Lin said (see Figure 4).

Figure 4

“FLARE accelerates the learning in the fab to bring up customer products in our foundry. It helps the customer achieve their time to market. It also saves on fab operation costs, so it’s a win-win situation for everyone,” Lin said.

The Closed-Loop DFM flows are in production use today for customers of Samsung Foundry services. While proven in 14 nm technology, the flows can be used for ICs manufactured with other Samsung process nodes.

At the 2016 Design Automation Conference, Mentor and Samsung are co-hosting a lunch seminar entitled “Accelerate Yield Ramps with Samsung Foundry Closed-Loop DFM and Mentor Tools.” The event is Monday, June 6, from 12:00 to 1:30 PM. Interested customers can register for the event using this registration link.

https://www.mentor.com/products/ic_nanometer_design/events/samsung-dac-lunch-seminar

Mentor’s Pattern Matching Tackles IC Verification and Manufacturing Problems

Sunday, June 5th, 2016

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Mentor Graphics Corporation announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems. The solution is integrated into the Mentor® Calibre nmPlatform solution, creating a synergy that drives these new applications at IC design companies and foundries, across multiple process nodes.

Calibre Pattern Matching technology supplements multi-operational text-based design rules with an automated visual geometry capture and compare process. This visual approach is both very powerful in its ability to capture complex pattern relationships, and to work within mixed tool flows, making it much easier for Mentor customers to create new applications to solve difficult problems. Because it is integrated into the Calibre nmPlatform toolset, the Calibre Pattern Matching functionality can leverage the industry-leading performance and accuracy of all Calibre tools and flows to create new opportunities for design-rule checking (DRC), reliability checking, DFM, yield enhancement, and failure analysis.

“Our customers count on eSilicon’s design services, IP, and ecosystem management to help them succeed in delivering market-leading ICs,” said Deepak Sabharwal, general manager, IP products & services at eSilicon. “We use Calibre Pattern Matching to create and apply a Calibre-based yield-detractor design kit that helps identify and eliminate design patterns that impact production ramp-up time.”

Since its introduction, use models for Calibre Pattern Matching technology have rapidly expanded, solving problems that were previously too complex or time-consuming to be implemented. New use cases include the following:

  • Physical verification of IC designs with curved structures—for analog, high-power, radio frequency (RF) and microelectromechanical (MEMS) circuitry—is extremely difficult with products designed to work with rectilinear design data. Calibre customers are automating that verification using a combination of Calibre Pattern Matching technology and other Calibre tools for much greater efficiency and accuracy, especially when compared to manual techniques.
  • Calibre Pattern Matching technology can be used to quickly locate and remove design patterns that are known or suspected of  being difficult to manufacture (“yield detractors”). Foundries or design companies create libraries of yield detractor patterns that are specific to a process node or a particular design methodology. Samsung Foundry used this approach in its Closed-Loop DFM solution to help its customers ramp to volume faster, and reduce process-design variability.
  • Some customers use Calibre Pattern Matching technology with Calibre Auto-Waivers™ functionality to define a specific context for waiving a DRC violation. This enhancement allows for automatic filtering of those violations for significant time savings and improved design quality.

“To help our customers create manufacturing-ready designs, we use Calibre Pattern Matching to create and use a yield detractor database to fix most of the litho hotspots in the block level. Then we perform fast signoff DFM litho checking at the chip level using an integrated solution with Calibre Pattern Matching and Calibre LFD” said Min-Hwa Chi, senior vice president, SMIC. “By offering a solution for manufacturability robustness that is built on the Calibre platform, we are seeing ready customer adoption of SMIC’s DFM solution.”

With the Calibre Pattern Matching tool, design companies can now optimize their physical verification checking to their unique design styles. The tool is easy to adopt because it doesn’t rely on expertise in scripting languages. Instead, any engineer can readily define a visual pattern that captures the designer’s expertise in the critical geometries and context for that configuration.

“With the growing adoption of Calibre Pattern Matching technology, Mentor continues to help our customers address increasing design complexity, regardless of the process node they are targeting,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “By incorporating the Calibre Pattern Matching tool, the Calibre platform becomes an even more valuable bridge between design and manufacturing for the ecosystem.”

At the 2016 Design Automation Conference, Mentor has a Calibre Pattern Matching presentation on Tuesday, June 7 at 3PM in the Mentor booth #949. Register for the session using the registration form.

https://www.mentor.com/events/design-automation-conference/schedule

Samsung’s Closed-Loop DFM Solution Accelerates Yield Ramps

Sunday, June 5th, 2016

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Mentor Graphics Corp. announced that Samsung Foundry’s closed-Loop design-for-manufacturing (DFM) solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps.

In the Closed-Loop DFM flows, Samsung integrates its DFM kits with its testing and manufacturing expertise to identify integrated circuit design patterns that are most likely to impact manufacturing yield, thereby helping customers improve design quality, yield, and ramp to production.

“We can detect the risks in customer products and prevent them,” said K.K. (Kuang-Kuo) Lin, Director, Foundry Marketing Ecosystem, Samsung Semiconductor. “We have seen yield gain of up to 8.5%. In terms of the post-manufacturing yield analysis, we have seen the benefits of around 2%. These numbers are not guaranteed because each product is different, but from our experience, these are the numbers we have seen.”

The Samsung solution extracts customer yield-averse design patterns, feeds that information forward to optimize manufacturing and testing, and closes the loop with feedback from silicon results for product design and yield improvement. This solution is not only useful to initial customer designs, but it also allows learning from current production designs to be applied to next-generation designs from that same customer across entire product families.

As shown in Figure 1, Samsung’s foundry offerings cover the needs of devices, ranging from the IoT to consumer, mobile computing, high end computing to automotive. The company, which first got into the foundry business in 2005, claims to be the first foundry to have high-k metal gates in production (in 2011), the first foundry to offer FinFET risk production (in 2013) and the first foundry to tape out a 10nm product. “We are also at the forefront of 7nm. We call it 7LPP, which will be based on EUV,” he added.

Figure 1

With the end goal of rapid yield ramp for new production introduction, Samsung turned to Mentor Graphics tools for pre-production DFM, which it calls PRISM (pattern recognition and identity scoring methods), which runs on Mentor’s Calibre platform. For this pre-production phase, “we provide very comprehensive process-aware DFM sign-off kits and optimization flow for the designers so they can double-check and verify, prevent any DFM issues during the design phase,” Lin said.

The other component of closed-loop DFM is in post-manufacturing. Samsung has developed as set of tools called FLARE (Failure analysis And yield Rank Estimation with DFM hotspot database), which runs on Mentor’s Tesset platform.

Figure 2 shows how PRISM and FLARE work together in a closed-loop fashion for pre- and post-production DFM.

Figure 2

“Every design has its idiosyncrasies and its unique signatures because layout designers can be pretty creative,” Lin explained. “We use PRISM to do extensive pattern analysis and then do optimization during the data prep and also use the pattern analysis result to drive in-line inspection.”

Once the wafer is manufactured in the fab, FLARE involves mapping a yield learning database with EDS, (electrical engineering die-sort data). “We’ll combine them to do yield pareto data analysis and also mapping analysis. From those deep learning, we are able to prioritize which part of the fab process we can improve. We can also feedback to the DFM kit which we use in the design phase, which gives the designer feedback on what they can further improve,” Lin said.

At the heard of PRISM is a defect database built from test vehicles and existing products (Figure 3). “We put all the patterns that we know into this defect database,” Lin explained. “We also couple it with some very novel things. We use a layout schematic generator from Mentor to increase the coverage, to enumerate all the possible patterns. And then we also have meta data and simulators to do yield prediction of those known defects from different sources.”

Figure 3

“Once a customer product comes into Samsung foundry, we will check against the known defect database. Then we will do prediction in terms of the process margin and feed-forward this data into the subsequent steps of data prep or retargeting, and in-line inspection so we can prioritize our resources to know what to inspect and what not to in the manufacturing steps,” Lin said (see Figure 4).

Figure 4

“FLARE accelerates the learning in the fab to bring up customer products in our foundry. It helps the customer achieve their time to market. It also saves on fab operation costs, so it’s a win-win situation for everyone,” Lin said.

The Closed-Loop DFM flows are in production use today for customers of Samsung Foundry services. While proven in 14 nm technology, the flows can be used for ICs manufactured with other Samsung process nodes.

At the 2016 Design Automation Conference, Mentor and Samsung are co-hosting a lunch seminar entitled “Accelerate Yield Ramps with Samsung Foundry Closed-Loop DFM and Mentor Tools.” The event is Monday, June 6, from 12:00 to 1:30 PM. Interested customers can register for the event using this registration link.

https://www.mentor.com/products/ic_nanometer_design/events/samsung-dac-lunch-seminar

Mentor Graphics U2U Meeting April 26 in Santa Clara

Monday, April 11th, 2016

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Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.

Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high.  What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.

He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.

After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth?  What types of designs will be staffed and funded? Is it IoT?  Wearables?  Automotive?  Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.

Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.

These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.

A few of the highlights:

  • Oracle’s use of advanced fill techniques for improving manufacturing yield
  • How Xilinx built a custom ESD verification methodology on the Calibre platform
  • Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
  • Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
  • Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
  • Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
  • A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
  • How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
  • Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements

Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.

The day winds up with a closing session and networking reception from 5:00-6:00pm.

Registration is from 8:00-9:00am in the morning.

Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

Thursday, March 17th, 2016

Mentor Graphics Corporation (NASDAQ: MENT) today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification. In addition, the Calibre and Analog FastSPICE platforms are ready for early design starts and IP design on TSMC’s 7nm FinFET process based on the most current Design Rule Manual (DRM) and SPICE model.

To help mutual customers prepare their designs for advanced manufacturing processes, Mentor has made improvements for 10nm physical verification, accelerating the runtime of the Calibre nmDRC™ sign-off tool compared to the tool’s runtime when it was initially certified for required 10nm accuracy last year. New device parameters of the 10nm process are supported in the Calibre nmLVS™ tool for more accurate SPICE models and self-heating simulation. Mentor has also enhanced the parasitic accuracy in the Calibre xACT™ solution, and is actively improving layout parasitic extraction flow to meet 10nm requirements.

The Calibre platform also helps designers improve design reliability and manufacturability. The TSMC reliability offering leverages the Calibre PERC™ reliability verification solution, now with enhanced techniques for 10nm resistance and current density checking. For design for manufacturing (DFM), Mentor added color-aware fill and more sophisticated alignment and spacing rules to the SmartFill feature of the Calibre YieldEnhancer tool. Mentor also optimized the Calibre DesignREV™ chip finishing tool, the Calibre RVE™ results viewer, and the Calibre RealTime interface to give designers easier integration and debugging capabilities for multi-patterning, layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) and reliability verification.

Mentor and TSMC are now collaborating on bringing the Calibre platform’s broad capabilities to the 7nm FinFET process. The Calibre nmDRC and Calibre nmLVS tools are already certified for customers’ early design starts. TSMC and Mentor are expanding use of the SmartFill functionality and Calibre multi-patterning capabilities to support the technology requirements of 7nm.

For fast, accurate circuit simulation, TSMC certified the AFS platform, including the AFS Mega circuit simulator, for 10nm V1.0. The AFS platform is also certified for the latest version of the 7nm DRM and SPICE for early design starts.

The Mentor place-and-route platform—including the Olympus-SoC™ system—has been enhanced to support advanced design rules at 10nm, and Mentor is optimizing its correlation with sign-off extraction and static timing analysis tools. This collaboration has also been extended to 7nm.

“We continue to collaborate with Mentor Graphics to provide design solutions and services that will help our mutual customers become successful with their 7nm designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Working together, we are also enabling the full production release of our 10nm technology design support.”

“To get the world’s most advanced processes into the hands of today’s leading SoC designers requires intense collaboration between the foundry and the EDA supplier,” said Joe Sawicki, vice president and general manager of Mentor Graphics Design-to-Silicon Division. “We’re honored that TSMC continues to leverage the proven quality, performance and breadth of Mentor platforms in its ecosystem strategy for the future.”

Mentor Graphics Adds Support for Integrated Fan-Out (InFO) Packaging Technology at TSMC

Monday, March 14th, 2016

Mentor Graphics Corporation (NASDAQ: MENT) today announced a design, layout, and verification solution to support design applications for TSMC’s Integrated Fan-Out (InFO) wafer-level packaging technology. The solution comprises the Calibre® nmDRC physical verification product, the Calibre RVE™ results viewing platform, and the Xpedition® Package Integrator flow. It enables mutual customers to deploy the unique fan-out layer structures and interconnects in the TSMC InFO technology, targeting cost-sensitive applications such as mobile and consumer products.

The interplay between today’s advanced system-on-chip (SoC) technologies and packaging requirements is driving the need for co-validation between integrated circuit (IC) and package design environments. The Xpedition Package Integrator flow will be Mentor’s platform to support TSMC’s unique TSMC InFO design requirements, including integration with other Mentor solutions—the first being Calibre nmDRC and Calibre RVE.

The Mentor® solution allows IC and package designers to view and cross-probe results from the Calibre nmDRC tool directly inside the Xpedition Package Integrator flow for verification of TSMC InFO interconnect structures. Because this flow is based on proven integration via the Calibre RVE tool, it results in automated sign-off verification and easier correction of any issues highlighted by the Calibre nmDRC product. It also streamlines the addition of future features and capabilities.

IC designers have widely adopted the Calibre nmDRC tool as their sign-off solution for multiple process node generations. Through the integration with Xpedition Package Integrator, they now share a common view with package developers when performing co-verification.

“We are focused on making our solutions easier for customers to adopt by providing a design methodology that leverages proven EDA design tools,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Mentor and TSMC have established this InFO methodology through an integration of the Calibre and Xpedition platforms, and will continue to collaborate on enhancing that solution.”

“Integrating Calibre nmDRC technology with the Xpedition Package Integrator flow is a solid first step in Mentor’s support of TSMC’s InFO technology,” stated Joe Sawicki, vice president and general manager of Mentor Graphics Design to Silicon Division. “We continue to work with TSMC and its ecosystem to expand beyond this initial step by establishing a roadmap for additional capabilities to further accelerate time-to-market for users of TSMC’s InFO offering.”

Meeting the IoT Design Challenge

Monday, November 2nd, 2015

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By Pete Singer, Editor-in-Chief

Mentor Graphics acquired Tanner EDA in March of 2015, in an effort to better address the design, layout and verification of analog/mixed-signal (AMS) and MEMS ICs, key building blocks in Internet of Things (IoT).

Since then, the Tanner team has moved offices and successfully been integrated into Mentor’s corporate structure.

We recently caught up with Jeff Miller, product marketing manager for the Tanner Group at Mentor Graphics. “We’ve kept the team together and we’re continuing to work as a business unit within Mentor Graphics with the same team under the same leadership,” he said. “Greg Lebsack, who was the president of Tanner EDA is now the general manager of the Tanner Group. We have the same basic org chart.” He noted that the same people who were with Tanner for a long time are still there. “We tried to preserve that and we’ve done a good job of that,” Miller said.

With the explosion of IoT devices – some estimate 70 billion devices will be connected to the internet by 2020 – the Tanner acquisition seems particularly prescient in that many if not most IoT devices are analog/mixed signal devices, and many involve the use of MEMS.

“We’ve been involved in various IoT-type designs for a long time,” Miller explained. He defined an IoT device as a sensor and an actuator — that’s the “thing” part – plus some amount of readout or control circuitry, and some digital logic in order to control that and interface to a radio which then communicates to your cell phone or you WiFi network and then on to the internet. “You need to have all those four pieces to make your IoT device,” he said.

The microcontroller or microprocessor component and the radio component have been traditionally been done outside of the Tanner EDA tools, but Miller said they group has been making a big effort in the last couple of years to bring some of that into their design flow in terms of enabling a greater degree of integration. “The cost, size pressures and power pressures are going to force some integration there,” Miller said.

In other words, sensors are being integrated with more and more of intelligence. “Instead of just having a raw MEMS accelerometer, they’ll have a 3-axis accelerometer with a 3-axis gyro and a read-out circuit and enough digital logic to do some processing,” said Miller. “These sensors are becoming a lot smarter and more integrated in order to support these kinds of applications.”

Miller said he’s seen a lot of new entrants into the IoT market. Typically design teams have5 to 20 people. Tanner’s market historically has been the smaller companies with relatively focused products.

“I’m expecting the needs of this market to be diverse enough that we’re going to see a proliferation of small interesting designs that enable a particular class of IoT device,” Miller predicts. “This proliferation across the market will lead to small design teams doing something innovative in a smaller scale environment, trying to make these things as small and efficient as they can possibly be. “

Since the acquisition, a big focus of the Tanner Group has been on how to best integrate Mentor’s tools such as Calibre, ModelSim and AFS with existing Tanner products. “More so than ever before, we have a complete design flow, start to finish, for analog design flow, mixed signal design and for MEMS design, and any integration across those things,” Miller said. “We’re keeping our basic ways of doing things and leveraging the incredible resources that are available being part of a large company like Mentor Graphics. It’s really good for us to part of this new, larger team.”

The first major integration was with Calibre, followed by ModelSim as the digital simulator in their mixed signal flow. “We can integrate our SPICE simulator with ModelSim and do mixed signal simulations and communicate the signals across the boundary between analog and digital,” Miller said. He adds that expects to have more and tighter integrations with other Mentor Graphic tools moving forward.

“I’ve been really encouraged that Mentor has been investing us and making sure we’re going to be around and still doing business in a Tanner kind of way going into the future,” Miller said.

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