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Amkor and Cadence to Develop Packaging Assembly Design Kits for Amkor’s SLIM and SWIFT Packaging Technologies

Thursday, May 5th, 2016

Amkor Technology, Inc., a outsourced semiconductor packaging and test service provider, today announced the expansion of its collaboration with Cadence Design Systems, Inc. to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor’s SLIM and SWIFT advanced fan-out package technologies. As a leader in electronic design automation, Cadence will provide Amkor with PADK development support based on the Cadence Physical Verification System (PVS) software tool. This integrated solution allows Amkor’s customers to shorten the SLIM and SWIFT design and verification cycles.

“We’re at a critical juncture in the semiconductor industry with increased dependence on packaging solutions for delivery of next-generation products,” said Ron Huemoeller, Amkor’s corporate vice president, research and development. “The development of these PADKs, the latest outcome of our lengthy collaboration with Cadence, addresses a critical gap forming between foundry and back-end-of-line, as fan-out packaging solutions blur the lines between these processes. Based on our vast experience with advanced package design methodologies, Amkor is well positioned to lead the industry with our unique fan-out packaging technologies.”

By jointly developing Cadence PVS-based PADKs for SLIM and SWIFT technologies, Amkor and Cadence are filling the gap between semiconductor die design and package design, while refining design methodologies for advanced IC packaging fan-out technologies. Amkor’s PADKs will enable designers to meet the design requirements needed to ensure complete package-level sign-off verification for SLIM and SWIFT technologies and provide more seamless collaboration with their customers.

“To keep up with the industry’s faster-performing, lower-power and smaller form-factor device requirements, fan-out processing is now an essential part of advanced IC packaging,” said Steve Durrill, senior product engineering group director of the PCB Group at Cadence Design Systems. “Our partnership with Amkor fills a void when it comes to complete sign-off verification for this advanced IC packaging technology, helping to accelerate the adoption of SLIM and SWIFT technologies in this fast growing market segment.”

IoT Demands Part 2: Test and Packaging

Friday, April 15th, 2016

By Ed Korczynski, Senior Technical Editor, Solid State Technology, SemiMD

The Internet-of-Things (IoT) adds new sensing and communications to improve the functionality of all manner of things in the world. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT applications will have to be extremely small and low-cost. To understand the state of technology preparedness to meet the anticipated needs of the different application spaces, experts from GLOBALFOUNDRIES, Cadence, Mentor Graphics and Presto Engineering gave detailed answers to questions about IoT chip needs in EDA and fab nodes, as published in “IoT Demands:  EDA and Fab Nodes.” We continue with the conversation below.

Korczynski: For test of IoT devices which may use ultra-low threshold voltage transistors, what changes are needed compared to logic test of a typical “low-power” chip?

Steve Carlson, product management group director, Cadence

Susceptibility to process corners and operating conditions becomes heightened at near-threshold voltage levels. This translates into either more conservative design sign-off criteria, or the need for higher levels of manufacturing screening/tests. Either way, it has an impact on cost, be it hidden by over-design, or overtly through more costly qualification and test processes.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

We need to make sure that the testability has also been designed to be functional structurally in this mode. In addition, sub-threshold voltage operation must account for non-linear transistor characteristics and the strong impact of local process variation, for which the conventional testability arsenal is still very poor. Automotive screening used low voltage operation (VLV) to detect latent defects, but at very low voltage close to the transistor threshold, digital becomes analog, and therefore if the usual concept still works for defect detection, functional test and @speed tests require additional expertise to be both meaningful and efficient from a test coverage perspective.

Korczynski:  Do we have sufficient specifications within “5G” to handle IoT device interoperability for all market segments?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

The estimated timeline for standardization availability of 5G is around 2020. 5G is being designed keeping three classes of applications in mind:  Enhanced Mobile Broadband, Massive IoT, and Mission-Critical Control. Specifically for IoT, the focus is on efficient, low-cost communication with deep coverage. We will start to see early 5G technologies start to appear around 2018, and device connectivity,

interoperability and marshaling the data they generate that can apply to multiple IoT sub-segments and markets is still very much in development.

Korczynski:  Will the 1st-generation of IoT devices likely include wide varieties of solution for different market-segments such as industrial vs. retail vs. consumer, or will most device use similar form-factors and underlying technologies?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

If we use CES 2016 as a showcase, we are seeing IoT “Things” that are becoming use-case or application-centric as they apply to specific sub-segments such as Connected Home, Automotive, Medical, Security, etc. There is definitely more variety on the consumer front vs. industrial. Vendors / OEMs / System houses are differentiating at the user-interface design and form-factor levels while the “under-the-hood” IC capabilities and component technologies that provide the atomic intelligence are fairly common. ​

Steve Carlson, product management group director, Cadence

Right now it seems like everyone is swinging for the fence. Everyone wants the home-run product that will reach a billion devices sold. Generality generally leads to sub-optimality, so a single device usually fails to meet the needs and expectations of many. Devices that are optimized for more specific use cases and elements of purchasing criteria will win out. The question of interface is an interesting one.

Korczynski:  Will there be different product life-cycles for different IoT market-segments, such as 1-3 years for consumer but 5-10 years for industrial?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

That certainly seems to be the case. According to Gartner’s market analysis for IoT, Consumer is expected to grow at a faster pace in terms of units compared to Enterprise, while Enterprise is expected to lead in revenue. Also the churn-cycle in Consumer is higher / faster compared to Enterprise. Today’s wearables or smart-phones are good reference examples. This will however vary by the type of “Thing” and sub-segment. For example, you expect to have your smart refrigerator for a longer time period compared to smart clothing or eyewear. As ASPs of the “Things”come down over time and new classes of products such as disposables hit the market, we can expect even larger volumes.​

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

The market segments continue to be driven by the same use cases. In consumer wearables, short cycles are linked to fashion trends and rapid obsolescence, where consumer home use has longer cycles closer to industrial market requirements. We believe that the lifecycle norms will hold true for IoT devices.

Korczynski:  For the IoT application of infrastructure monitoring (e.g. bridges, pipelines, etc.) long-term (10-20 year) reliability will be essential, while consumer applications may be best served by 3-5 year reliability devices which cost less; how well can we quantify the trade-off between cost and chip reliability?

Steve Carlson, product management group director, Cadence

Conceptually we know very well how to make devices more reliable. We can lower current densities with bigger wires, we can run at cooler temperatures, and so on.  The difficulty is always in finding optimality for a given criterion across the, for practical purposes, infinite tradeoffs to be made.

Korczynski:  Why is the talk of IoT not just another “Dot Com” hype cycle?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

​​I participated in a panel at SEMICON China in Shanghai last month that discussed a similar question. If we think of IoT as a “brand new thing” (no pun intended), then we can think of it as hype. However if we look at the IoT as as set of use-cases that can take advantage of an evolution of Machine-to-Machine (M2M) going towards broader connectivity, huge amounts of data generated and exchanged, and a generational increase in internet and communication network bandwidths (i.e. 5G), then it seems a more down-to-earth technological progression.

Nicolas Williams, product marketing manager, Mentor Graphics

Unlike the Dot Com hype, which was built upon hope and dreams of future solutions that may or may not have been based in reality, IoT is real business. For example, in a 2016 IC Insights report, we see that last year $63.4 billion in revenue was generated for IoT systems and the market is growing at about 20% CAGR. This same report also shows IoT semiconductor sales of over $15 billion in 2015 with a CAGR of 21.1%.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

It is the investment needed up front to create sensing agents and an infrastructure for the hardware foundation of the IoT that will lead to big data and ultimately value creation.

Steve Carlson, product management group director, Cadence

There will be plenty of hype cycles for products and product categories along the way. However, the foundational shift of the connection of things is a diode through which civilization will only pass through in one direction.

IoT Demands Part 1: EDA and Fab Nodes

Thursday, April 14th, 2016

The Internet-of-Things (IoT) is expected to add new sensing and communications to improve the functionality of all manner of things in the world:  bridges sensing and reporting when repairs are needed, parts automatically informing where they are in storage and transport, human health monitoring, etc. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT applications will have to be assembled at low-cost and small-size in High Volume Manufacturing (HVM). Micro-Electro-Mechanical Systems (MEMS) and other sensors are being combined with Radio-Frequency (RF) ICs in miniaturized packages for the first wave of growth in major sub-markets.

To meet the anticipated needs of the different IoT application spaces, SemiMD asked leading companies within critical industry segments about the state of technology preparedness:

*  Commercial IC HVM – GLOBALFOUNDRIES,

*  Electronic Design Automation (EDA) – Cadence and Mentor Graphics,

*  IC and complex system test – Presto Engineering.

Korczynski:  Today, ICs for IoT applications typically use 45nm/65nm-node which are “Node -3″ (N-3) compared to sub-20nm-node chips in HVM. Five years from now, when the bleeding-edge will use 10nm node technology, will IoT chips still use N-3 of 28nm-node (considered a “long-lived node”) or will 45nm-node remain the likely sweet-spot of price:performance?

Timothy Dry, product marketing manager, GLOBALFOUNDRIES

In 5 years time, there will be a spread of technology solutions addressing low, middle, and high ends of IoT applications. At the low end, IoT end nodes for applications like connected smoke

detectors, security sensors will be at 55, 40nm ULP and ULL for lowest system power, and low cost. These applications will be typically served by MCUs <50DMIPs. Integrated radios (BLE, 802.15.4), security, Power Management Unit (PMU), and eFlash or MRAM will be common features. Connected LED lighting is forecasted to be a high volume IoT application. The LED drivers will use BCD extensions of 130nm—40nm—that can also support the radio and protocol-MCU with Flash.

In the mid-range, applications like smart-meters and fitness/medical monitoring will need systems that have more processing power <300DMIPS. These products will be implemented in 40nm, 28nm and GLOBALFOUNDRIES’ new 22nm FDSOI technology that uses software-controlled body-biasing to tune SoC operation for lowest dynamic power. Multiple wireless (BLE/802.15.4, WiFi, LPWAN) and wired connectivity (Ethernet, PLC) protocols with security will be integrated for gateway products.

High-end products like smart-watches, learning thermostats, home security/monitoring cameras, and drones will require MPU-class IC products (~2000DMIPs) and run high-order operating systems (e.g. Linux, Android). These products will be made in leading-edge nodes starting at 22FDX, 14FF and migrating to 7FF and beyond. Design for lowest dynamic power for longest battery life will be the key driver, and these products typically require human machine Interface (HMI) with animated graphics on a high resolution displays. Connectivity will include BLE, WiFi and cellular with strong security.

Steve Carlson, product management group director, Cadence

We have seen recent announcements of IoT targeted devices at 14nm. The value created by Moore’s Law integration should hold, and with that, there will be inherent advantages to those who leverage next generation process nodes. Still, other product categories may reach functionality saturation points where there is simply no more value obtained by adding more capability. We anticipate that there will be more “live” process nodes than ever in history.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

It is fair to say that most IoT devices will be a heterogeneous aggregation of analog functions rather than high power digital processors. Therefore, and by similarity with Bluetooth and RFID devices, 90nm and 65nm will remain the mainstream nodes for many sub-vertical markets, enabling the integration of RF and analog front-end functions with digital gate density. By default, sensors will stay out of the monolithic path for both design and cost reasons. The best answer would be that the IoT ASIC will follow eventually the same scaling as the MCU products, with embedded non-volatile memories, which today is 55-40nm centric and will move to 28nm with industry maturity and volumes.

Korczynski:  If most IoT devices will include some manner of sensor which must be integrated with CMOS logic and memory, then do we need new capabilities in EDA-flows and burn-in/test protocols to ensure meeting time-to-market goals?

Nicolas Williams, product marketing manager, Mentor Graphics

If we define a typical IoT device as a product that contains a MEMS sensor, A/D, digital processing, and a RF-connection to the internet, we can see that the fundamental challenge of IoT design is that teams working on this product need to master the analog, digital, MEMS, and RF domains. Often, these four domains require different experience and knowledge and sometimes design in these domains is accomplished by separate teams. IoT design requires that all four domains are designed and work together, especially if they are going on the same die. Even if the components are targeting separate dice that will be bonded together, they still need to work together during the layout and verification process. Therefore, a unified design flow is required.

Stephen Pateras, product marketing director, Mentor Graphics

Being able to quickly debug and create test patterns for various embedded sensor IP can be addressed with the adoption of the new IEEE 1687 IP plug-and-play standard. If a sensor IP block’s digital interface adheres to the standard, then any vendor-provided data required to initialize or operate the embedded sensor can be easily and quickly mapped to chip pins. Data sequences for multiple sensor IP blocks can also be merged to create optimized sequences that will minimize debug and test times.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

From a testing standpoint, widely used ATEs are generally focused on a few purposes, but don’t necessarily cover all elements in a system. We think that IoT devices are likely to require complex testing flows using multiple ATEs to assure adequate coverage. This is likely to prevail for some time as short run volumes characteristic of IoT demands are unlikely to drive ATE suppliers to invest R&D dollars in creating new purpose-built machines.

Korczynski:  For the EDA of IoT devices, can all sensors be modeled as analog inputs within established flows or do we need new modeling capability at the circuit level?

Steve Carlson, product management group director, Cadence

Typically, the interface to the physical world has been partitioned at the electrical boundary. But as more mechanical and electro-mechanical sensors are more deeply integrated, there has been growing value in co-design, co-analysis, and co-optimization. We should see more multi-domain analysis over time.

Nicolas Williams, product marketing manager, Mentor Graphics

Designers of IoT devices that contain MEMS sensors need quality models in order to simulate their behavior under physical conditions such as motion and temperature. Unlike CMOS IC design, there are few standardized MEMS models for system-level simulation. State of the art MEMS modeling requires automatic generation of behavioral models based on the results of Finite Element Analysis (FEA) using reduced-order modeling (ROM). ROM is a numerical methodology that reduces the analysis results to create Verilog-A models for use in AMS simulations for co-simulation of the MEMS device in the context of the IoT system.

Cadence to Acquire Rocketick

Monday, April 11th, 2016

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced that it has entered into a definitive agreement to acquire Rocketick Technologies Ltd., an Israel based pioneer and leading provider of multicore parallel simulation. Rocketick’s technology accelerates Cadence Incisive® Enterprise Simulator to provide up to 6X speed-up for register-transfer-level (RTL), up to 10X speed-up for gate-level functional and up to 30X speed-up for gate-level DFT simulations using standard x86-based servers. The Rocketick solution is proven and is in use today by numerous marquee systems and semiconductor companies in the mobile, server, and graphics domains. The integration of Rocketick’s technology will serve to strengthen Cadence’s System Design Enablement strategy by delivering ultra-high-performance simulation to accelerate the development of complete systems with the consumer end-product in mind.

“Ensuring that SoC verification is completed on time within ever shrinking project schedules is driving the strong need to speed up the underlying logic simulation technology,” said Dr. Anirudh Devgan, senior vice president and general manager of the System & Verification Group and the Digital & Signoff Group at Cadence. “Rocketick is the leading, established provider of parallel simulation technology. I look forward to welcoming the Rocketick team to Cadence as we accelerate our innovation in functional verification to solve our customers’ most difficult challenges.”

Rocketick’s market-leading technology achieves linear speed-up by parallelizing simulation on standard x86-based multicore servers, providing automated partitioning across designs and testbenches, and the flexibility to direct simulations to server farm resources ranging from one to 64 cores. It also provides a significant accuracy advantage and enhanced visibility with four-state logic simulation, and reduces host memory footprint by 2-3X for gate-level designs. Rocketick’s technology works seamlessly with the Cadence Incisive Enterprise Simulator without the need to modify designs or testbenches, eliminating ramp-up time while providing accurate results at significantly accelerated speeds.

“Rocketick and Cadence serve market-leading customers whose exploding verification challenges are testing the limits of conventional simulators,” said Tomer Ben-David, CEO of Rocketick. “Rocketick’s technology has been proven to deliver as much as 30X faster simulation on very challenging designs at top tier system and semiconductor companies. We are very excited to join the Cadence team and look forward to providing even more benefit to customers through the tight integration of Rocketick’s core engines with Cadence’s overall verification solution.”

The acquisition is expected to close in the second quarter of fiscal 2016, and is not expected to have a material impact on Cadence’s fiscal 2016 results of operations. Terms of the transaction were not disclosed. Rocketick is backed by investments from Intel Capital and other strategic and financial investors. Needham & Company advised Rocketick on the transaction.

Functional Safety, Security for IoT Stressed at Cadence Event

Thursday, April 7th, 2016

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By Jeff Dorsch, Contributing Editor

Lip-Bu Tan, President and CEO, Cadence Design Systems

The “big trends” in the electronics industry are social, mobility, the Internet of Things, and security, Lip-Bu Tan, the president and chief executive officer of Cadence Design Systems, said Tuesday (April 5) in his keynote address at the CDNLive Cadence User Conference in Santa Clara, Calif.

He later touched on 5G wireless communications, Big Data, deep learning, and ultra-low-power devices, leading up to the concept of System Design Enablement, or SDE. “We have been changing the entire system design flow,” Tan told a capacity audience in the Santa Clara Convention Center’s Elizabeth A. Hangs Theatre.

The Cadence CEO described new products that have been introduced in the past year.

(The system design theme is also exemplified by the Electronic Design Automation Consortium renaming itself last month as the Electronic System Design Alliance.)

Tan was followed by Qualcomm CEO Steve Mollenkopf, who took “The Evolution of Connected Devices” as his theme.

“There’s tremendous innovation in front of us…providing technology at scale,” Mollenkopf said. Mobility and low-power technology are “disrupting multiple industries,” he added.

While growth in the smartphone market is slowing down, wider adoption of Long-Term Evolution communications and the introduction of augmented reality and virtual reality on handsets promise to buoy the smartphone business for years to come, according to Mollenkopf.

The description of automotive vehicles as “a phone on wheels” is not unjustified, the Qualcomm CEO observed. While the unit volume of the auto business is lower than smartphones and many electronics products, the process of adding connectivity and Internet service to cars is “just beginning,” he said.

While the IoT is “not the next savior for the [semiconductor] industry,” Mollenkopf said, the industrial IoT promises to generate valuable data for manufacturers. “We’re moving from discrete to integrated platforms,” he added.

Qualcomm CEO Steve Mollenkopf

Mollenkopf also addressed drone aircraft, 5G, and autonomous vehicles in his keynote.

Congratulating Cadence on its collaborations with Qualcomm, Mollenkopf concluded, “We need people to make it easy for us to use silicon.”

GlobalFoundries CEO Sanjay Jha was up next. He identified mobile computing, the IoT, and mission-critical/automotive applications as important considerations for the near future.

The IoT market could generate a low estimate of $3.9 trillion in the next decade, with high estimates topping out at $11.5 trillion, Jha said, citing IHS Technology, iSuppli, and other sources. The semiconductor industry could realize $50 billion to $75 billion in value from IoT-related products, “from chips to mini-systems,” he added.

GlobalFoundries, which last year acquired IBM Microlectronics, has identified several key technologies for its operations and foundry services: fully-depleted silicon-on-insulator, magnetic random-access memory, radio-frequency SOI and silicon germanium, system-in-package and other advanced packaging, FinFETs, and application-specific integrated circuits.

“Power consumption is the big differentiator,” Jha commented.

GlobalFoundries CEO Sanjay Jha

The 5-nanometer process node “will be a very expensive technology,” he said. Jha compared an extreme-ultraviolet lithography scanner (EUV technology is now expected to be production-ready for 5nm chips) to “a small Hadron Collider.”

The CDNLive Silicon Valley event was the first of 2016 for the EDA company. Similar conferences are scheduled this year for Germany, Korea, Japan, India, China, Taiwan, the eastern US (Boston), and Israel.

Cadence and University of Oxford Foster the Advancement of Formal Verification Innovation

Thursday, April 7th, 2016

Cadence Design Systems, Inc. (NASDAQ:  CDNS) and the University of Oxford today announced a move to foster the advancement of formal verification innovation with the appointment of Dr. Ziyad Hanna, Cadence vice president of R&D, as a visiting professor in Oxford’s Department of Computer Science for the next three years. Through Dr. Hanna’s appointment at Oxford, a globally distinguished university, Cadence further expands its Cadence® Academic Network footprint.

Dr. Ziyad Hanna, vice president of R&D at Cadence

Dr. Hanna brings more than 25 years of industry experience to Oxford. He currently leads the R&D team for the Cadence JasperGold® formal verification platform, having joined from Jasper Design Automation, which was acquired by Cadence in 2014. Before joining Jasper, Dr. Hanna was also a senior principal engineer and a group leader at Intel, working on formal property verification and equivalence checking. A senior IEEE member, he has mentored dozens of research projects, delivered many visionary talks for the industry and academia, and served in more than 50 program committees to advance academic research. Dr. Hanna has co-authored over 30 articles and holds 15 U.S. patents, and he earned both his B.Sc. and M.S. degrees in mathematics and computer science at Tel Aviv University and his D.Phil. from the University of Oxford.

Oxford’s Automated Verification Group, based in the Department of Computer Science, is one of the largest and strongest academic research groups in the field worldwide, and Cadence has one of the largest corporate investments in formal verification and formal equivalence research and development. Through this appointment, Dr. Hanna is using his real-world experience to enhance Oxford’s automated formal verification research program, while also gaining exposure to the university’s practical and industrially oriented research, which is what the Cadence Academic Network works to foster.

“The University of Oxford appoints visiting professorships to highly distinguished individuals who are regarded as world leaders in their field and can further enhance our research excellence,” said Thomas Melham, Professor of Computer Science at the University of Oxford. “The appointment of Dr. Hanna to Oxford highlights the commitment of Cadence to further the research and development of innovative technology, including formal verification. His visiting professorship provides Cadence with early insight into new academic research directions for addressing the hardest verification challenges that many chip design and system companies encounter.”

“Oxford’s work in verification spans a wide range of research, from fundamental investigations into model checking to practical, machine-assisted methods applicable to real-world design and verification problems in software and hardware systems,” said Dr. Hanna. “It’s an honor to be working with Oxford’s renowned Department of Computer Science. This appointment enables me to collaborate closely with Oxford’s leading verification researchers to tap into the university’s research, which can drive formal verification innovation and bring talented Oxford graduates to Cadence.”

Cadence Adds New Tools for Analog Design, Enhances Layout

Wednesday, April 6th, 2016

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By Jeff Dorsch, Contributing Editor

Cadence Design Systems today is introducing new tools within its Virtuoso Analog Design Environment (ADE), along with enhancements to the Virtuoso Layout Suite.

New to Virtuoso ADE are the Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier.

“The new Virtuoso ADE Verifier technology and the Virtuoso ADE Assembler technology run plan capability make our design teams more productive,” said Yanqiu Diao, deputy general manager of the Turing Processor business unit at HiSilicon Technologies Co., Ltd. “Through our early use of the new Cadence Virtuoso ADE product suite, we’ve found that we can improve analog IP verification productivity by approximately 30 percent and reduce verification issues by one-half. Our smartphone and network chip projects should benefit from these latest capabilities.”

Steve Lewis, product marketing director for Cadence’s Custom IC & PCB Group, said the electronic design automation company’s Virtuoso ADE L, XL, and GXL tools “will be kept, will be maintained, and taking that technology to the next level.”

Virtuoso ADE Verifier is “the brand-new kid on the block,” Lewis said in an interview. The tool advances analog verification technology, according to Cadence, and offers an integrated dashboard for engineers to employ.

Under international standards for automotive vehicles, medical equipment, military/aerospace systems, and other products, suppliers “have to trace every aspect of your design,” he noted. “All has to be documented.”

The digital side of chip design addressed those issues about a decade ago, according to Lewis. Such recordkeeping and documentation are “far less common on the analog,” he said. “It’s no longer okay to say the analog takes care of itself.”

Changes in analog design projects were typically tracked in spreadsheet programs, which don’t connect to the Virtuoso suite, Lewis noted, adding, “Now, I know who’s working on what.”

The new analog design tools “add a little bit more granularity” with real-number models, Lewis said. “It’s not quite SPICE,” he admitted.

Regarding Virtuoso ADE Assembler, “we made it look like ADE XL,” Lewis said, so users should have a shorter learning curve with the new tool. Virtuoso ADE Explorer provides what Cadence calls a complete corners and Monte Carlo environment for finding and correcting variation problems.

Cadence is also offering a Virtuoso Variation Option, providing fast Monte Carlo analysis for FinFET chips with 16-nanometer or smaller dimensions.

The enhancements in Virtuoso Layout Suite are a 10x to 100x improvement in graphics rendering performance, real-time customization of Module Generators with a simpler and more visual approach; and new structured device-level routing capabilities that are said to enhance routing productivity by up to 50 percent.

“We actually made significant changes in layout for L, XL,” addressing “current techniques, current designs,” Lewis commented.

Cadence Virtuoso Analog Design Environment (ADE): Reimagining analog design with emphasis on usability, performance, and innovation

New MEMS Design Contest Encourages Advances in MEMS Technology

Wednesday, March 16th, 2016

Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks. To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge.

The contest seeks companies, entrepreneurs, researchers and students from around the globe. Design teams are encouraged to propose imaginative design concepts that combine MEMS and mixed-signal technologies. The organizers will provide free training workshops to familiarize the participating teams with the design tools, design methodologies and process technologies involved.

A panel of highly experienced industry professionals and respected academics will undertake appraisal of the submissions. Each submission will be judged on the degree of innovation demonstrated in hardware and methodology, the novelty of the application and the value the design provides. Awards for the top three submissions will be presented at Cadence’s annual user conference, CDNLive EMEA 2018, in Munich and the winning team’s solution will be manufactured at X-FAB’s wafer production facilities.

“Supporting innovation and advancement in electronic design is fundamental to what this contest is all about,” said Alexander Duesener, Corporate VP EMEA of Cadence Design Systems. “Creating mixed-signal logic and MEMS designs requires a new process flow and totally new thinking. By enabling the winning design team to turn their concepts into manufactured designs, we highlight the value of MEMS and mixed-signal designs in today’s products.”

“The MEMS Design Contest calls attention to the increasing integration of MEMS and mixed-signal technologies in phones, cars and Internet of Things (IoT) devices,” said Dr. Stephen Breit, Vice President of Engineering at Coventor. “By offering design teams state-of-the-art Cadence and Coventor tools in combination with X-FAB’s latest MEMS and CMOS design kits, we hope to inspire new applications of our combined solution for efficiently designing, integrating and manufacturing MEMS and mixed-signal CMOS technologies.”

“By enabling the winning design team to turn their ideas into manufactured designs, X-FAB is highlighting the value of proven MEMS process technology and design enablement through our design kits,” added Joerg Doblaski, Director Design Support at X-FAB. “We look forward to seeing innovative designs from around the world and helping bring the best of them to life.”

For complete information on the contest and how to enter visit: http://www.cadence.com/MEMS_Design_Contest_2018

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016

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By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

Cadence Debuts Product for Reducing Test Time, Costs

Tuesday, February 2nd, 2016

By Jeff Dorsch, Contributing Editor

Cadence Design Systems is introducing the Modus Test Solution, a product that it touts as capable of reducing IC testing time and test costs, while improving profit margins for chips.

Modus shares a Tcl scripting and debugging environment with Cadence’s Genus Synthesis Solution, Innovus Implementation Solution, and Tempus Timing Signoff Solution, according to the company.

Its other capabilities include 2D compression, elastic compression, and embedded memory bus support. Modus incorporates automatic test pattern generation, built-in self-test, and design-for-test technologies.

“We’re pretty excited about it,” Paul Cunningham, vice president of research and development at Cadence, says of Modus. The automatic test equipment market is worth about $4 billion a year, yet test technology hasn’t yielded any significant breakthroughs in the 21st century, he asserts.

“Test has been stagnant for the last 15 to 20 years,” he says.

Cadence is trying to work around the challenges of test time and test costs by addressing “actual physical test” and “test logic itself,” Cunningham notes. Just as chip designers are constantly aware of power/performance/area in their projects, Cadence addressed test coverage and chip size in developing Modus, he adds.

ATPG, BIST, and DFT technologies have been around for a long time, and they are regaining substantial interest in the semiconductor industry as system-on-a-chip device designs grow more complex.

“Chip CAGRs are not what they used to be,” Cunningham observes. “Cost and profit are very, very critical. Power/performance/area are really, really critical.”

Chipmakers are constantly looking to “squeeze profit margins out,” and reducing test costs can contribute to that imperative, the Cadence executive says. “There is “real pressure on margins, real pressure on complexity,” he adds.

Cunningham also focuses on the “concept of a single user interface” for Modus and its related design tools. With a common UI, different steps in the chip design, manufacturing, and testing processes can be like “different apps on an iPhone,” he says.

Cadence collected testimonials for Modus from three chip companies.

“Minimizing the cost of test is crucial in high-volume, price-sensitive markets like embedded processing. The Modus Test Solution is showing a 1.7x reduction in digital test time on one of our largest and most complex embedded processor chips without any impact on design closure,” said Roger Peters of Texas Instruments, who is involved in microcontroller silicon development.

Sue Bentlage, director of ASIC design and methodology at GlobalFoundries, said, “The Modus Test Solution demonstrated a 3.6x reduction in test time on a customer networking chip without impacting design routability or fault coverage. This technology definitely reduces production test costs. The evolution of the Modus Test Solution, as well as the Innovus Implementation System, the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution, provides a leading edge end-to-end design flow in 14nm and beyond for our worldwide design centers and for our ASIC customers.”

Chris Malkin, baseband IC manager at Sequans Communications, said of Modus, “Test time has a significant impact on semiconductor product costs and production capacity, so reducing test time is important. We have seen the Modus Test Solution achieve a 2x reduction in test time without impacting fault coverage or die size.”

“With the Modus Test Solution, we achieved an impressive 2.6X reduction in compression wirelength and a 2X reduction in scan time. The reduction in compression logic wirelength enabled us to address a key challenge for design closure as we push to smaller process nodes and scale design size,” said Alan Nakamoto, vice president, engineering services at Microsemi Corp.

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