By Mark LaPedus
Pacific Crest Securities has lowered its estimates on several chipmakers, following lower than expected sales for Samsung’s Galaxy S4 smartphone. The perception is that sales of Apple’s iPhone are slowing. One of the few bright spots in the smartphone market involves the Chinese OEMs, which are seeing strong growth in China. “Checks suggest that Coolpad, Huawei, ZTE, and Lenovo are all exhibiting strong sell-through trends,” said Doug Freedman, an analyst with RBC.

Has the game console industry lost its luster? In a research note after attending the Electronic Entertainment Expo (E3), Evan Wilson, an analyst with Pacific Crest Securities, said: “Unfortunately, we came away without the ‘wow’ factor that many expected from next-generation consoles. We now think this cycle may be the first down cycle for hardware. We believe this is due to: (1) the continued lack of excitement for the Wii U, (2) the lack of compelling non-game functions from Sony and Microsoft, (3) Xbox One pricing and used restrictions, (4) what seems like a light launch slate for both systems so far and (5) competition from other devices.”

It’s déjà vu all over again, as Advanced Micro Devices has entered into what could be the start of a new GHz microprocessor speed race. AMD unveiled the most powerful member of its FX family of CPUs, the world’s first 5GHz CPU processor, the AMD FX-9590. The 8-core CPU is made using GlobalFoundries’ 32nm process and Soitec’s silicon-on-insulator (SOI) substrates.

Altatech, a subsidiary of Soitec, has installed and qualified an AltaCVD system at the Fraunhofer Research Institution. It will be used to deposit poly-silicon films for CMOS and MEMS applications.

Khaled Juffali Co. (KJC), a Saudi Arabian investment company, and Soitec have announced that the Saudi Arabian Oil Co. (Saudi Aramco) has decided to use Soitec’s concentrating photovoltaic (CPV) technology for a 1-megawatt solar-energy pilot plant in Saudi Arabia’s northwestern Tabuk region.

Maxwell Technologies and Soitec announced that they will collaborate on a California Energy Commission-funded, two-phase program to demonstrate the cost and efficiency benefits of combining an energy storage system with Soitec’s Concentrix CPV technology.

Soitec has installed a concentrator photovoltaic demonstration plant in the isolated rural village of Usib near Rehoboth in central Namibia.

SEMI reported that worldwide semiconductor manufacturing equipment billings reached $7.31 billion in the first quarter of 2013. The billings figure is 8% higher than the fourth quarter of 2012 and 32% lower than the same quarter a year ago.

Cadence has completed the acquisition of the IP business of Evatronix.

SilabTech has succeeded using the Mentor Graphics’ Pyxis, Eldo, and Calibre tools for custom layout, extraction, simulation, physical verification, and DFM analysis.

UMC will join the IBM Technology Development Alliances as a participant in the group’s development of 10nm CMOS process technology. The agreements between UMC and IBM expand upon their 2012 agreements concerning prior nodes, including 14nm FinFET.

Texas Instruments outlined its long-term strategy for manufacturing facilities in Chengdu, China. Future plans include a new assembly/test operation and the expansion of its existing wafer fabrication factory. TI’s investments in these operations could total up to $1.69 billion over the next 15 years.

Air Liquide has signed an agreement to acquire Voltaix. Founded in 1986, Voltaix is a manufacturer of materials used in the production of semiconductors and advanced solar cells.

Sematech announced that William Rozich has assumed the role of chairman. Rozich, who previously was a member of the company’s board, succeeds Michael Polcari, who served as chairman since 2009.

With both companies just shy of the $800 million mark, Bosch and STMicroelectronics each had MEMS revenue of approximately $793 million in 2012, according to IHS.

Surging smartphone shipments coupled with sluggish notebook computer sales are forecast to propel the total communications IC market past the total computer IC market for the first time in history this year, according to IC Insights.

By Mark LaPedus
The European Commission this week announced a collection of five major projects to boost Europe’s manufacturing competitiveness in electronics. The “pilot lines” include a previously announced, fully depleted silicon-on-insulator (FDSOI) project. Other projects involve 450mm, GaN, MEMS and power electronics. In fact, Soitec will lead one consortium, dubbed the French AGATE pilot line. The aim of this proposal is to show that gallium-nitride (GaN) technology can be manufactured in a standard process line, with adapted equipment at a cost-competitive level on 150mm wafers, while keeping open the route to 200mm substrates. GaN is an emerging technology for LEDs, RF and other applications.

Minera El Tesoro (MET), part of one of the largest mining groups in Chile, has built the first pilot plant in South America with Soitec’s Solar technology, installing four of its concentrator photovoltaic (CPV) systems.

At the Cowen & Co. technology event, Bob Halliday, CFO of Applied Materials, addressed the state of the semiconductor and equipment industries. He also outlined Applied’s prospects for the year.

The World Semiconductor Council wants to expand the scope of the Information Technology Agreement (ITA), a key trade pact that provides for duty-free treatment of certain information technology products, including semiconductors. The list of covered products has not been updated since ITA’s inception in 1996. The WSC cited two such semiconductor products that should be covered by an expanded ITA—multi-component integrated circuits and multi-chip packages (MCP). Inclusion of these devices in an expanded ITA would result in estimated global tariff savings of between $94 million and $188 million annually. In a statement, Ajit Manocha, SIA chairman and CEO of GlobalFoundries, said: “The consensus reached in the 2013 WSC Joint statement represents a significant step toward enacting sound policies that will open markets, increase consumers’ ability to benefit from semiconductor technology advances, maintain market-based competition, and protect the environment.”

At the 50th Design Automation Conference (DAC) in Austin, Texas, GlobalFoundries will unveil a comprehensive set of certified design flows to support its advanced processes. It will also unveil a set of certified design flows to support 2.5D IC product development.

Mentor Graphics has collaborated with GlobalFoundries to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform.  In addition, Mentor Graphics announced that its Calibre physical verification platform has achieved version 0.1 of design reference manual (DRM) and SPICE model tool certification for TSMC’s finFET process. And, Mentor Graphics announced the application of its Capital software suite to the development of CaetanoBus’ flagship C5 coach.

Andras Poppe of Mentor Graphics and the Budapest University of Technology has been recognized by the JEDEC international standards organization for his contributions to the JESD51-5x series of thermal testing standards for LEDs.

Cadence announced that several of its system-on-chip development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s 16nm finFET process.  In addition, PMC has adopted Cadence’s physical verification system as signoff technology for its global design centers.

The Silicon Integration Initiative (Si2) has acquired the Compact Model Council (CMC). The CMC develops and standardizes compact models of electronic devices used within commercial circuit simulators across the electronics industry, including virtually all SPICE-class simulation.

PMC-Sierra has entered into a definitive agreement to acquire Integrated Device Technology’s enterprise flash controller business and certain PCI Express (PCIe) switch assets for $100 million.

Using IC Insights’ current worldwide GDP forecast of 3.0%, the most likely range for IC market growth in 2013 is still 3-7%.

In February, Semiconductor Intelligence forecasted 7.5% growth in the semiconductor market in 2013 and 12% growth in 2014. Although 1Q 2013 was weaker than expected, the general trends driving moderate growth are still in place. Still, the research firm has lowered its IC forecast for 2013 to 6%. It is still holding the 2014 forecast at 12% based on continued improvement in the global economy.

By Mark LaPedus
Change is in store for Taiwan’s United Microelectronics Corp. (UMC), which is struggling to keep up with its leading-edge foundry rivals. UMC is behind in 28nm technology, and plans to skip the 20nm node, thereby jumping from 28nm to finFETs. This week, UMC took more steps to revamp its strategy. UMC has turned its 300mm fab in Singapore from a leading-edge logic plant into a specialty process production and R&D facility. Technologies being developed in this fab include CMOS image sensor backside illumination, embedded memory, high-voltage applications and TSV connections.

Intel’s new CEO Brian Krzanich has implemented a sweeping reorganization at the chipmaker, according to Reuters.

ST-Ericsson, the failed cell-phone chip venture between STMicroelectronics and Ericsson, has sold its GPS mobile business to Intel, according to Reuters. “Intel has purchased ST Ericsson’s mobile GPS, called GNSS (or Global Navigation Satellite System) business unit which includes assets and IP associated with the business,” said Doug Freedman, an analyst with RBC Capital Markets. “We believe the acquisition is prudent as Intel is expected to grow its competitive presence in the mobile area, particularly in 2014 when mobile manufacturing is moved to leading-edge 14nm. Note that Intel does offer high-performance LNAs (low-noise amplifiers) using GiSe:C for GPS signals in mobile communications.”

A group of 19 European companies and academic institutions have launched a three-year, 360 million Euro ($464.5 million) pilot-line project to support the industrialization of fully depleted silicon-on-insulator (FD-SOI) technology. STMicroelectronics and GlobalFoundries will provide the manufacturing capabilities for the program.

Separately, GlobalFoundries also is joining Imec’s advanced MRAM project.

STMicroelectronics said its FD-SOI guru, Jean-Marc Chery, has been appointed general manager of the Embedded Processing Solutions Segment and vice-chairman of the corporate strategic committee. Chery will now be responsible for the digital convergence, imaging, BiCMOS ASIC and silicon photonics, and microcontroller, memory and secure MCU product groups, as well as for the related technology R&D and front-end manufacturing. He was formerly general manager of ST’s Digital Sector and of technology R&D and manufacturing.

Soitec announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. The system has 43.6% efficiency.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.08 in April, down from 1.11 in March, according to SEMI.

Mentor Graphics reported its financial results for the company’s fiscal first quarter ended April 30. “Sales force execution and strong customer demand produced an all-time bookings record for a first quarter,” said Walden Rhines, chairman and CEO of Mentor Graphics.

Mentor Graphics has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process.

In a move to ease and speed the development of complex ICs, Cadence introduced the Tempus Timing Signoff Solution, which significantly speeds up signoff using up to hundreds of processors in parallel.

Look for changes at Tessera Technologies. The chip-packaging IP firm has entered into a settlement agreement with activist firm Starboard Value regarding the composition of the company’s board. The board will consist of 10 directors, including six of Starboard’s nominees and four of Tessera’s nominees.

Now, Starboard Value is looking to gain control of DSP Group. The firm owns approximately 10.1% of DSP Group’s outstanding common stock.

Advanced Semiconductor Engineering (ASE) has acquired shares of Wuxi Tongzhi Microelectronics from Toshiba. The move will strengthen ASE’s ability to provide IC assembly and testing services in China.

Worldwide semiconductor revenues decreased by 2.2% to $295 billion in 2012, according to IDC. The firm expects the semiconductor market to return to growth in 2013 with revenues forecast to increase by 3.5% this year.

A slowdown in notebook and desktop PC purchases coupled with strong growth in smartphones and tablet PCs knocked Advanced Micro Devices down to fourth place in microprocessor sales in 2012 from second, according to IC Insights. Moving ahead of AMD in the 2012 microprocessor rankings were Qualcomm and Samsung.

The solar photovoltaic (PV) market is poised to rise from the ashes of its 2011 crisis to grow to $155 billion in 2018, says Lux Research. In the most likely scenario, the PV market will grow at a modest clip to 35 GW in 2013 before rapidly ramping up to 61.7 GW in 2018.

By Mark LaPedus

Taking another shot to displace ARM, Intel recently rolled out its new microarchitecture for its Atom processor line. In a research note, Will Strauss, president of Forward Concepts, said: “How many times have we heard Intel say that its next member of the Atom processor line would finally be competitive with low-power ARM implementations? Every other year, Intel carts out a new variant that will ‘finally’ do the trick.  The next (and fourth?) iteration of the family, code named Merrifield is said to be the ‘turning point’ for the company in mobile phones.  Although the 2012 launch of Medfield-based 3G phones came close, it didn’t put a dent in ARM’s market share. Merrifield will ship in 4Q13 and phones based on the SoC will be announced at MWC in February 2014. But, the application processor is only part of the solution for a successful smartphone chip offering.  Multimode LTE modems and LTE RF transceivers are also necessary.  Yes, the Infineon-heritage RF transceivers have been fielded in Motorola LTE smartphones, but we’re still waiting for Intel’s multimode LTE modem.  It’s our understanding that the Infineon-heritage multimode 2G/3G/HSPA+ (based on CEVA’s DSP cores) will be married to the Blue Wonder-heritage single-mode LTE (based on Tensilica’s DSP cores). Since the software between the two is not compatible, we expect that has led to integration problems and subsequent delays.”

Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast. In 2012, the IC market fell 2.2%, according to the research firm. Mike Splinter, chairman and CEO of Applied Materials, presents his forecast.

In its most recent quarter, Applied Materials generated orders of $2.27 billion, up 7%t from the prior period, with Silicon Systems Group orders up 14% from the first quarter and Display orders up 41% sequentially. Net sales were $1.97 billion, up 25% sequentially.

At SEMI’s recent Silicon Valley Lunch Forum, speakers from Applied Materials, ASML, and Intel discussed the critical challenges of 450mm and EUV.

The infrastructure in Saratoga, N.Y. can’t keep pace with the growth. One local government organization, the Saratoga County Industrial Development Agency, voted to consider issuing GlobalFoundries nearly $70 million in bonds to finance the infrastructure, according to The Saratogian.

Three companies announced RF switches based on SOI or a variant of the technology. Skyworks rolled out some new parts. Peregrine announced a product for harsh environments. And RDA’s RF switches are being used in Samsung’s smartphones.

Mentor Graphics announced that MagnaChip Semiconductor has adopted the Pyxis custom IC design platform and the Mentor process design kit (PDK) automation process.  Mentor Graphics also announced that CNH, a supplier of agricultural and construction equipment, has transitioned to the latest VeSys software platform.

Cadence Design Systems announced that it helped Yamaha reduce power consumption for its mobile consumer chips with characterization tools.

Is TranSwitch on the block? The communications chip maker has retained Needham & Co. as financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Altera has signed a definitive merger agreement to acquire Enpirion, a provider of high-efficiency, integrated power conversion products known as power SoCs (power system-on-chips).

The use of Wi-Fi functionality in small-cell base stations will be a game changer for cellphone service providers, according to IHS.

Android and iOS, the number one and number two ranked smartphone operating systems (OS) worldwide, combined for 92.3% of all smartphone shipments during the first quarter of 2013 (1Q13) as Windows Phone crept past BlackBerry for 3rd place, according to IDC.

By Ann Steffora Mutschler
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable.

But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

Whether it is memory stacked on logic, which is most common today, or stacking multiple logic die on top of each other vertically with through silicon vias (TSVs), both approaches are complicated and require more infrastructure than traditional SoCs.

Yervant Zorian, a Synopsys fellow and chief architect, noted that we have always dealt with multiple chips—but the multiple chips that we dealt with previously were packaged chips. “Having packaged chips on a board allowed us to test the chips fully upon packaging when they are on the wafer. And also, after being packaged to give the full quality chip, proven and warrantied to the board-level team to assemble it on the board. Now that’s all good when a die is packaged—a package protects it from further defectively. However, with 3D stacks or 2.5D interposers or some other advanced packaging technologies we are dealing with there is bare die that is unpackaged so the whole issue starts with that.”

So even though the bare die are fully tested, they are prone to defectively during assembly, mounting, transportation. “Whatever you do between the production of that die up through the time it is assembled with the rest of the dies there is this defectivity magnet situation where certain things happen to it and therefore we need to retest it after it’s been assembled—whether it is two dies, four dies, at every stage you need to test it again to make sure that nothing is damaged,” he added.

Clearly, the test challenges with stacked die include the need to test things at multiple points during fabrication and assembly, Petrakis said. “Then there is a big question about how much testing is required. With test there is cost and what do you forgo and what do you actually test.”

There are two schools of thought here, he noted. One is to use the normal manufacturing test type of approaches such as implanting test circuitry as is normally done and testing each die separately. “You make sure that you apply all the tests and then you know you probably have good die to work with. ‘Probably’ is a good term because you never know.”

Then, if the design will use through-silicon vias, what is the best approach to test and how do you get access to the test interface? “On a normal chip you just go to the pads and you say, ‘These are the test pads,’ and you target those. On a TSV-based design there is a lot of talk about landing probes, but the dimensions are so small that there is fear that they are going to be damaged,” he added.

It’s not all doom and gloom with stacked die, though. “The fun comes in when you start stacking logic die,” asserted Stephen Pateras, product marketing director for Mentor Graphics’ Silicon Test Solutions group. “In the case where you had a single logic die you had full access to it. If there were any test pins and memories that needed to be accessed directly even though they are stacked, you’re going through the BiST, the JEDEC standard interface, so you don’t have to worry about accessing the DRAMs directly. But with stacked logic die, now presumably you want to test pieces of a logic die. You want to test the interconnect between them, so you need access each of those logic die independently somehow. Generally you don’t have access to them, because if they are stacked vertically the idea is that the bottom die will be the one that is connected to the package and the other die are connected to each other. So there may be neighbors top or bottom in that stack. That’s where we need to have a way of going through the stack to get access to those die for test so you need some kind of test access architecture that makes use of the TSVs.”

At the foundation of such a test access architecture is the proposed IEEE P1838 standard, which gives just such access.

Zorian explained that IEEE P1838 complements the work that was done previously with JTAG 1149.1 and IEEE 1500, whereby JTAG was for the chips on the board and 1500 was for the cores in the SoC. “P1838 is for the dies in a 3D structure to talk to those dies. You need an access port and this access port cannot be JTAG. It cannot be 1500, but it can be something between the two and very complementary to those working hand-in-hand coherently with the first two standards to handle the new multi-dies in a package. P1838 will allow us to know exactly what that test bus is. The seven-bit communication bus proposed today will communicate the test related functions between one die to the other, from that die to the next and so on.”

By the time 3-D becomes prominent it is expected that P1838 will be ratified as an IEEE standard.

Further, Cadence’s Petrakis noted that the idea behind p1838 is isolation. “How do we isolate one die from the others such that we can test it internally without disturbing anything else? Then it’s not quite really disturbing it. It’s really a matter of true isolation. You do not want any foreign signals or unknown traditions to affect the testing that you are doing. The isolation is that we put the chip in a mode where it only sees data coming in and out from itself. In other words, the application of test reading the results back is not influenced by anything else.”

The looming cost concern
Amidst the technical challenges of 3D and 2.5D stacked die is the discussion surrounding who will pay for all of this extra testing.

Synopsys’ Zorian said, “The two stops in test that we used to have, which is testing the chip at the wafer level and testing the chip post-package, will still be there. But now we introduce intermediate steps so suddenly we need to do more test in between. When I have two dies together, three dies together—these are the prevalent situations where we need to test them. And there is a cost associated with it because it is after the die has been produced, so you cannot cost-wise expect the die producer that is the chip manufacturer to do that. It is a packaging-oriented cost because it happens later on during the stages of pulling those dies together. It depends who will be doing it and therefore who will pay for it.”

At this point, it seems that the cost will not fall to the die producer, but it depends on how the business model develops—especially because several chip manufacturers and foundries have expressed interest in being part of this ecosystem. “Whether it is TSMC, GlobalFoundries or otherwise, if they are doing it then of course it will be the last stage, because it’s not the wafer manufacturing stage or the wafer testing stage. It is one stage after that.”

However the situation turns out, the rising wave of 3D manufacturing and test is causing ripples throughout the entire ecosystem.

By Mark LaPedus
Japan’s Ushio will discontinue its R&D for EUV light sources and will sell its EUV service business to ASML. That means the market has only two EUV source vendors—ASML’s Cymer unit and Gigaphoton. “Ushio’s subsidiary, Xtreme Technologies, competes with Cymer, which was recently acquired by ASML, thus symbolizing an endorsement of Cymer’s EUV technology. Ushio will gain cost savings in both fixed costs and variable costs as 30 staff in their German facility will be shifted under ASML’s umbrella. Although the termination of this business is disappointing, it does reduce future risk of high R&D costs as well as lowering current costs,” said analyst David Motozo Rubenstein in his blog called Chips and Dips.

Taking another shot to displace ARM in the mobile, tablet and other markets, Intel rolled out its new and long-awaited microarchitecture for its Atom processor line.

SEMI applauded the White House announcement that President Obama decided to visit Applied Materials’ facilities in Austin, Texas. This was part of his focus on manufacturing jobs, high-tech skills and technology that will drive long-term economic growth. The administration’s announcement cited Applied Materials’ contribution to innovation and job creation.

While faced with difficult technology and investment choices in R&D, there is now increased pressure on the component-level supply chain, according to Michael Lercel, director of nanodefectivity and metrology at Sematech, in SEMI’s newsletter.

Worldwide silicon wafer area shipments decreased during the first quarter 2013, when compared to fourth quarter 2012 area shipments according to the SEMI.

KC Ang, senior vice president and general manager of GlobalFoundries Singapore, has been appointed to serve SEMI Singapore Regional Advisory Board (RAB) as their new chairman.

Cadence announced its intent to acquire the IP business of Evatronix, adding to its rapidly expanding IP offering.

Cadence also introduced a new version of Incisive Enterprise Simulator, which improves low-power verification productivity of complex SoCs by 30%.

Mentor Graphics announced availability of the newest tool in the Capital software suite, Capital Harness TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models.

SRC and NIST announced the second phase of the Nanoelectronics Research Initiative (NRI). For this phase, SRC and NIST will provide a combined $5 million in annual funding for three multi-university research centers tasked with demonstrating non-conventional, low-energy technologies that outperform current technologies on critical applications in 10 years and beyond.

On the outside, the U.S. and South Korean versions of Samsung Electronics’ Galaxy S4 smartphone look alike. But on the inside, there are differences in key components, according to IHS. Global shipments of solid state drives (SSD) in PCs are set to rise by a factor of seven by 2017, allowing them to claim more than one-third of the market for PC storage solutions by that time, according to an IHS.

The high-flying acceleration and sensor product category was brought back to earth in 2012 when price erosion pulled down annual sales growth to 7%—the lowest percentage increase for motion-sensing semiconductors since 2005, according to IC Insights.

After falling 15% in 2012, solar photovoltaic wafer production is forecast to grow 19% in 2013, passing 30 GW and recovering to the 2011 level, according to NPD Solarbuzz. However, industry utilization is expected to remain below 60%.

Natural gas vehicles (NGVs) on the road in the world’s seven largest automobile markets will reach only 7.5 million as the industry struggles to capitalize on cheap shale-driven natural gas, Lux Research said.

By Mark LaPedus
Enterprise-based bring your own device (BYOD) programs continue to become more commonplace. In fact, 38% of companies expect to stop providing devices to workers by 2016, according to a global survey of CIOs by Gartner.

What would happen if half of all global DRAM production, two-thirds of NAND flash manufacturing and 70% of the world’s tablet display supply suddenly disappeared from the market? For high-tech companies, this could be the outcome if current tensions escalate to the point of war on the Korean peninsula, resulting in the disruption of South Korea’s technology manufacturing base, says IHS iSuppli.

Intel telegraphed its future directions. The chip giant has named Brian Krzanich as its next chief executive, succeeding Paul Otellini. Krzanich, Intel’s chief operating officer since January 2012, will become the sixth CEO in Intel’s history. As announced, Otellini will step down as CEO. In a research note, Hans Mosesmann, an analyst with Raymond James, said: “We are not entirely shocked by the news but note that some investors preferred an external option on the belief that new blood was needed. Giving Krzanich’s manufacturing background we think the appointment is an indication that Intel will continue Paul Otellini’s strategy of building bigger/better fabs to attack the market. We also believe the move toward better manufacturing processes (like the 450mm transition) will remain front and center.” Added RBC Capital analyst Doug Freedman: “The move to appoint Renee James (as president) is likely in support of the vision of Krzanich’s and the board has laid out for the future of Intel. This appointment validates the increasing importance of on-going software development to Intel’s future, whether it be internally or in collaboration with partners.”

Microsemi has inked a foundry deal with Intel. Microsemi is currently engaged with customers and has started designs utilizing Intel’s 22nm tri-gate technology. Product delivery is anticipated to begin in late 2014 to early 2015.

Infineon and GlobalFoundries announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology. The cooperation will focus on technology development based on Infineon’s eFlash cell design and manufacturing of automotive and security microcontrollers with 40nm process structures.

GlobalFoundries has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20nm and 14nm. GlobalFoundries is using the Cadence Pattern Classification and Pattern Matching Solutions.

SEMI announced that Philip Yeo, chairman of Spring Singapore, and Lee Kok Choy, country manager of Micron Technology Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry. The awards will be presented during festivities held at Semicon Singapore 2013 on May 7.

Soitec has finalized a ZAR 1,000,000,000 (more than $100 million) solar financing bond issued by CPV Power Plant No.1 Bond SPV, an affiliate of Soitec Solar GmbH. The bonds will finance the construction of a 44 MWp utility-scale concentrator photovoltaic (CPV) solar power plant in Touwsrivier, South Africa.

Applied Materials and The Center for Science Teaching and Learning (CSTL) announced the San Francisco Bay Area grand-prize winning team and nine finalist teams in the 2013 Clean Tech Competition.

Rudolph has purchased selected assets related to 3D metrology from Tamar Technology.

Proteus Digital Health has completed a second closing of its Series F financing, raising $62.5 million in total. New corporate investor Oracle joins Otsuka, Novartis, Sino Portfolio and others in this funding round. Proteus is working to create a new category of products. Called Digital Medicines, these new pharmaceuticals will contain a tiny sensor that can communicate, via a digital health feedback system, vital information about an individual’s medication-taking behavior and how their body is responding.

Is Mindspeed Technologies on the block? The supplier of semiconductor solutions for communications has retained Morgan Stanley as a financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Spansion has acquired the microcontroller and analog business of Fujitsu Semiconductor for approximately $110 million, plus approximately $65 million for inventory.

Amkor Technology announced that Stephen Kelley has been appointed to serve as president and CEO. He succeeds Ken Joyce, who previously announced his intention to retire.

ASE remained the world’s largest OSAT in 2012, according to the new rankings from Gartner.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Ann Steffora Mutschler

With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations.

Certainly, double patterning was the biggest change and the biggest concern on the designer’s minds when they began moving to 20nm, observed David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. They wanted to know what double patterning was and how to deal with it.

“Also, for the foundries themselves, they wanted to know how were they going to find provide a solution that was viable to the users,” Abercrombie said. “That’s certainly been the bulk of the questions we’ve gotten with the move to 20 nm and below—things related to double patterning, finding and fixing errors, how to deal with parasitic extraction or LVS or whatever, place and route and other things associated with double patterning. It’s certainly a new and different kind of error to deal with.”

The nature of the difference

Most design rule checks typically are associated with either a single polygon or its neighbor. That includes width or spacing or area, which can be complex. For instance, the space is dependent on the width, the run length, etc., but it’s still basically a neighbor-to-neighbor interaction or the layout of the shape itself.

“With odd cycles and anchor path errors, it’s now an issue of the network of interacting shapes—multiple shapes that can be spread over long distances and how they interact with each other in the network of spacings to form this odd cycle or this anchor path,” said Abercrombie. “It’s very different than the traditional rule in that sense. In some ways people have learned to think about it more like an antenna rule that is network-based. It’s not conductivity-based, it’s spacing-based, but it’s about the network of shapes and the spacings.”

This is a whole new level of complexity for designers to deal with. “If you’ve seen 20nm designs from customers, they’re different from 28nm and the reason for that is because of the core fundamental issue in double patterning of conflicts, where one defines a conflict as a native conflict or a loop conflict,” said Manoj Chacko, product marketing director at Cadence noted. “A native conflict is something that you can detect but cannot fix without a design change. That means the designer has to make a design change.”

Consider a loop conflict, for example. If you have four polygons, for example, and two masks for double patterning at 20nm, then each polygon is split into two masks and four polygons is split into eight. That works fine in a very regular layout, but not all layouts are so regular.

“This seems kind of reasonable given that you can assign four polygons eight colors, but in reality it’s a little different because it depends on the proximity of the polygons to the others and so on,” Chacko said. “If you had nine polygons because of an L joint, for example, even if you have to split four into eight but the eighth polygon is not straight, it’s an L—now the L basically may become two colors again, making nine. This is called a loop problem, where you have the eighth polygon that is split into 2 colors. This is the problem that designers see. It doesn’t require systematic changes but it does require identification of the loop, and then there are methods to fix it.”

One other problem is when you think of that last ninth polygon as an L, where at the corner of the L where the two lines join. That could make a split. The foundries decide on the split based on their process. They may not do a split at a joint. They may do it on a straighter edge. But when they make the joint, there is an overlay of these two masks. If you think of that ninth polygon – that eighth polygon that got split into two pieces—they will expose first one joint, then etch it, then expose the remaining portion of that L, then etch it. Now you have to make sure these two exposures make that one L that the customer wants. The idea is that the overlay is a problem. In manufacturing, it’s called overlay. In design, it’s called stitching—meaning they have to make sure there’s enough overlap at the split/splice location. So that is another issue that design tools have to give good feedback about.

These coloring issues are exactly why Mentor Graphics looks at this differently, Abercrombie said. “Displaying the error as a ring is so much more productive than showing the colors because this was the initial mental struggle [with double patterning,] and the request that came up most was, ‘I want to see the colors.’ That was the first thing designers said—only the colors. And I said, ‘Why do you want to see the colors?’ ‘So I know what to fix.’ Seeing the colors is actually a misleading thing. If you imagine an odd cycle there is no legal way to color it. That’s the problem. That’s why it’s an error. There is an odd number of things interacting, and you have two colors and you can’t divide and odd number by an even number or you get a remainder. So you can’t color them alternating colors in an odd cycle, because somewhere in that cycle you’re going to end up with the same two colors next to each other. When you ask the tool to show you colors, inherently the tool can only show you the wrong colors because in that configuration there are no legal colors.”

A second problem is that there are many, many different wrong colorings that could be shown because there is no right one, so the selection of which one to show is completely arbitrary.

This is why Mentor approaches this type of error with a ring scenario. “By showing colors, there could be a random chance that I showed you that one error that may be the hardest one to fix and hence I’ve pushed you down a path of most work,” Abercrombie said. “By ignoring the colors—not showing the colors, if at all possible because it’s just going to mentally push you in a direction—look at the ring and look at the options that it is showing you as a benefit. Now you have multiple choices and you can do what is best for you.”

Not so scary

Mentor’s Abercrombie asserted that as scary as it is for designers to learn something new, “like anything else once they start dealing with it they learned pretty quick and they found it’s not those it’s not as overwhelming as they thought.”

And there are even some nice things about double patterning errors, he said, in that although the error can seem large and involve a lot of shapes with a lot of spaces around things, the advantage of it is that you have multiple options for fixing it. In a given odd cycle, for example, you only have to break one separation within the network of polygons that are interacting and it is clean. You don’t have to fix them all. You only have to fix one of them.

“In that way a single error has many ways to fix it and that’s better than a lot of other DRC rules,” he said. “When the check is like ‘me and my neighbor’ and how far away we are—when you only have one option you’ve got to fix that space and that may be difficult because of the ramifications of trying to fix it. When you try to move those edges, or you might have to move vias and other shapes, that could be a very complicated location to fix. But with a DP error, the fact that it’s got multiple options gives some freedom to say, ‘Here’s an odd cycle with five different spaces and there are actually five choices that I can make.’ I can look at which one is easiest for me.”

Saleem Haider, senior director of marketing for physical design and DFM at Synopsys, agreed. “[DP errors], at the highest level, look pretty much the same as a general design rule error. Even without double patterning at 28nm we have a fairly complex set of design rules that the foundries gives us and design implementation has to adhere to those. Ten years ago, pretty much all design rules were somewhat width- and spacing-oriented. Now the rules are very, very complex. Some of them are based on the size of the object itself, and there are spacings from corners and edges and sides, etc., so it’s a fairly complex set of rules.”

Double patterning becomes a part of that, so at the end of the day, a DP violation or a DP error is going to, generically speaking, look just like a design rule error, he said. Just as if there was a design rule error in the design, the foundry would not accept that design because when the design comes into the foundry, one of the first things they do is run design rule checking on it to see if it meets the checking criteria that they specified. If the design doesn’t meet it, they will send that design back to the design team. It’s part of the incoming process. It’s the same for DP.

Like many new technologies, understanding double-patterning errors is just a learning process, Mentor’s Abercrombie concluded. “The foundries first had to figure out what it is they want to provide and support and work with us to make the tool capabilities to do that. Now that they’ve rolled out the decks to the customers it’s been more about educating the customer to overcome that initial shock of something new and get them educated. As soon as they play with it for a little while, it comes pretty fast. They’re smart. For the ones that have already made that move, they are settling in pretty quickly.”

Additional resources:

http://www.mentor.com/solutions/foundry

http://semimd.com/mentor/

http://www.synopsys.com/Tools/Implementation/CapsuleModule/ic_validator_wp.pdf

http://www.synopsys.com/Solutions/EndSolutions/20nmdesign/Documents/20nm-and-beyond-white-paper.pdf

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”