By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that conversation, which took place before a live audience at the Semico Impact Conference.

SMD: Do subsystems limit the number of players that can compete in the market by raising the cost of entry?
Kablanian: Absolutely. The integrated device manufacturers and large chipmakers have been able to do this integration for years. It includes everyone from software to architect to RTL designer, physical library providers to the fab. They have the whole vertical know-how. For a small company to do this is almost impossible. Naturally it will limit the number of companies doing this, and it will force consolidation among a few players.
Gianfagna: You’ll have to have more investment and more vertical knowledge, and that in general will result in a better deliverable. I don’t think it will limit innovation, though. The market resists being homogenized. Differentiation will continue at a higher level of abstraction.

SMD: Software is a subsystem, right?
Gianfagna: It is.
Roddy: There was a time when you could count 500-plus IP providers. But if there are 3,000 to 5,000 design starts, you can’t have 500 IP providers. They’re all going to wind up with five customers. That doesn’t work. But there can be 30 to 50 IP providers.

SMD: Both of the big foundries have done testing of IP. Will that continue with subsystems?
Meyer: You have to look at that by technology node. The closer you are to the bleeding edge of technology the more expensive that investment is. There you’re going to limit the number of partners. You have to do that because you need solutions as early as possible for existence proof of that technology node. We work very hard on that, and we do that with guys who know what they’re doing and who are capable of providing a level of support at that design level. It’s not just throwing it over the wall and getting IP. The IC integrator has to be involved to do that successfully. But as we start moving away from the bleeding edge, we want to work with innovative companies doing things like power management at 1.3 micron or even 65nm. With embedded and non-volatile we look to work with those companies.
Kablanian: There is room for the foundries to adopt new IP and take some risks. That has not been done.
Meyer: A lot of what we’re doing is anticipating yields. A lot of our focus is on working with companies like Cadence and Synopsys and Mentor on yield enhancement, and we’re working with system providers to understand how that IP will work in silicon. We think our customers get a lot more of an advantage working in those areas, like DFM, as opposed to the system-level aspect. That’s why you can come in with a customer who really understands the value of what you’re doing.

SMD: One of the great advantages of stacking die is that you don’t necessarily need to worry about developing IP at the latest process node. What does that mean for subsystems?
Roddy: If it becomes widespread then the economics of the value chain will change. That’s a dramatically different business model because the IP provider essentially is a contractual silicon provider. They might sell you a 50-cent sliver of silicon that you’re integrating, which is dramatically different business structure. The analog IP provider works to validate with the global partner. You could be sitting back at quarter micron for your analog and your memory might be at 14nm.
Gianfagna: There is certainly more predictability.
Roddy: It adds much more opportunity for the analog part, which has less flexibility because they have so many process-specific attributes. If you get it right, then there will be an emphasis on keeping it in that process.
Gianfagna: If you get it right for subsystems, you can make the same argument.
Roddy: You can still validate a piece of silicon with the proper interface. That may be the next evolution.

SMD: Subsystems aren’t a new concept. It’s been done at the board level for decades. But have we gotten to the point where designers are willing to let others create and verify these subsystems?
Gianfagna: It’s no longer a question of who designs the best circuit. It’s who integrates it the best.
Roddy: There are a handful of companies that still do their own libraries, but the vast majority do not. The vast majority doing SoC design are no longer providing all of the pieces, but they are working with vendors to optimize blocks wherever they can.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that conversation, which took place before a live audience at the Semico Impact Conference.

SMD: If we have two good memory subsystems and they no longer work when they’re put together, who’s responsible and how do we sort that out?
Gianfagna: The one who fixes it is always the system designer. But who’s responsible is a good question. Is it because the spec was wrong? Is it because the design was wrong? It could be the IP vendor, the subsystem vendor or the system designer. Natural selection will eventually weed out the problem, but at the end of the day is the system vendor who has take responsibility. They’re the general contractor. They have the responsibility of making sure everything works, which is a daunting task at this level of complexity. Even though things may comply with standards, that may not mean the same thing to everyone.
Roddy: The are two pieces to this. The first is that the subsystem has to be a naturally occurring subsystem. You can’t take two things that don’t normally go together because no one will know how to put them together. Expertise in one area isn’t the same in another. The second is that you see system designers doing an immensely larger amount of system simulation. If they can do it early enough they can determine if these things will work together with the system resources like bandwidth and memory. Planning ahead is the key to avoiding problems.
Kablanian: The best thing is to avoid having two similar subsystems on the same chip. You need to understand how to test a memory, for example, how to integrate it into a common test methodology, and how to debug it. If you have two similar subsystems, it’s almost impossible to figure this stuff out.
Gianfagna: But if you buy two subsystems from the same vendor, will they work together? I would hope so.

SMD: Where does the foundry sit in all of this?
Meyer: If it comes down to a design issue, there’s not much we can do. What we can do is enable design components ahead of the integration into the system level. For instance, if it’s a third-party IP partner, we work with them as we go through the process of silicon validation. Increasingly, for more advanced technologies we’re actually building in a second spin. We try to get out early in the process, work with our IP suppliers to get on early shuttles so we get back results early. We have a learning step through that to make the process more robust. We’ll do what we can relative to silicon validation with third-party IP. When we have a large customer that does its own IP, we have a team in design enablement that does co-optimization with them. That team actually works with our customers early. We often run their test chips as part of that process, as well, for their libraries, memory and IP. But we also have a team that goes in and does early co-optimization and gives them our input as to anticipated silicon effects. Whatever the problem is, we’ll get involved as much as we can, because until it gets into production everything we do is an investment to save time. We’re highly motivated to get all parties into production.

SMD: When you look at IP it’s a black box. Subsystems are bigger black boxes. Is it harder to verify and integrate them?
Roddy: If the vendor has done their work to validate the box, whether it has one element or four, it should be largely immaterial to the integrator. The inflection point is when you start stacking software on top of the multiple elements and it goes out and addresses other resources and you’re bus traffic-dependent. You have to factor in the expected system behavior, including latencies and interactions between multiple blocks and the system. What are the potential problems from the graphics subsystem fighting with the video subsystem? That’s where we get into system modeling and analysis. If the vendor assumed a certain set of conditions that your SoC doesn’t adhere to, then all the characterization goes out the window.
Kablanian: Testing the silicon is not sufficient because many of the IPs people use are configurable. What works in one case may not work in another. The crux of this is a verification methodology, and companies that figure that out will be successful with this strategy.
Gianfagna: There’s a topic we’re touching on here that is very important, which is what it means to deliver a certain level of quality. There are not a lot of standards there. This is a big problem. There is no vocabulary we can use that is consistent between IP vendors. You need machine-generated metrics, which is something the IP community won’t like. But we don’t even have a common language that says this IP is of a certain level of quality and it has passed these tests.
Meyer: Ultimately, if it doesn’t work then GlobalFoundries is involved. We’re doing all we can. Obviously we have partners at the very leading edge working on this, including verification of their IP. When we start looking at 28 gigabit-per-second SerDes, that’s a whole subsystem. We are not the systems experts, but we put into place a very good support structure for them. Now, when you start to move away from the bleeding edge, clearly the challenges are not as great. We’re working with customers on all types of IP, but for each different application and each technology node we are working with customers and IP partners to make sure their IP is as risk-free as possible.

SMD: Even in the most advanced devices we’ve seen major errors crop up in subsystems. There is no way to test all of this complexity. Are subsystems really a step forward in reducing complexity or are they just adding new wrinkles to it?
Roddy: I don’t think subsystems change the overall equation. There are too many pieces. In the fully synchronous synthesizable areas the processors interact with the software so it becomes an issue of software correctness. The good news is that you do have software, so it can be fixed. If you can do an analysis and make sure the parts that consume data flowing through the device are properly calibrated and you model all the use cases, then you can fix the software to address everything else. It’s all about appropriate system-level design. It isn’t any different today than 15 years ago when we worked on IP blocks instead of subsystems. It still gets treated like a block.
Gianfagna: There needs to be a methodology. You have to run tests on those blocks before you create masks. But if the quality of the incoming data is vetted you’re going to have fewer problems later on for everyone in the supply chain. From the front of the supply chain to the back, everyone has to step up.
Roddy: We look at a core as being a subsystem. It’s a complex set of registers, data paddles and so forth. That’s an integral part of an SoC. Typically you bring up a technology node with very regular structures. We’ve integrated an A9 core and integrated it into our test chip strategy. It gives us a different understanding of the technology problem, which is great for isolating defects. But you also now have to consider proximity effects, so we now use the A9 as part of our test strategy for bringing up our process technology. We started looking at these problems from the yield side. Once we see them work, we start increasing the frequency. We are trying to support the subsystems down to our test strategy.

The Silicon Integration Initiative (Si2) announced the founding members of their Open3D Technical Advisory Board (TAB).

The group is chartered to enable interoperable 2.5D and 3D design flows with open standards, providing common formats and interfaces. The founding members of the Open3D TAB are ANSYS, Atrenta, Cadence Design Systems, Fraunhofer Institute, GlobalFoundries, Intel, Invarian, Mentor Graphics, Qualcomm, R3Logic, STMicroelectronics and Texas Instruments.

Initial areas of focus for Open3D TAB members include developing standards to support:

• Definition of the power distribution network across the die of a 3D stack, a topic for which a contribution has already been received in response to the request for technology (RFT) that was released earlier in the year

• Thermal design and analysis of an entire 3D stack, including thermal constraints between neighboring dies

• Expression of design constraints into and out of the path-finding and floorplanning stage of the overall design process

“The Mentor Graphics Calibre business unit has been working with Si2 to drive standards with the donation of iDRC and other OpenDFM efforts for the benefit of the overall industry for multiple process nodes, and we continue to support Si2’s efforts as the industry moves from 2D to 3D,” said Juan Rey, senior director of Calibre engineering at Mentor.

“3D technology touches upon every aspect of the semiconductor design and manufacturing supply-chain,” says Andy Brotman, vice president of design infrastructure for GlobalFoundries. “As our customers implement this technology, it is in our best interest to participate in the standardization of basic ground rules to enable ultimate success.”

Membership in Si2 projects is open to all interested parties across the semiconductor supply chain.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: So have we learned anything over the years from standards?
Radojcic: I do think we’re smarter than we were. It’s easier for tools guys to look at standards and subscribe to them than in the past. There isn’t as much ‘Mine is better than yours.’
Gianfagna: There’s a lot of work to create the standards. There’s a lot of work on the EDA side and there’s a lot of work on the process side. And then we talk about all that work being front-loaded. But the uptake is really slow. With 3D we talk about memory and processors and then go to something else. There’s a tremendous investment that has to be made over the next 18 months, and then we may not get it back for seven years.
Hogan: Xilinx has been shipping its prototype in limited production. What it always takes to get everything going is the killer app. Who would have thought about a full-finger touch-screen for your phone until Apple showed us we needed it. Now everyone has it and Apple is fighting with Samsung for displays. So what’s the killer app? I was not interested in touch displays. They have low margins and it’s a bad business. But suddenly touch displays are hot. What will it take for 3D to kick off?
Subramaniam: You don’t have to have a killer app. In the Xilinx case it’s pure economics. What they have done is create a tile structure for the FPGA. Rather than have a big FPGA die they have taken slices and hooked them together. The yield is inversely proportional to the area of the chip. If they went to a traditional FPGA model their yield would be extremely low. By going to a tile model they will have many more good tiles and their overall cost will be significantly better. Where you are talking about arrays or repeatable structures there will be benefits. In multicore designs, why build a 16-core chip? You can build four-core chips and put them together.
Hogan: I don’t disagree with that. But I do say it’s the system appetite that drives all of this stuff.
Wingard: That’s what makes Wide I/O so interesting. There is a system appetite in smart phones right now for a massive increase in acceptable bandwidth that we don’t know how to get to without doing this. That’s why so many people are aligning around Wide I/O.
Radojcic: Yes, and even though we doubted that phones would do this, we hurt in one area even more. Look at all the things you’re putting in a phone. It has to have a small footprint, so many gigabits per second of bandwidth and low power. It’s painful and 3D can help. Phones will probably be the killer app and most people are now saying it will happen in 2013.
Hogan: Video, too.
Wingard: Yes, video content with minimal power.
White: For mobile applications, does 2.5D suffice or do you really need to go to full 3D?
Radojcic: We are pursuing full 3D and so are most of the people in the phone business, primarily because of the form factor and cost. If you think about an interposer, you’re adding another die to the cost. Conceptually an interposer is an elegant solution and it works fine for someone who sells a product for $100. If you throw in a $1 interposer it’s no big deal. But if you’re making a $5 die and you throw in an interposer, it is a big deal

SMD: How about the thermal issues in 3D? Are they worse?
Radojcic: Thermal is an issue in 2D or 3D. It’s always an issue. 3D gives you some opportunities to help with the thermal. You can drive the power down. It can work as a heat spreader. It’s harder, but you can engineer it correctly. Do we have the infrastructure for dealing with thermal? Some of it. You can do thermal analysis. But can you take thermal information from a memory producer? No. You need to do a custom job to interface with the memory guy to see where he anticipates thermal issues. What we need are exchange formats. The tools are there. We need a methodology.
Gianfagna: There’s an analogy with timing-driven design. It used to be that you’d do timing analysis on the outer loop, then you’d do place and route and it would become part of the inner loop when you couldn’t get timing closure. The same thing is happening here. There are standalone tools that will do thermal analysis at the outer loop. That’s not going to work for a long period of time. You’ll need them in the inner loop as part of your iterative placement and partitioning. That’s not an unsolvable problem, but it is another hurdle across.
Wingard: And in a phone it’s mode-specific. The thermal patterns for an SoC are different, depending upon the use case. If someone uses their phone to watch a video it’s different than using it for a phone call.
Radojcic: And it’s different if you’re doing it in a hot car in Arizona.
Wingard: Some of this happens as a result of PoP. What used to be a package now becomes a heat source. With TSVs the granularity is finer, but if you’re looking at the hot spots on a chip that someone else gave you it’s going to be really difficult to work with.
White: You have to work with a transistor-by-transistor power model, and you use that to drive your decision-making.
Wingard: But it’s so use-case dependent.
Subramaniam: It’s not that bad. You’re not talking about different materials. It’s all silicon, so it’s easier to model. You can do the modeling and the analysis.
Wingard: And it’s more important to model.
Hogan: It will follow the arc. There will be details of transistors, then someone builds the lump model, and the lump model won’t give you enough degrees of freedom so someone will build a better model with more granularity—but not too detailed because you don’t want to slow it down in simulation.
Gianfagna: If you want to do this analysis, is it enough to do it structurally or even from a vector input point of view? You need to start running software scenarios. Bringing software into a hardware architectural design is interesting today, but it will be critical in the future.
Radojcic: This is all true and scary, but thermal is a good conductor. So do I need granularity for every transistor? Probably not. One transistor may not be quite as hot as its neighbor, but it will be pretty close. And do I need to run all these different use cases? Probably not all of them. You can say you’re going to burn most of your power here. Everything needs to be use-case and software-specific, but a lot of it we can do now. We can do thermal that’s plus or minus ‘x’ percent.

SMD: Does 3D change who makes money and where they make money?
Gianfagna: One of the Holy Grails for EDA is whether they can be a cost-enabler instead of a cost of doing business. And can they partner with customers to open new markets? Beyond that, who’s the general contractor? You’ve got a 3D stack that consists of multiple die that are known good quantities with a silicon interposer put together for an end customer. There are yield risks, assembly risks, inventory risks and design risks.
White: The foundry is also going to work very hard to get a cut of that.
Subramaniam: For us it’s just another piece of silicon and another way of packaging silicon. We don’t see it as any different from what we’re doing today.
Gianfagna: The supply chain is more complex.
Subramaniam: That’s true. And there are some issues with test. But by and large it’s very traditional.
Radojcic: It is different. Today you don’t go and buy memory and own the memory inventory.
Subramaniam: There are some differences, but they’re all manageable. We do multi-chip modules and PoP. We do all the different packaging technologies that are out there. This isn’t just a packaging solution, but it’s not all that different.
Hogan: Embedded in that is a question of where the value flows. The SoC guys still get the majority of the value. The question is who picks up value down below? Is it EDA or the enabler or the functional equivalent.
Gianfagna: The system guy gets most of it because that’s who defines the software and the delivery vehicle.
Hogan: So the rich get richer.
White: I don’t like that answer but it is the answer.
Hogan: Joe Costello described EDA as five dogs and one dog bowl. Below the system that’s what it’s going to be like. The value will flow differently, though. EDA will get some. I don’t think the foundries will get it all. [Value-chain producers] will get more.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: How important will standards be in 3D?
Radojcic: We definitely need standards. But before the world invents standards we have to have a pretty good image of what we’re doing. With Wide I/O memory that was easy. JEDEC was developing the standard so it was all good. If you open the door for logic on logic, it’s not going to be seamless. You really need to think about what kind of partitioning makes sense. You’re not going to want to split your clocks. We first need to do that as an industrial community.
Wingard: In the logic-on-logic space it’s going to be a closed shop model first. It’s going to be the same people designing the chip above and below.
Subramaniam: Yes, they will have control of the area and the design. The other place I see logic working is in re-use. A company could build the building blocks and then use those building blocks for different applications. Again, that will be a closed-shop approach.
Wingard: Then you need standards. Everytime you mention re-use you will need a standard.
Subramaniam: At least you will need an internal standard.
Wingard: One thing that’s different about the way we’ve done packaging before is that we had a layer of the package in between that had the same protocols and signaling levels even though our bond patterns didn’t match exactly. We relied on PCBs to make things match. With TSVs we don’t have that anymore. You have to agree on everything, from pad pitch to signaling all the way up that stack.
Radojcic: And it’s all interdependent. Figuring it out is a big problem.
Wingard: That’s what makes interposers so interesting. They’re the bridge for things like logic on logic. I think 2.5D logic on logic will happen well before 3D logic on logic for exactly these reasons.
Radojcic: For companies that can tolerate the form factor.
Wingard: Yes.

SMD: Isn’t one of the big issues focused on responsibility? You may have two perfectly good chips, but when they’re put together they don’t work properly.
Radojcic: There are things before that we need to figure out. We need information from the memory guys for stacking memory on logic so you can manage your hotspots and mechanical interaction. We need to agree how we exchange information between us and what that information includes. Then, when it comes to the building side, we need to create a supply chain business model for who owns what.
Hogan: This isn’t trivial. It’s a lot of work and we will solve it. But why bother? Let’s back out for a moment. The SoC is the way everyone delivers system value today. That’s dominated by the ARM processor. Everyone uses something that looks like an interconnect. On that interconnect people differentiate themselves with two things. One is a peripheral device. Texas Instruments is a great example of that. Someone else might add memories. The second thing is software. What 3D allows you to do is consider other things and other arrangements. We can spend a lot of time talking about the margins on SoCs, but they’re 50% or 60%. That’s why everyone does SoCs instead of discretes. There’s more value in the system. There will be a lot more integration of peripheral devices and software. That’s what’s exciting about this. It’s not to trivialize all the EDA work and the supply chain, because there’s a lot of work, but that’s what’s really interesting for me. This will allow more democratization of a design.
Gianfagna: You were talking about how the ecosystem would evolve. First it would be monolithic and internal by one company. Then you try to figure out how you do re-use, and then there will be third parties. That’s exactly how the existing 2D ecosystem evolved. That’s depressing. It says we didn’t really learn anything from 2D. You don’t think we’re any smarter?
Wingard: We’re starting with the standard interface stuff. Logic on memory is the early example. It’s not a closed shop today.
Subramaniam: It is a closed shop. Samsung owns the processor and the memory. They already do this Wide I/O design. They’re not going to wait for the standard. There will be a standard eventually, but they’re going to drive it.
Wingard: My guess is that’s not the volume driver. It’s a technology-proving vehicle. But independently, it will be standard interface first, then logic-on-logic in a closed environment, then we’ll figure out what else we can standardize on. To think that we’re going to get standardization ahead of where people know how to use it is very scary.
Gianfagna: So we’re stuck with standards driving the ecosystem and not the other way around?
Hogan: Anytime you have standards in place you lower the barrier to entry. That accelerates the ability of the ecosystem to grow. But there will be companies like Samsung that can’t wait, so they’re going to do their own version. And they have enough volume to do it. For the rest of the world they’ll have to wait for this chip-to-chip and logic-to-logic capability. But it will happen.
Subramaniam: On the logic-to-logic, I’m still not convinced a standard will evolve. The reason why a Wide I/O standard evolved was that you need a third party. Nobody is going to be designing their own memory. A third party is necessary. But with logic on logic, people may view it as a competitive advantage not to have a standard. There’s no reason, if I develop my own logic-on-logic, that it should hook up with a third-party logic design. I’m not agreeing with logic on logic becoming a standard.
Gianfagna: At one level that’s true. People don’t want to be homogenized.
Hogan: At CES Microsoft said it was going to use an ARM-based SoC with an Nvidia block. An Nvidia block? If you think about Xbox development they started out doing everything themselves, then they gave up and went to ARM. They’re not even doing their own graphics processor anymore.
Wingard: PoP (package-on-package) has been about memory on logic. One common version is baseband on application processor. Right now that business is done partly because some of the companies don’t have their own baseband assets. I would expect that to be logic-on-logic in the future. The more advanced basebands need more access to memory than they did before. There’s going to have to be some reasonable baseband connectivity in the future. Even if there aren’t any industry standards, with logic on logic if you want to get any re-use you’re at least going to need company standards.
Gianfagna: You guys are debating whether you integrate IP blocks on one die or two. You’re going to start with a certain number of building blocks. But if you have one at 22nm and one at 65nm, how do you connect them?
Wingard: I don’t think the model for a long time will be, ‘I’ve got this system to go build and I’m going to partition it across a set of dies the way I partition it across a set of FPGAs.
Gianfagna: Why?
Wingard: Because of legacy and because it’s too expensive. With legacy I’ve got something that’s been proven. But I’ve got something else I want to change, so this other die is the one with the new stuff on it. It’s that kind of re-use and how systems evolve and not having the assets because this thing comes from somebody else. All the logic doesn’t have to end up on one die.
Radojcic: There are many new constraints, both physical and architectural. The idea is that you take one die and slap it together with another die. But when you start thinking about it more and more it makes your head hurts. There are all these degrees of freedom that are interdependent.
Hogan: If I’m Cisco, I’ve got 35 million lines of legacy code I have to run in my router. How do I upgrade? It would be great to have an interposer because I can leave all that old code. Routers, servers and base stations are going to be loving this. The mil/aero guys are going to love this, too.
Subramaniam: If you have a 28nm chip, your upgrade could be done with an older chip geometry, and then you can use an interposer to slap the two together. Your equipment and design costs are going to be much lower with this approach.

SMD: There are two trends here. One is to build more and more on the SoC. The other is to set up all these separate processors. Does 3D move it all into one device and does it become more of a logical partitioning problem?
Gianfagna: Yes, but it’s going to happen slowly. You’ve taken what used to be on a printed circuit board and integrated it into a device. The more planes you add, the opportunities to mess up go up exponentially around thermal, stress, mechanical, heat dissipation, TSVs that don’t have anything to do with an interconnect. You can think about integrating multiple pieces of the system in the same package, but it’s going to take a while to get there.
Hogan: If you’re talking about integrating silicon, try getting TSMC to add two more mask layers or two more stops as the wafer travels around the fab. You need an enormous amount of volume because they like to minimize risk. Otherwise you’d need your own fab.
Subramaniam: If you put a TSV on a chip you’re effectively creating three or four layers on top of your 10 layers of metal. That’s going to happen sooner or later. The question is how many more layers will you get. There will be a limit.
Hogan: When we did studies on SiP (system in package), the yield is a linear function with the number of layers. Every time you add another layer it’s worse yield.
Subramaniam: But these layers are very coarse.
Hogan: I understand, but what should your yield be? How do you even test these things. The system is only functional when you have both die together.
Subramaniam: And you cannot use wirebond.
Gianfagna: You might also get a really fancy boundary scan and isolation logic.
Radojcic: We’re having a discussion the 3D industry already went through. The first discussion was, ‘This is really cool.’ The next discussion was, ‘How am I going to do this? How am I going to test this?’ The classic hype curve has been followed. There is a trough of disillusionment. But some of these things are already solved or solvable. It’s good to focus on, ‘We can do this. We can do memory on logic. So let’s focus on the work to be done.’ The work that’s left to be done is design exchange formats so you can model thermal or stress behavior from die A to die B, and you need feed power from tier two to tier one. We just need to get our act together and create standards.
Hogan: If you have standards in place you can get things done. If you have to integrate this stuff, no one lets the standards out and you have to fight for them—or you get competing standards.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SemiMD: 3D stacking means different things to different people. The type of 3D stacking talked about by companies such as IBM and Freescale is different from putting older generations of analog IP on top of new technology. What’s likely to really take off and when?
Gianfagna: The stock configurations will be first. What I’ve seen is processor on one layer, memory on another, and the sexy thing is ‘wide I/O, narrow I/O, silicon interposer.’ How do you really optimize memory and processor?
Radojcic: It is a memory and logic combination and there are two solutions. One is side by side with an interposer for guys that can tolerate a big footprint. There is wide I/O and logic. There also is the version without an interposer that some companies are pursuing. There is a consensus in the industry that all these types of technology have traction and will hit product with 3D.
Wingard: It’s important to look at why that’s so compelling. It boils down to the fact that in the last 30 years of computer architecture the processor speeds have been increasing while fundamental memory bandwidth has not. There is a chokepoint in the system where we have this large number of data requests being funneled through a single interface to external memory. Then you get onto the DRAMs themselves and they have a lot of bankable parallelism. We went to multi-bank DRAM a long time ago. What TSVs (through-silicon vias) in particular give us is a cheap way of greatly increasing the bandwidth between the logic chip and the memory. We can’t do it with bond wires. We have to do it with something where the cost of the connection becomes orders of magnitude cheaper. That’s what makes it compelling.
Radojcic: The value proposition is wide I/O. TSVs are the enabler.
Hogan: I’d back up even further. It’s always performance, power and cost or area. You get the opportunity for less latency. You don’t have a memory controller that’s chewing up a bunch of power. And you can integrate different process nodes to get the cost down. Xilinx is shipping a transposer rather than an interposer. They can drop four FPGAs onto that. It’s like a reference board on silicon.
Subramaniam: What we’ve been talking about with an interposer is 2.5D. It’s two pieces of silicon sitting on another substrate. It’s a packaging technology. There are several advantages to this. In a plastic substrate you are constrained by the design rules of plastic, which are hundreds of microns. If you go to silicon you are constrained by silicon design rules, which are tens of microns. What happens is that you are able to have significantly higher interconnect between chips, which you did not have in the past with plastic substrates. The reason you’re getting high bandwidth is because you’re about to have a 512-bit I/O instead of the standard 64-bit I/O. You can do that because you have the luxury of these smaller pitches on silicon. The second thing wide I/O does is improve power because you don’t have to have your typical DDR interface with an I/O buffer running at a higher voltage. With wide I/O you don’t need an I/O buffer, because with two pieces of silicon sitting so close to one another you can drive it with core voltage. That’s where you get the significant improvement in power.
Wingard: Actually, you don’t even have a PHY. There are no DLLs or PLLs.
Hogan: It’s a scheduler.
Subramaniam: So you can put in a baseband and an RF, or any other chips, and you can increase the speed at which these two chips can talk to one another. You can have more I/Os between the two of them and incorporate that. That’s the biggest advantage of silicon interposer technology. With 3D you’re going further. The devices will have active transistors in them and a TSV. But that will require significant changes in design methodology, CAD tools and design rules. The whole ecosystem needs to evolve significantly for that to happen.
Hogan: This is really what we used to refer to as hybrid technology. This idea has been around forever. We’re just introducing more technology with TSVs. It’s a 2.5D solution.

SemiMD: Is it really just packaging?
Radojcic: We spend a lot of time thinking about this. To call it packaging technology is misleading. You are going to use TSVs and TSS (through-silicon stacking) only if you are going to architect for it. You can’t just take two existing chips and slap them together. TSVs will cost more. The way you get the value out of it is by including it in the architecture. Wide I/O is an excellent example. You can do wide I/O only with TSS. You can’t do it with wires. It’s more than just packaging. It’s an integration technology.
Subramaniam: I agree. Things you can do in a multi-chip module today you can do with TSVs. But that doesn’t mean it’s the only thing you can do with TSVs.
Radojcic: But if you are trying to do multichip modules with TSVs you’re just creating a more expensive solution. You’re only going to do things with TSVs that you cannot do with multichip modules.

SemiMD: Are the design tools there?
White: The EDA industry, in general, is mindful that it needs to solve today’s problems at 28nm and 20nm outside of 3D ICs. At the same time, we also need to be investing in technologies to support 3D ICs. We need to balance our investments between both of those. Most of our efforts have 3D components. The Calibre division is working on solutions for 3D ICs and trying to judge the investment level versus the time when customers will need physical verification models. The EDA tools will come. They may not be out as quickly as some would want, but they will be available to the general market as they are needed. Our plan is to have physical verification tools in place this year.
Hogan: You’ve got to have that. And if you look at Sonics’ technology, the network on chip architecture gives you even more degrees of freedom to do high-level integration and go after performance. I think performance will drive everything.
Radojcic: The value proposition is either performance or power or form factor. But in terms of tools you have to step back and look at the application. If the first application is memory and logic you really don’t need many new tools. You need some standardization in terms of how you move design information from one tool to another. But you don’t need new tools because I’m designing one thing at a time. At some future date will be designing logic-to-logic integration, and then we will truly need new tools. People have been saying for 3D you will have to throw away all your tools. It’s not at all like that. I can design the kind of products people are talking about with a few tweaks. You may need new flows, but not new tools.
White: I agree with that. The approach we’re trying to take is to build upon the existing tools and extend them to deal with the interfaces in a more seamless way to deal with the memory and the logic underneath. You’re currently using scripts to try and deal with those interfaces. We want to connect up the memory physically and electrically with the logic underneath. Over time that will evolve to something more sophisticated where you have logic on logic so you have finer granularity.
Gianfagna: That is the good news. You don’t need to swap out the whole design perspective. A lot of our tools can be extended in a rather straightforward way to 3D design. It’s not trivial, but it is an extension of the existing methodology. It’s not tool retraining. But down the road as you start looking at thermal and mechanical stress, that’s different. You’re looking at placing TSVs that have nothing to do with connectivity. They have to do with heat dissipation. That’s weird, and it gets more difficult as we proceed. But you don’t have to bite it off all at once.
Radojcic: You don’t need new tools in the RTL to GDS II flow. But you do need new tools for exploring the value proposition. We can’t rely on past experience that came from 2D scaling to define a winning vision in 3D. We call that pathfinding. Somewhere at the tail end we will need methodologies and tools to manage the interaction of die for thermal. How do you incorporate that into corners or stress?
Hogan: I think the opportunity is at the architectural level. If I have a wide memory, it gives me more options in terms of implementation. And because we have more degrees of freedom, it gives us more options at the software level.
Subramaniam: You can’t trivialize the tools. You will need significant enhancements in terms of extraction and planning analysis—especially if you are going to do logic on logic. How do you figure out the partitioning, and then how do you model the interconnect between block A and block B? That whole area needs to be studied. And with TSVs in your ASIC you’re going to have islands and blockages that you will have to work around. This will need a lot of R&D.
Wingard: Another problem is how we’re going to share known good die between companies, which is something we’ve been trying to do for years and years. How do people deal with these very thin wafers? For me the big risk is in that area. The second big risk is in the architectural area. When we try to think about partitioning systems, where we have standard interfaces I’m not worried. It’s all the places where we don’t have standard interfaces. Will we have to come up with a new class of standard interfaces or will the way we partition a system across multiple FPGAs be one in which we don’t worry about the I/O because it’s just the I/O? Is that the model we’re going to use? I really don’t think so. How many people can afford to build four logic die and four mask sets instead of one? We’re going to need some standard interfaces.
Radojcic: I agree. You need the architecture first. Then you can worry about physical problems.

Semiconductor Manufacturing & Design examines the myth and reality of 3D stacking–and the hurdles that still need to be solved. In the hot seat: VC Jim Hogan; eSilicon’s Prasad Subramanian; Sonics’ Drew Wingard; Atrenta’s Mike Gianfagna, and Mentor Graphics’ Michael White.