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SPIE Advanced Lithography conference concludes

Friday, February 27th, 2015

By Jeff Dorsch, contributing editor

Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.

Doubts about the continued viability of Moore’s Law abound as the 50th anniversary of Gordon Moore’s historic article for Electronics magazine draws near. Lithographers are under immense industry pressure to lower the operating costs of lithography cells in the fab while increasing wafer throughput.

“Enabling,” “productivity,” and “stability” were watchwords frequently repeated throughout the conference. The various merits (and occasional demerits) of electron-beam, extreme-ultraviolet, 193i immersion and nanoimprint lithography technologies were debated and touted over four days.

One of the technical sessions closing out Wednesday at the San Jose Convention Center was devoted to papers on “Multibeam Lithography,” especially e-beam direct-write technology, which has been seen as “pie in the sky” for many years, yet seems closer to realization than before.

Hans Loeschner of IMS Nanofabrication described how his company’s e-beam tool has progressed from alpha to beta status this year, and predicted it would be ready for production applications in 2016. Altera, CEA-Leti, and MAPPER Lithography presented a total of three papers on MAPPER’s FLX-1200 e-beam direct-write system, saying it is better able to make chips with 20-nanometer features than an immersion lithography system.

The eBeam Initiative held its annual luncheon at SPIE Advanced Lithography on Tuesday, emphasizing how multibeam mask writing, model-based mask data preparation, and complex inverse lithography technology can enable continued density scaling at the 10-nanometer process node.

“We have reached a point with traditional rules-based designs where the rules are so conservative and the implementation costs are so high that the semiconductor industry has started to lose the economic benefits of scaling to smaller design nodes for system-on-chip designs,” D2S CEO Aki Fujimura said in a statement. “A simulation-based approach combining complex ILT, MB-MDP and existing variable shaped beam mask writers in parallel with the impending emergence of multibeam mask writing are providing platforms to enable the semiconductor industry to reverse this trend and reactivate the density benefits associated with Moore’s Law.”

EUV, another technology that has had a long gestation, was the subject of a conference track over all four days, with photomask and photoresist issues being discussed in several sessions.

The news that Taiwan Semiconductor Manufacturing was able to process 1,022 wafers in 24 hours with ASML Holding’s NXE:3300B scanner was the talk of the SPIE conference on Tuesday, the first day of the two-day exhibition, which had about 60 companies occupying booths. ASML didn’t declare an end to development of its EUV systems, saying there is more work to be done. This includes development of a pellicle for the scanner’s reticles and working with resist suppliers on formulas for EUV resists.

While improvements in all types of lithographies were discussed at the conference, there was increased interest in directed self-assembly, which employs polymers to get molecules to arrange themselves in lines and spaces with a patterning guide. Advances in reducing the defectivity of DSA were reported by imec, Merck, and Tokyo Electron.

Global interest in DSA over the past four years has accelerated due to “other things getting delayed,” said Tom Ferry of Synopsys. Among other initiatives, the electronic design automation software and services company was talking about how its S-Litho molecular simulator, S-Litho shape optimizer, and Proteus ILT guide patterning tool can help enable DSA research and development, design, and manufacturing.

The Belgium-based imec was a big contributor to conference presentations, with a first author on 18 papers and posters, and a co-author of 25 publications.

While EUV garnered headlines during SPIE Advanced Lithography, the Cymer subsidiary of ASML was at the conference to talk about its third-generation XLR 700ix light source for deep-ultraviolet lithography systems. Ted Cacouris of Cymer said, “10 nanometer is basically done with DUV. It could go to 7 nanometer; immersion could be extended. It could be complementary to EUV.”

Cymer also announced its DynaPulse program, an upgrade for its OnPulse subscription service for maintenance and repair of light sources. In 2012, prior to the company’s acquisition by ASML, Cymer derived nearly 70 percent of its light-source revenue from the OnPulse service program.

It’s been an interesting week, with about 2,400 attendees from around the world gathering for the premier lithography conference of the year. They will convene again a year from now to learn what’s new in lithography.

Proponents of EUV, immersion lithography face off at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.

Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.

On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.

ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.

While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.

“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”

The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.

Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.

“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.

The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.

Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.

On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”

Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.

Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.

Erik Byers of Micron Technology observed, “EUV is not a panacea.”

Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.

Complexity is the Theme at Lithography Conference

Monday, February 23rd, 2015

By Jeff Dorsch, contributing editor

Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.

“Complexity is much higher,” said Kevin Lucas of Synopsys at the Nikon event, LithoVision 2015. He noted that at the 28nm process node, lithographers could resort to five different options. For 14nm or 16nm, that expanded to eight options. There are 21 options available at 10nm, Lucas said, and at 7nm that explodes to more than 71 options.

“The increase in complexity is pretty dramatic,” he observed.

Electronic design automation vendors have “to provide more accurate modeling,” Lucas said. “We will have to go to better methods of [optical proximity correction].”

Ralph Dammel of EMD Performance Materials reviewed the situation in semiconductor materials as IC gate lengths continue to shrink. “We’re going to move from adding new elements to different forms of elements,” he said, such as graphene, silicine, black phosphorus, and molybdenum disulfide.

At the Lithography Users Forum, the event put on by KLA-Tencor, Mark Phillips of Intel said, “Scaling can continue, but it needs improved metrology.” He added, “We need side-by-side accuracy metrics.”

Phillips reported on Intel’s work with ASML Holding on developing pellicles for the reticles of ASML’s extreme-ultraviolet lithography systems. The companies have together come up with a prototype pellicle, which needs more development as a commercial product, he said.

Changes and Challenges Abound in Multi-patterning Lithography

Monday, January 26th, 2015

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By Jeff Dorsch

Multi-patterning lithography is a fact of life for many chipmakers. Experts in the fields of electronic design automation and lithography address the issues associated with the technology. Providing responses are David Abercrombie, Design for Manufacturing Program Manager, Mentor Graphics; Gary Zhang, Vice President Marketing, ASML Brion; and Dr. Donis Flagello of Nikon Research Corporation of America.

1. What are the significant considerations in semiconductor manufacturing and design with multi-patterning lithography?

David Abercrombie: Like most process/design trade-offs moving from one node to another it comes down to cost vs area and performance. Without multi-patterning or EUV you will struggle do design at 20nm or below limiting the opportunity to take advantage of design area and performance scaling. Essentially, Moore’s Law slows to a crawl without it. Multi-patterning affects almost all aspects of design and manufacturing. For physical design it adds additional design rule constraints and constrains cell placement and routing depending on cell architecture. For electrical design it adds additional parasitic variability to consider in timing analysis. For DFM it adds additional requirements for fill and lithographic checking. In manufacturing it adds additional masks, process steps and increases stepper utilization. All of these increase complexity and have an associated cost. It ultimately has to make business sense. Because of this you are seeing fewer companies moving to these advanced nodes as quickly as before, as they must have the volume and profit margins to justify the increased cost. Fortunately, there are products that do need the newest and most advanced process nodes, and because of those needs we continue to move forward into these new technology nodes on a regular schedule.

Gary Zhang: Multiple patterning (MPT) using immersion lithography is required for the semiconductor industry to continue device scaling until extreme ultraviolet (EUV) comes into full production (EUV is expected for a mid-node insertion in the 10nm logic node, and for 7nm node development and production in the 2015-2017 time frame). Multiple-patterning lithography brings the following new challenges from design to manufacturing. ASML has been collaborating with the chipmakers in a holistic lithography framework to tackle these challenges with innovative hardware and software solutions, including scanner systems, computational lithography, metrology and process control.

Integrated circuit designs have to be multiple patterning compatible. Industry has been developing methods to enable MPT-compatible designs via layout decomposition (coloring) and conflict resolution using multiple patterning rules as constraints. This applies to standard-cell libraries, cell boundaries, and placement and route to ensure full chip layouts meet all manufacturing requirements and can be decomposed into separate masks without any post-coloring MPT conflicts. Structured layouts with highly restricted design rules seem to be a key enabler for MPT-compliant designs.

The rule-based approach to MPT compatible designs tends to run the risk of pattern defects from design hot spots, especially when design rules are pushed aggressively for competitive die size. The lithography process window of these design hot spots can be enlarged using source-mask optimization (SMO). Brion’s Tachyon SMO has been routinely used to co-optimize scanner optics such as illumination source and projection lens wavefront and mask enhancements including sub-resolution assist features (SRAF) and optical proximity correction (OPC) for any given designs. Take triple patterning of a 10nm node metal layer as an example. Tachyon SMO enables a 23% larger process window for the selected SRAM and logic designs (Figure 1). By evaluating a range of design variations, SMO can help optimize design rules and MPT coloring rules to eliminate design hot spots in the technology development stage. For production mask data preparation, Brion’s multiple patterning OPC and LMC (Lithography Manufacturability Check) are widely used by the leading chipmakers to deliver the best full chip process window in wafer manufacturing. A combination of SMO, OPC and LMC makes up ASML’s process window enhancement solutions to the design hot spot problem.

Figure 1. Source-mask optimization (SMO) of a 10 nm node metal layer in triple patterning lithography. Overlapping process window of all three splits (masks) is improved by 23% for selected SRAM and logic patterns imaged with the same illumination setup.

Multiple patterning drives tighter CD, focus and overlay requirements to account for more process variations from the additional processing steps. Overlay is used here as an example to show the increasing complexity in multiple patterning process control from single exposure at 28nm node, to double patterning at 14nm node, to triple patterning at 10nm node (Figure 2). Tighter overlay specification has to be met for the exponentially increasing number of critical masks and metrology steps at 14nm and 10nm nodes. To deliver the required overlay control on product wafers, scanner matching and process control have to include high order corrections (Figure 3). ASML’s latest generation of immersion scanners have a large number of flexible actuators and are capable of sub-3 nm matched-machine overlay, dynamic lens heating and reticle heating corrections, and high-order interfield and intrafield corrections for imaging, focus and overlay.

Figure 2. A comparison of overlay metrology and control for single exposure at 28 nm node, double patterning at 14 nm node and triple patterning at 10 nm node, using the Metal 1 (M1) to Metal 2 (<2) process loop as an example.

Figure 3. On-product overlay roadmap showing the ever tighter specification from 28 nm node to 14 and 10 nm nodes and the requirement of advanced scanner correction capabilities (such as dynamic and high-order).Two different production scenarios are considered, namely scanner/chuck dedication and mix and match of different scanners.

With the introduction of multiple patterning below 28 nm node, the increasing number of masks and metrology steps translates to lower wafer throughput per scanner and longer wafer cycle time from start to finish. This then leads to cost per wafer significantly higher than the historical cost scaling trend from the previous technology nodes. ASML has been continuously driving the scanner innovation to increase the throughput and improve productivity in terms of wafer output per day. ASML’s YieldStar integrated metrology is another innovative solution to reduce wafer cycle time and improve on-product performance for effective productivity gain and overall cost benefit.

In summary, a full suite of design and manufacturing solutions are required to address the new challenges in multiple-patterning lithography. ASML has taken a holistic approach and worked in close collaboration with the chipmakers to optimize design, scanner, mask and process control altogether for the best manufacturability and yield. Figure 4 gives an example on how holistic lithography enables focus roadmap down to 1x nm node. In the design phase, process window enhancement solutions such as SMO, OPC and LMC are used to eliminate the design hot spots and maximize the full chip process window. In the wafer manufacturing phase, process window control solutions such as scanner matching and high order corrections are implemented to optimize CD, overlay and focus control dynamically from tool to tool, field to field, wafer to wafer and lot to lot. A combination of the largest process window and the tightest process control delivers the most robust manufacturability and yield in volume production.

Figure 4. An example of how holistic lithography enables focus roadmap down to 1x nm node (DPT: double patterning; MPT: multiple patterning). A combination of process window enhancement and process window control solutions delivers robust manufacturability and yield in volume production.

Donis Flagello: Multiple patterning brings a host of issues due to the added complexity associated with imaging and processing multiple patterns within the same design layer. From the exposure tool point of view, we need to ensure that the overall cost of ownership is maintained and the tool can enable further scaling. We are concentrating on many aspects of the technology. One of the most critical is overlay. This must be as low as possible such that the ensemble overlay of all the exposures within a layer is equal or better than a single exposure. Simultaneously, we need to increase the throughput of the tools to ensure that cost per wafer per hour is also continuously improved.  Both of these aspects drive a huge amount of innovation and technology development.

2. How do you deal with color assignment?

Abercrombie: The answer to that depends on the foundry and layer being discussed. Colorless, partial coloring and full coloring flows exist. In colorless flows the designer does not assign colors. There are specialized checks (like odd cycle checks in double patterning) that make sure the layout can be decomposed into multiple masks later once the design is taped-out to the foundry. In a partial coloring flow most of the layout follows the colorless flow, but the designer can manually assigns some parts of the layout to a particular color to manage subtle variation concerns. For instance, making sure matched circuitry also has matched coloring. In a fully colored flow the designer is responsible for producing the final mask assignments for all polygons in the layer. A GDS layer is dedicated to each mask. To assign a polygon to a given mask a copy of it is placed on the appropriate mask color layer. EDA companies provide various automation capabilities to assist with color assignment in custom, P&R and batch full chip applications.

It is best to use an EDA solution like Calibre that not only can address all different coloring flows but also provides the same checks/algorithms for all phases a design goes through from initial IP blocks to final full chip signoff.

Zhang: Layout decomposition or coloring has to deliver split patterns on separate masks which are free of any process rule violations and can then be patterned in single exposure with sufficient process window. A double patterning (DPT) using a litho-etch-litho-etch process is shown as an example (Figure 5). In the DPT coloring step, any non-native color conflicts are resolved in a layer aware implementation with stitches that are properly located away from the overlap region between layers (such as a metal line contacting a via) and have the least impact on the device performance and manufacturing yield. Process robust stitching must have sufficient overlap margin to tolerate misalignment between the exposures of the split masks. This is the concept of overlay aware stitching.

Figure 5. An example of design to manufacturing work flow for a litho-etch-litho-etch double patterning (DPT) process, from layer aware coloring to overlay aware stitching, to model based OPC, to the final contour after litho and etch processes.

Color balancing is another critical care-about in layout decomposition. MPT coloring not only needs to deliver split layouts free of MPT conflicts but also has to ensure the pattern density is balanced between the split masks. Color balancing is beneficial for litho and etch process control so that robust and uniform patterning qualities can be achieved.

Coloring can also be optimized for best process window using a model based approach, as described above in the “Design hot spots” section. Model-based coloring is not suitable for full chip application. It can be either used in source-mask optimization for MPT rule development or applied in local hot spot fix during the mask data preparation.

3. How does design rule check change? How is it the same?

Abercrombie: In a fully colored flow the design rules change slightly. First for every traditional spacing check there are essentially two checks for double patterning (DP): a minimum spacing for different colored polygons, and a larger minimum spacing for same colored polygons. In addition, there are usually additional density checks making sure the ratio between the colors is reasonably equal. In colorless flows specialized new checks have been developed to verify if a valid coloring exists for a given layout construct. In double patterning these specialized checks include odd cycle checks. For triple patterning (TP) and quadruple patterning (QP) new types of checks are required.

Zhang: Triple patterning (TPT) coloring is a lot more difficult and complex than DPT coloring. It is extremely hard to determine if a layout is TPT compatible, known as NP-complete problem in graph theory. There is no efficient way to find a solution on the full chip level. There are no existing methods for determining the number of conflicts and their locations.

Stitches are color-dependent in TPT and candidate stitch locations can be determined only after or during coloring.

Therefore it is important to ensure TPT compliance by design construct.

4. What are the complexities and issues in transitioning from double-patterning to triple-patterning?

Abercrombie: Although checking and decomposing a layout for two colors is complex, the algorithmic processing scales reasonably by design size. However, the generalized solution for triple and quadruple patterning has exponentially increasing run time as the number of polygons processed increases. This is, of course, is not a practical solution. So the problem must be constrained such that reasonable heuristic algorithmic approaches can be applied that provide reasonably scalable run times. So the complete set of design rules and design methodology need to be properly tuned to constrain the graph-complexity of the layouts produced so these checking and decomposition heuristic tools can be utilized. In addition, specialized checks may be needed so that layout constructs that do not meet the complexity constraints can be diverted from processing (to keep run time from exploding) and flagged to the user for modification until they can be properly processed.

The other challenge in moving from DP to TP and QP is colorless error visualization. If you are doing a colorless flow and need to check if the design can legally be colored, you need a way to highlight constructs for which no valid coloring solution exists in a way that the designer can understand so he/she can make changes in the layout to fix it. For DP this was odd cycle error visualization. An even-numbered cycle of interacting polygons can be colored and an odd numbered cycle of interacting polygons cannot. For TP and QP this is not the case. Any simple even or odd cycle can be colored. The constructs which cannot be colored are much more complex than in DP. In addition, narrowing down the implicated constructs to the “root” of the problem is more difficult. To address these issues Mentor Calibre is developing a new array of error visualization layers to help inform and guide the user to appropriate and productive fixes.

Flagello: Years ago many industry observers did not believe that double patterning was viable. Today double and triple patterning is being done. However, there are some key differences between the two. Depending on the technology used, double exposure from a tool perspective is more or less straightforward. Mask alignment is usually based on the previous layer mark. However, moving to triple exposure often results in much more of an optimization problem to determine the best alignment strategy. Sometimes, the previous layer alignment mark may have a poor signal depending on the number of films involved in the multiple-patterning schemes. While increasing the number of patterning steps increases some of the complexity, the solutions become more of an optimization and controls challenge.

5. What issues in IC design and verification emerge with multi-patterning?

Abercrombie: The designer should expect to see new design rules, more parasitic variation, more complexity in design and methodology constraints, increased wafer cost, and the need for new EDA tools and additional CPU hardware to process their designs. This is really not new as this increased complexity and cost has existed between every node transition. The difference is that the delta may be more than between previous nodes. It is important that design teams educate themselves early on the impacts of moving to multi-patterned process nodes. That includes getting information from the foundry and EDA partners as well as reading available material on the subject. I have a whole series of articles covering much of the questions in this round table in significant detail: http://www.mentor.com/solutions/foundry/solutions/multi-patterning

Zhang: In addition to the power, performance and area metrics, designers now have to ensure their IC designs are MPT compliant and free of design hot spots so that they can be manufactured cost effectively with the best yield using multiple-patterning lithography. From lithography point of view, design hot spots are the major yield detractor. Device performance such as RC timing delay, cross talk, leakage (such as IDDQ), breakdown voltage and final yield is heavily influenced by MPT process variations. Brion’s LMC has been used to evaluate the impact of realistic dose, focus, mask and overlay variations on MPT hot spots both intra-layer and interlayer. Identification of such MPT hot spots helps drive design and OPC improvements so that they can be eliminated in wafer manufacturing.

Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

Solid State Watch: September 12-18, 2014

Monday, September 22nd, 2014
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ASML on EUV: Available at 10nm

Wednesday, September 17th, 2014

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By Jeff Dorsch, contributing editor

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Giving the keynote presentation Tuesday at the SPIE Photomask Technology conference in Monterey, Calif., Martin offered a lengthy update on his company’s progress with EUV technology.

Sources for the next-generation lithography systems are now able to produce 77 watts of power, and ASML is shooting for 81W by the end of 2014, Martin said.

The power figure is significant since it indicates how many wafers the litho system can process, a key milestone in EUV’s progress toward becoming a volume manufacturing technology. With an 80W power source, ASML’s EUV systems could turn out 800 wafers a day, he noted.

The goal is to get to 1,000 wafers per day. ASML has lately taken to specifying throughput rates in daily production, not wafers per hour, since many wafer fabs are running nearly all the time at present.

ASML’s overarching goal is providing “affordable scaling,” Martin asserted, through what he called “holistic lithography.” This involves both immersion litho scanners and EUV machines, he said.

Martin offered a product roadmap over the next four years, concluding with manufacturing of semiconductors with 7nm features in 2018.

The ASML president acknowledged that the development of EUV has been halting over the years, while asserting that his company has made “major progress” with EUV. He said the EUV program represented “a grinding project, going on for 10 years.”

For all of EUV’s complications and travails, “nothing is impossible,” Martin told a packed auditorium at the Monterey Conference Center.

With many producers of photomasks in attendance at the conference, Martin promised, “We are not planning to make a significant change in mask infrastructure” for EUV. He added, “What you are investing today will be useful next year, and the year after that.”

Blog review August 18, 2014

Monday, August 18th, 2014

Vivek Bakshi provides a deeper look at the ASML/IBM announcement on EUV progress. ASML and IBM reconfirmed the benchmarking in press and via social media. In short, 637 wafers per day throughput stands, resulting from the successful upgrade of source power by 100%, to its targeted level of ~43 W.

Dick James of Chipworks finally has his hands on Samsung’s V-NAND vertical flash. The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

Phil Garrou provides an overview of controlling warpage in packaging as discussed at ECTC by Hitachi Chemical, Amkor, Qualcomm, and imec.

Anand Sundaram, Senior Associate for PwC’s PRTM Management Consulting writes that software that controls and powers embedded devices is playing a key role in making possible the highly integrated, multi-functional ‘smart’ devices we take for granted in our daily lives – from the ubiquitous smart phones/tablet to ‘smart’ home appliances and wearable electronics.

Pete Singer posted an IoT infographic, courtesy of Jabil. The global IoT market is poised for explosive growth. By 2020, the market is expected to soar to $7.1 trillion. This infographic, courtesy of Jabil, gives an good overview of what will be connected (even garbage bins!).

Bob Smith, Senior Vice President of Marketing and Business Development, Uniquify blogs that these days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces.

A New Era for Equipment Suppliers

Saturday, September 1st, 2012

By Pete Singer

The semiconductor equipment industry received quite a jolt recently. In July, lithography equipment supplier ASML announced a customer co-investment program that enabled minority equity investments in ASML (up to 25% total) by its largest customers. Customers could also make commitments to fund ASML’s research and development (R&D) spending for future programs.

Intel was the first investor, acquiring 15% equity ownership interest in ASML. R&D funding and equity investment agreements totaled approximately $4.1 billion. Part of the deal was a contractual commitment from Intel for advance purchase orders for 450 mm and EUV development and production tools from ASML. ASML has said the results of the technology investments will be available to every semiconductor manufacturer with no restrictions.

In August, TSMC joined in, taking a 5% stake in ASML, worth about $1.04 billion. TSMC also committed about $341 million, spread over 5 years, to ASML’s R&D programs.

The Intel announcement made instant believers out of many that both EUV and 450mm would actually happen. Both technologies have been significantly delayed beyond initial target dates, and the thinking was that some massive investment would be required to get them production-ready in a reasonable timeframe (i.e,. 2015-2020). $5+ billion is a pretty good start!

Not only does it seem to ensure that EUV will succeed, but it removed one of the most significant barriers to 450mm development. Even if 450mm solutions were developed for all the other types of process equipment — deposition, etch, ion implant, CMP, cleaning, etc. — it would be going nowhere without EUV. Now, seemingly overnight, 450mm seems inevitable.

It is a new era for semiconductor manufacturing equipment suppliers, for they must now seriously tackle the 450mm challenge, but don’t expect a blossoming new model based on customer co-investments anytime soon. There are at least two competitors in other markets, and developments will likely be funded the way they always have been — though good old-fashioned capitalism.