By Mark LaPedus

Taking another shot to displace ARM, Intel recently rolled out its new microarchitecture for its Atom processor line. In a research note, Will Strauss, president of Forward Concepts, said: “How many times have we heard Intel say that its next member of the Atom processor line would finally be competitive with low-power ARM implementations? Every other year, Intel carts out a new variant that will ‘finally’ do the trick.  The next (and fourth?) iteration of the family, code named Merrifield is said to be the ‘turning point’ for the company in mobile phones.  Although the 2012 launch of Medfield-based 3G phones came close, it didn’t put a dent in ARM’s market share. Merrifield will ship in 4Q13 and phones based on the SoC will be announced at MWC in February 2014. But, the application processor is only part of the solution for a successful smartphone chip offering.  Multimode LTE modems and LTE RF transceivers are also necessary.  Yes, the Infineon-heritage RF transceivers have been fielded in Motorola LTE smartphones, but we’re still waiting for Intel’s multimode LTE modem.  It’s our understanding that the Infineon-heritage multimode 2G/3G/HSPA+ (based on CEVA’s DSP cores) will be married to the Blue Wonder-heritage single-mode LTE (based on Tensilica’s DSP cores). Since the software between the two is not compatible, we expect that has led to integration problems and subsequent delays.”

Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast. In 2012, the IC market fell 2.2%, according to the research firm. Mike Splinter, chairman and CEO of Applied Materials, presents his forecast.

In its most recent quarter, Applied Materials generated orders of $2.27 billion, up 7%t from the prior period, with Silicon Systems Group orders up 14% from the first quarter and Display orders up 41% sequentially. Net sales were $1.97 billion, up 25% sequentially.

At SEMI’s recent Silicon Valley Lunch Forum, speakers from Applied Materials, ASML, and Intel discussed the critical challenges of 450mm and EUV.

The infrastructure in Saratoga, N.Y. can’t keep pace with the growth. One local government organization, the Saratoga County Industrial Development Agency, voted to consider issuing GlobalFoundries nearly $70 million in bonds to finance the infrastructure, according to The Saratogian.

Three companies announced RF switches based on SOI or a variant of the technology. Skyworks rolled out some new parts. Peregrine announced a product for harsh environments. And RDA’s RF switches are being used in Samsung’s smartphones.

Mentor Graphics announced that MagnaChip Semiconductor has adopted the Pyxis custom IC design platform and the Mentor process design kit (PDK) automation process.  Mentor Graphics also announced that CNH, a supplier of agricultural and construction equipment, has transitioned to the latest VeSys software platform.

Cadence Design Systems announced that it helped Yamaha reduce power consumption for its mobile consumer chips with characterization tools.

Is TranSwitch on the block? The communications chip maker has retained Needham & Co. as financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Altera has signed a definitive merger agreement to acquire Enpirion, a provider of high-efficiency, integrated power conversion products known as power SoCs (power system-on-chips).

The use of Wi-Fi functionality in small-cell base stations will be a game changer for cellphone service providers, according to IHS.

Android and iOS, the number one and number two ranked smartphone operating systems (OS) worldwide, combined for 92.3% of all smartphone shipments during the first quarter of 2013 (1Q13) as Windows Phone crept past BlackBerry for 3rd place, according to IDC.

By Mark LaPedus
After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility.

The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a little less than five years to develop the production tools for 450mm fabs, which are expected to cost a whopping $10 billion or more. Based in Albany, N.Y., the G450C has five members—GlobalFoundries, Intel, IBM, Samsung and TSMC.

But between now and 2018, there is a staggering amount of work to be done. Based on the current progress for select equipment, fab technologies and standards, the path towards 450mm will be a bumpy road and it’s unclear if the industry can meet the 2018 target.

The most obvious problem is lithography. For example, ASML Holding is not expected to deliver a production-worthy, 450mm version of its extreme ultraviolet (EUV) lithography scanner until 2018. Other challenges include lithographic cost-of-ownership and throughput.

On the wafer-processing front, Applied, Lam, TEL and others are moving full speed ahead in 450mm. TEL also is proposing an “open platform” standard—a move that has received a lukewarm response. Meanwhile, there is some movement in metrology, as a new consortium has recently been formed to address the challenges in 450mm.

And the industry is still debating over various 450mm fab standards, such as aisle space and ceiling height. There is even a debate over the type of cranes needed to install 450mm tools. Other standards, such as gas interface boxes, cooling water manifolds, and hookups for power, are also in the works.

That’s just the tip of the iceberg. The goal for the G450C is not only to help develop these technologies, but it also has the arduous task of getting the various players to synchronize on the roadmap. “It’s going to require a collaborative and concerted effort to introduce (450mm technology) in an efficient manner,” said Steve Johnston, director of external programs and technology strategy in the Technology Manufacturing Engineering Group at Intel, at a recent SEMI event. “All of this requires flawless and synchronized execution across the industry and at multiple levels.”

Avoiding past mistakes
Indeed, the industry hopes to avoid past mistakes. In the mid-1990s, the IC industry wanted to make the shift from 200mm to 300mm fabs. The equipment industry had the 300mm tools ready in the late 1990s, but chipmakers pushed out their 300mm fabs amid an IC downturn. Equipment vendors ended up holding the bag and lost a fortune. Shortly thereafter, chipmakers began to ramp up their 300mm fabs, but the events left a bad taste in vendors’ mouths.

Recently, Intel, Samsung and TSMC have been pushing for 450mm fabs. The argument is that the industry needs to make a wafer transition every 15 years to stay on Moore’s Law. Moving to 450mm wafers will give chipmakers a 2.25x boost in wafer area and a 30% cost reduction, according to chipmakers.

For some time, however, fab tool vendors were lukewarm about 450mm. There are only a handful of customers who would buy 450mm tools, and it’s unclear who will foot the R&D bill for the technology.

More recently, 450mm has become a reality. Intel and TSMC have outlined plans to build 450mm fabs. And in 2011, the G450C was established at the College of Nanoscale Science and Engineering’s NanoTech Complex. The G450C recently opened a cleanroom. Its roadmap also calls for 450mm pilot lines in 2015 and 2016, with high-volume production targeted for 2018.

“Synchronization and collaboration are very important to avoid the same type of issues we ran into in the late 1990s with the transition to 300mm,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials.

There are other issues, namely supply-chain readiness, return-on-investment and R&D funding. “The (R&D funding) issue requires a very different business model,” Hasserjian said. “That has not been completely resolved. We have the consortium activities, which have provided some level of funding.”

Fab tool challenges
The industry has moved to fund at least one technology, namely lithography. Intel, Samsung and TSMC recently invested in ASML, in an effort to accelerate ASML’s efforts in 450mm and EUV. And with separate funding from Intel, Nikon is developing a 193nm immersion scanner for 450mm.

ASML itself has initiated 450mm programs on two separate platforms and four wavelengths, including EUV. The goal is to deliver “early version tools” in 2015 to 2016, with 450mm production systems due out by 2018, said Jim Koonmen, general manager of Brion Technologies, a division of ASML.

The development of a 450mm EUV scanner is expected to be a herculean effort. Today, ASML is struggling to deliver 300mm EUV tools amid delays with the power sources. Cost is also an issue, as ASML’s pre-production EUV scanners cost $100 million or more per unit today.

Throughput is also an issue. The throughput for a 450mm scanner in general is projected to be only about one-half of a 300mm tool, Koonmen said. A 300mm tool has a throughput of about 250 wafers per hour (wph), while a 450mm system can run 100-125 wph at 1.1x the cost, he said.

“If you look at the entire semiconductor process, there are steps that do get a lot of leverage from larger wafer sizes and can realize cost reduction,” he said. “Unfortunately, with lithography, there simply isn’t that much of a benefit in going to larger wafer sizes. We are scanning as fast as we can. The number of fields is going to increase when we go to larger wafers, but that just means your throughput for each 450mm wafer is going to go down. So you’ve got double the number of fields, but you are going at half the throughput. That in itself is not easy to do. In order to handle a 450mm wafer, you need to have larger stages with larger masks, and that creates a whole bunch of issues for us.”

Meanwhile, amid the problems with EUV, the industry is hedging its bets by developing 193nm immersion scanners for 450mm. Optical is a proven technology, but the solution is expensive. At 10nm or 7nm, chipmakers must also use expensive multiple patterning schemes.

Delivery schedules for 193nm immersion are more certain, however. “450mm is expected to be in production by 2018,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “We will ship development tools earlier than that.” By 2015, Nikon plans to ship “early learning tools” based on 193nm immersion for 450mm, Zarringhalam said. Nikon has already garnered “multiple orders” for the systems, he added.

On the wafer processing side, there are also some technical and cost challenges. “Prices could rise 30% to 50% for 450mm tools, as they did when the wafer size shifted to 300mm from 200mm,” said analyst David Motozo Rubenstein, who is also the author of a blog entitled “Chips and Dips.”

Applied, Lam, TEL and others are developing standalone 450mm tools. TEL also is proposing the idea of having an “open and modular platform” for 450mm. This would enable fab tool vendors to develop various plug-and-play process modules for the open platform, thereby reducing costs and development times. TEL and its rivals could develop modules for the platform. “The open platform is a concept for the 450mm high-volume manufacturing era,” said Aki Sekiguchi, vice president and general manager for SPE marketing at TEL.

The open platform could benefit smaller companies that don’t have the resources to develop standalone tools. But larger companies are not eager to endorse an open platform, because it will give its rivals a competitive edge. “We are looking at it,” said Applied’s Hasserjian. “We are not doing what TEL is doing and advocating a modular platform.”

Metrology challenges

Another challenge is the development of 450mm metrology gear. “There are not many companies that can invest six years in advance,” said Menachem Shoval, chairman of Metro450, an Israeli-based consortium that is developing 450mm metrology technology. “Even without going 450mm, there are huge challenges for metrology in terms of going down from 22nm to 14nm to 10nm to 7nm.”

This is especially true when moving from today’s planar devices to finFETs at 22nm and beyond. “Going to 3D has created numerous challenges for us,” said John Allgair, senior member of the technical staff at GlobalFoundries. “We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.”

One solution to the problem is to collaborate through a consortium, Metro450′s Shoval said. Last year, for example, the Metro450 consortium was formed by the following companies—Applied Materials, Nova, Jordan Valley, Nanomotion and Intel. The group also consists of four universities in Israel, with some 60% of the funding coming from the Israeli government.

“Each company develops its own technology,” Shoval said. “They are competing with each other. But we can collaborate on those parts which are common. We will work on platforms, but not on detection.”

One of the goals for the Metro450 group is to meet the design rule targets by 2017. It is also devising technologies that are 2.5x faster than 300mm, thereby meeting the cost requirements for 450mm. To reach its goals, the group is working on five specific technologies: wafer handling; sampling optimization; wafer damage and contamination; calibration; and data processing.

“We plan to complete our work in three years,” Shoval said. “So companies will still have about three years to complete the development of their high-volume manufacturing tools.”

By Mark LaPedus
Japan’s Ushio will discontinue its R&D for EUV light sources and will sell its EUV service business to ASML. That means the market has only two EUV source vendors—ASML’s Cymer unit and Gigaphoton. “Ushio’s subsidiary, Xtreme Technologies, competes with Cymer, which was recently acquired by ASML, thus symbolizing an endorsement of Cymer’s EUV technology. Ushio will gain cost savings in both fixed costs and variable costs as 30 staff in their German facility will be shifted under ASML’s umbrella. Although the termination of this business is disappointing, it does reduce future risk of high R&D costs as well as lowering current costs,” said analyst David Motozo Rubenstein in his blog called Chips and Dips.

Taking another shot to displace ARM in the mobile, tablet and other markets, Intel rolled out its new and long-awaited microarchitecture for its Atom processor line.

SEMI applauded the White House announcement that President Obama decided to visit Applied Materials’ facilities in Austin, Texas. This was part of his focus on manufacturing jobs, high-tech skills and technology that will drive long-term economic growth. The administration’s announcement cited Applied Materials’ contribution to innovation and job creation.

While faced with difficult technology and investment choices in R&D, there is now increased pressure on the component-level supply chain, according to Michael Lercel, director of nanodefectivity and metrology at Sematech, in SEMI’s newsletter.

Worldwide silicon wafer area shipments decreased during the first quarter 2013, when compared to fourth quarter 2012 area shipments according to the SEMI.

KC Ang, senior vice president and general manager of GlobalFoundries Singapore, has been appointed to serve SEMI Singapore Regional Advisory Board (RAB) as their new chairman.

Cadence announced its intent to acquire the IP business of Evatronix, adding to its rapidly expanding IP offering.

Cadence also introduced a new version of Incisive Enterprise Simulator, which improves low-power verification productivity of complex SoCs by 30%.

Mentor Graphics announced availability of the newest tool in the Capital software suite, Capital Harness TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models.

SRC and NIST announced the second phase of the Nanoelectronics Research Initiative (NRI). For this phase, SRC and NIST will provide a combined $5 million in annual funding for three multi-university research centers tasked with demonstrating non-conventional, low-energy technologies that outperform current technologies on critical applications in 10 years and beyond.

On the outside, the U.S. and South Korean versions of Samsung Electronics’ Galaxy S4 smartphone look alike. But on the inside, there are differences in key components, according to IHS. Global shipments of solid state drives (SSD) in PCs are set to rise by a factor of seven by 2017, allowing them to claim more than one-third of the market for PC storage solutions by that time, according to an IHS.

The high-flying acceleration and sensor product category was brought back to earth in 2012 when price erosion pulled down annual sales growth to 7%—the lowest percentage increase for motion-sensing semiconductors since 2005, according to IC Insights.

After falling 15% in 2012, solar photovoltaic wafer production is forecast to grow 19% in 2013, passing 30 GW and recovering to the 2011 level, according to NPD Solarbuzz. However, industry utilization is expected to remain below 60%.

Natural gas vehicles (NGVs) on the road in the world’s seven largest automobile markets will reach only 7.5 million as the industry struggles to capitalize on cheap shale-driven natural gas, Lux Research said.

By Mark LaPedus
The term carbon footprint seems to be “old hat” and yesterday’s measure of sustainability. “Sustainable development” is the new term. But what is it and can someone please define it? The recent European Coatings Show provided a clue, according to Lux.

For years, smart watches have failed to take off for one reason or another: they looked ugly, had weak functionality, or the battery life was lousy, according to ABI Research. However, a new collection of smart watches have emerged that could change consumers’ perceptions. Market intelligence firm ABI Research projects more than 1.2 million smart watches will be shipped in 2013.

Intel announced its results and cut its CapEx by $1 billion from $13 billion to $12 billion. Hans Mosesmann, an analyst with Raymond James, made the following observations: “With smartphones/tablets not contributing much for Intel in 2013 and the foundry growth vector still 2-3 years from being a real business, Intel is, in our view, quite vulnerable. The hope is for a datacenter recovery as an offset in 2H13 – we’ll see. Interestingly, Intel indicated in relation to its foundry strategy that it would not enable competitors that license ARM processor technology. Outside of programmable logic devices (PLDs), isn’t everybody of significance already using ARM?”

For total fab spending, GlobalFoundries plans to spend $4.4 billion this year to expand production as demand for smartphones and tablets jumps, according to Bloomberg. The spending compares with $3.8 billion last year.

TSMC raised its capital spending. Spending will be $9.5 billion to $10 billion, compared to an earlier forecast of $9 billion, according to Bloomberg. TSMC is accelerating its 20nm and finFET production.

In a blog, Applied Materials said it has recently completed the electrical characterization of through-silicon via (TSV) structures. This development is important because TSVs are the vertical interconnections that carry power and high-bandwidth speed signals between the stacked die of layered logic and memory devices.

Recently, more than 270 students from National Tsing Hua University in Hsinchu, Taiwan, crowded into the campus auditorium to hear Mike Splinter, chairman and CEO, of Applied Materials, to deliver a talk. The Applied Materials CEO told students to follow their passion.

Soitec’s solar unit has completed a debt financing plan for its Touwsrivier project in South Africa.

Soitec announced consolidated sales of 72.7 million euros for the fourth quarter, down 9.3% on a yearly basis. On a sequential basis, Q4 electronic sales were up by 19.1%.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.14 in March, up from 1.10 from April, according to SEMI. id=highlights

Mentor Graphics announced the opening of a new Mentor-sponsored electronics design laboratory at The University of Nottingham Ningbo China (UNNC), based in the Zhejiang province. Mentor has donated more than $10 million in EDA software and support to enable UNNC students to graduate with in-depth knowledge of leading-edge design methodologies.

ASML announced its results and said the contract of Eric Meurice, president and CEO, ends next year. As of July 1, ASML’s leadership will be comprised as follows: Peter Wennink, ASML’s CFO, will be president and CEO; Martin van den Brink, ASML’s executive vice president, will be president and chief technology officer. Meurice will be chairman of ASML and act as adviser to the new leadership and the supervisory board until the end of his contract on March 31, 2014.

Intermolecular has entered into a multi-year technology development and IP licensing agreement with Micron Technology, focused on technology development and related IP for advanced memory technologies. Intermolecular has been working on DRAM technology with Elpida, which is being acquired by Micron. Now, with Micron, Intermolecular is expanding into the nonvolatile memory front with the memory maker, said Dave Lazovsky, president and CEO of Intermolecular. “New materials and device architectures are increasingly needed to meet future embedded and mobile technology requirements, and partnering with Micron in this area is a significant milestone for Intermolecular,” he said.

Tessera has named Richard Hill as interim chief executive and executive chairman of the board. Hill replaces former president and CEO Robert Young, who has decided to step down amid pressure from an investment firm.

Altera has agreed to acquire TPACK, a subsidiary of Applied Micro Circuits Corp. TPACK delivers FPGA-based optical transport network products targeting packet and optical networking equipment suppliers.

”According to Dow Jones VentureWire and other news reports, Avago has reached a deal to acquire Javelin Semiconductor, a manufacturer of CMOS power amplifiers (PAs) which services the mobile market,” said Doug Freedman, an analyst with RBC Capital Markets.

Netronome has raised $19 million in series E and related financing from Sourcefire, Intel Capital and existing investors DFJ Esprit and the Raptor Group. The company is making a next-generation flow processor line, the NFP-6xxx, which is built using Intel’s 22nm tri-gate technology.

Smartphones are forecast to account for 26% of the $30.0 billion NAND flash memory market in 2013. The NAND flash market is forecast to grow 12% in 2013, from $26.8 billion in 2012, according to IC Insights.

By Mark LaPedus
Has Apple finally hit the wall after years of sizzling growth? “Relatively soft sales of large-format iPads and iPhones are likely to drive FQ2 revenue to $41.1 billion and FQ3 revenue to $33.5 billion, both of which are below the Street estimates of $42.8 billion and $40.0 billion, respectively,” according to a research note from Pacific Crest Securities. “Among them, we consider the reduction to our large-format iPad estimates to be the most significant, as this appears likely to be a sustained trend as tablet demand shifts to smaller and less expensive models. The shifts to our iPhone estimates are largely related to the product cycle, which we consider to be a transitory issue. However, we continue to believe sell-through evidence supports our view that the high end of the smartphone market is quickly becoming saturated.”

The semiconductor equipment market continues to consolidate. Hitachi High-Technologies has completed its acquisition of SII NanoTechnology from Seiko Instruments. SII, a supplier of photomask repair tools, has been placed into a new subsidiary called Hitachi High-Tech Science. The move also propels Hitachi High-Tech into the mask repair equipment business.

The European Commission is funding yet another 450mm program. The project, called Enable450, includes Intel and fab tool vendors. It is aimed at 450mm wafer processing, specifically targeting European material and equipment companies. The group also consists of U.S. tool vendors, as well. ASM International is the coordinator of the group. Other members are Applied Materials Israel, ASML, CEA-LETI, Fraunhofer, Future Horizons, IMEC, RECIF, SEMI, Soitec, among others. At present, there is no news to report beyond the formation of this group. Stay tuned.

IC Insights has released its top-50 semiconductor supplier rankings. In the rankings, Qualcomm registered a 34% surge in sales and moved up three positions to replace TI as the fourth-largest semiconductor supplier in 2012. GlobalFoundries registered better than 30% growth last year, moving from 21st place in the rankings in 2011 to 15th last year.

Taiwan DRAM maker ProMOS Technologies has agreed to sell its 300mm wafer fab and equipment to GlobalFoundries, according to Reuters.

Peregrine Semiconductor has filed a new suit, alleging the infringement of its RF silicon-on-insulator (SOI) technology by RF Micro Devices. This new legal action is in addition to an existing suit filed by Peregrine against RFMD in February 2012. That case is still pending.

In a blog, Applied Materials’ venture capital arm discusses the lessons it has learned to ensure the mutual success of a startup company and a corporate investor.

In another blog, Applied Materials talks about the evolution of the semiconductor service model. Instead of just repairing the equipment as in the past model, the new idea is to make fab tools work better, with higher output and lower cost of ownership.

SEMI Europe honored four industry leaders for their accomplishments in developing standards for the photovoltaics (PV) industry. The SEMI Standards awards were recently announced at the SEMI PV Fab Manager Forum 2013.

Why is there a need for “best practices” in mixed-signal SoC verification, and what are some of those practices? Cadence provides some insights in a video.

Mentor Graphics said that its FloEFD computational fluid dynamics (CFD) simulation solution helped Skeleton Bobsleigh World Championship winner Shelley Rudman of Great Britain to her first world championship win on Feb. 1 in St. Moritz, Switzerland.

Analog Devices announced that CEO Jerald Fishman passed away suddenly from an apparent heart attack. ADI President Vincent Roche has been appointed CEO on an interim basis by ADI’s board. In a research note, Doug Freedman, an analyst with RBC, said: ”If Jerry Fishman did not touch your life personally, his work and that of ADI have surely touched your life. I had the pleasure of competing against ADI for 12 years, and writing investment research about ADI for another 11 years. While Jerry was given a great company to run he did so much more than could be expected. ADI has been the envy of the analog IC industry for as long as I can remember. In Silicon Valley, we watched ADI build and maintain a data convertor and amplifier franchise that is unmatched in our industry. All the while, competitors tried extremely hard to take away the market share ADI had, and at every turn Jerry, and his east coast based team, turned away the efforts from Silicon Valley and Texas. In one instance, a competitor hired a team of engineers away from ADI and was able to get a foot hold into a market. Jerry fought back and won, not just in the market but in the courts having found patents that were violated. The far reaching impact of Jerry and the work at ADI is being felt in the areas of driver safety, medical imaging, and mobile communication (none of which would be as advanced as they are today without Jerry and his team of analog engineers). In recent years he had turned his attention on making the best better, not just technically but financially. The path he sought was always clear and easy to see, for all those that wished to follow him. I always enjoyed my interactions with him and will miss his conviction, thoughts and guidance. Jerry, Your legacy lives on in your family and ADI.”

China’s move to corner the market for rare-earth minerals (REMs) has prompted manufacturers of low-voltage industrial motors to adopt alternative technologies that reduce or eliminate the use of these materials, spurring new growth in the motors market, according to IHS.

By Mark LaPedus
Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning.

Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition. As before, with perhaps a slightly different twist, the candidates are EUV, multi-beam and the old standby, 193nm immersion with multiple patterning.

The same candidates also are competing for next-generation DRAM and NAND production. Nanoimprint is vying for a spot in NAND. But another option, directed self-assembly (DSA), could change the entire landscape if chipmakers can bring the technology from the lab to the fab.

Based on the delays with EUV, chipmakers could end up using 193nm with multiple patterning at 7nm. But they also are shuddering at the thought, as the costs and complexities for multiple patterning are enormous.

At 7nm, IC makers would prefer to use EUV or maskless for the critical or cut layers. But after a series of ongoing delays with these next-generation lithography (NGL) candidates, lithographers clearly are frustrated and beginning to run out of patience. “I am not happy with the progress of EUV,” said Burn Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). “I am also not happy with the progress of maskless, but it is making progress.”

Lin, considered the father of immersion lithography, is the industry’s biggest proponent for multi-beam e-beam. In addition, TSMC has installed an EUV scanner and recently invested in ASML to jumpstart technology. Intel and Samsung also have invested in ASML.

EUV or bust?
For now, chipmakers hope to put EUV in pilot production at the 10nm logic and next-generation memory nodes. At 7nm, EUV remains the leading NGL candidate, with maskless running a distant second. TSMC still has EUV and maskless running neck-and-neck, although both technologies could be used in production for different applications.

To date, the progress with EUV is mixed. ASML Holding’s production-worthy EUV scanner, the NXE:3300B, is ready to roll. The scanner has a numerical aperture (NA) of 0.33 and a resolution of 22nm (half-pitch). ASML plans to ship the first NXE:3300B in the second quarter of 2013, but the throughputs are far less than previously advertised.

The throughput issues are due to the source, which is being developed by Cymer. The development of the EUV source has been “more difficult than what we anticipated,” said David Brandt, senior director of EUV marketing and business development at Cymer, which recently was acquired by ASML.

Last year, Cymer promised to ship a 100 Watt source by the end of 2012. So far, in the lab, Cymer has demonstrated the ability to generate 40 Watts and 50 Watts of EUV power. A 55 Watt source translates to an EUV throughput of 43 wafers an hour.

Cymer’s EUV source is based on laser-produced plasma (LPP) technology. In LPP, plasma is generated by a laser pulse hitting a target. The source also makes use of a pre-pulse laser and a master-oscillator power amplifier (MOPA), which will help generate more EUV power.

By the end of 2013, Cymer hopes to ship an 80 Watt source with a MOPA upgrade, enabling an EUV throughput of 58 wafers per hour. By 2015, ASML hopes to ship an EUV scanner with a 250 Watt source, which translates to a throughput of 126 wafers an hour.

Two other vendors, Gigaphoton and Xtreme, are racing against Cymer to deliver a 250 Watt EUV source. So far, Gigaphoton has achieved an EUV light output equivalent to a maximum of 20 Watts, said Yuji Minegishi, manager of the sales division for the company.

By 2015 or so, the IC industry is expected to be at the 10nm node. EUV is a 13.5nm wavelength technology, meaning chipmakers must use multiple pattering with EUV. With self-aligned double patterning (SADP), ASML’s NXE:3300B has demonstrated resolutions down to 9nm.

But if EUV is used in conjunction with double patterning, the EUV scanner itself will require twice the source power than before—or about 500 Watts, contends TSMC’s Lin. However, to deal with the resists, Yan Borodovsky, a senior fellow and director of advanced lithography at Intel, recently said that EUV source power needs to be in the range of 1,000 Watts.

Another way to extend EUV is by moving to higher NAs. For example, with an NA of 0.45, an EUV scanner can print 9.5nm feature sizes, but the image contrast drops, according to Zeiss. To address that problem, the current 4X magnification scheme can be increased to 6X or 8X.

Current EUV scanners with 4X magnification support standard 6-inch photomasks. A 0.45 NA lens with 6X magnification may improve EUV resolutions, but in some cases, that solution may require the photomask industry to move to a new and larger 9-inch mask size. In other words, photomask tool makers must develop new equipment.

“I don’t think we should give up on 4X just yet,” said Harry Levinson, senior fellow and manager of strategic lithography technology at GlobalFoundries, at the recent SPIE conference. “We may be able to extend 4X a bit. Maybe for a later node, we can go for more of these radical changes, such as larger format masks and higher lens reductions.”

Still, Levinson urged the industry to explore the idea of moving toward 9-inch masks, a move that is less painful than some might think. To support 9-inch reticles, the optics and other critical parts of a photomask tool will not need to be re-engineered, but vendors will need to develop new handling systems, he said.

In another scenario, EUV with 8X magnification could support 6-inch masks, but scanning would be done in a smaller field size. “You put this all together and we get less than half the throughput at 8X than 4X,” he said. “This is not an attractive situation.”

Beam me up
Amazingly, multi-beam e-beam or maskless lithography has seen more delays than EUV. Summarizing the state of multi-beam, Serge Tedesco, lithography program manager at CEA-Leti, said: “It’s a shame. There is a lack of support from the industry, when you compare it to the EUV side. This is one of the reasons why the technology is not mature yet.”

In 2002, for example, Mapper Lithography claimed that within three years it would ship its 13,000-beam tool for the 45nm node. As it turned out, Mapper’s initial production tool, which only will consist of 1,300 beams, won’t ship until the end of 2013.

Two other vendors, KLA-Tencor and Multibeam, are separately developing multi-beam tools. In another major move, Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies.

In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena.

In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology. It also is working on a multi-beam tool based on a variant of VSB called multi-shape beam (MSB), said Ines Stolberg, manager of strategic marketing at Vistec Electron Beam.

Given that MSB is based on proven VSB technology, Vistec Electron Beam may have an advantage over rival multi-beam approaches, said Hans Pfeiffer, principal of HCP Consulting. “This has a greater chance for success,” Pfeiffer said.

Multi-beam’s future still remains unclear, as only two entities, CEA-Leti and TSMC, are basically propping up and supporting the entire industry. CEA-Leti recently launched the Imagine Program, a multinational consortium aimed to bring maskless into production.

TSMC is working with both KLA-Tencor and Mapper. For years, KLA-Tencor has been developing what it calls Reflective Electron Beam Lithography (REBL). REBL makes use of a six-wafer rotary stage and a linear column. The 75-100-KeV design also consists of a CMOS-based digital pattern generator module, a 4,096 x 247 pixel array unit that enables more than 1 million beams at full current.

When operating with the rotary stage, REBL has demonstrated the ability to print 120nm half-pitch resolutions, a modest effort at best. In a static mode, the tool demonstrated 28nm resolutions, said Thomas Gubiotti of KLA-Tencor. A high-throughput version of REBL is due out in 2015.

Rival Mapper is developing a multi-beam tool, which is supposed to consist of 13,260 beams with sub-25nm resolutions. However, the first production tool, dubbed the Matrix 1.1, will consist of only 1,300 beams and a throughput of 1 wafer an hour, according to CEA-Leti. In June, CEA-Leti is expected to receive one of the first Matrix 1.1 tools. First exposures for the Matrix 1.1 are slated for the fourth quarter of 2013.

By 2015 or 2016, the overall goal is to cluster 10 Matrix systems together, enabling an overall throughput of 100 wafers an hour. In terms of the cost-of-ownership (COO), the Matrix runs €1 million for a system with a throughput of 2 wafers per hours, €5 million for 10 wafers an hour, and $50 million euros for a 10-cluster unit.

Probing Lithography
The Imperial College London and Ilmenau University of Technology have made some advances in the development of scanning probe lithography. Claiming resolutions down to 5nm and beyond, the technology combines the best of high-resolution scanning probe and nanoimprint lithography.

Sometimes called dip pen lithography, scanning probe lithography utilizes the same nanoprobe used in an atomic force microscope (AFM). The AFM is used to pattern nanometer-scale features. The AFM also enables the direct write of features into calixarene molecular resist. Then, researchers use a confined, development-less resist removal process via emission of low-energy electrons. An AFM post-imaging process is used for final in-situ inspection.

Researchers demonstrated a tiny pattern written in 10nm 4M1AC6 resists, with 40V bias voltage and 30nC/cm line dose. With the technology, scanning probe lithography could be a candidate for the production of finFETs with silicon nanowires at 10nm resolutions.

Figure 1. (a) Development-less, positive-tone closed-loop scanning probe lithography (SPL) on calixarene-based molecular glass resist, using self-actuating, piezoresistive scanning probes. (b) Scanning electron microscopy image of a corner pattern written in 10nm-thick 4M1AC6 resist, with 40V bias voltage and 30nC/cm line dose.4(c) Atomic force microscopy image of lithographic test features written with 30V bias voltage and a line dose of 32nC/cm (broad lines) and 20nC/cm (small lines), respectively. The image was taken directly after lithography with the same cantilever. Source: SPIE

Researchers also see applications in the development of quantum-effect devices, such as single-electron transistors and quantum-dot structures. Using a combination of lithography and material morphology, researchers have fabricated room-temperature single-electron transistors using e-beams and silicon nanocrystals at about 10nm in size.

DSA Hard Drives
Sputtering has been one of the main techniques to enable magnetic media on today’s hard disk drives. The next round of high-capacity drives could be based on an entirely new technology, including bit-patterned media (BPM) or heat-assisted magnetic recording (HAMR).

HGST, formerly Hitachi Global Storage Technologies, continues to explore the development of BPM. Now owned by Western Digital, HGST has combined directed self-assembly (DSA) and nanoimprint lithography to create large areas of dense patterns of magnetic islands at 10nm widths. In partnership with Molecular Imprints, a nanoimprint lithography vendor, HGST has devised dense patterns of magnetic islands in about 100,000 circular tracks.

Self-assembling molecules, called block copolymers, are composed of segments that repel each other. In self-assembly, a pre-pattern or guide is developed. After polymer patterns are created, a process called line doubling is implemented. This makes the tiny features even smaller, creating two separate lines where one existed before.

The patterns are then converted into templates for nanoimprinting. HGST has combined self-assembling molecules, line doubling and nanoimprinting to make rectangular features as small as 10nm in a circular arrangement. When extended to an entire disk, the nanoimprinting process is expected to create more than 1 trillion discrete magnetic islands.

“We made our ultra-small features without using any conventional photolithography,” said Tom Albrecht, an HGST fellow, on the company’s Web site. “With the proper chemistry and surface preparations, we believe this work is extendible to ever-smaller dimensions.”

Pellicle Island
For years, photomask makers have used a pellicle to protect a mask from particle contamination. Used in the production of today’s photomasks in optical lithography, a pellicle is a thin film material that is stretched on a frame.

One of the problems with extreme ultraviolet (EUV) lithography is that the technology lacks a pellicle. This means that particles could invade an EUV mask, thereby disrupting the photomask flow and threatening the overall viability of EUV. In fact, EUV generally requires a defect-free mask to enable the technology.

To solve the problem, ASML Holding has begun the development of pellicles for EUV masks. There are two possible types of pellicles for EUV masks—grid-supported and free standing. ASML is focusing on the free-standing approach, which itself consists of two materials options—polysilicon and a silicon/molybdenum/niobium multilayer. See slide 26 here.

To make the technology viable, an EUV pellicle must have a transmission rate at 90%. At present, ASML has achieved a transmission rate at 87%. In a simulated test, the pellicle was subjected to a 250 Watt source. “The results are promising,” said Luigi Scaccabarozzi, a research scientist at ASML “There was no damage to the (EUV scanner).”

—Mark LaPedus

By Mark LaPedus
Altera has entered into an agreement for the future manufacturing of its FPGAs based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant. That puts the processor giant on a collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC

The Altera-Intel deal could change the landscape in the foundry business, in which Intel will likely become a much bigger player in the arena. But does Intel have staying power to remain in the foundry business? Added John Vinh, an analyst from Pacific Crest Securities: Altera’s “foundry agreement with Intel is exclusive for the foreseeable future. We believe Altera will have exclusive access versus Xilinx at 14nm and effectively have the right of first refusal at 10nm. Strategically, we believe this is likely the most significant aspect of this agreement in that it prevents Xilinx from having access.”

At SPIE, ASML Holding disclosed various milestones with its extreme ultraviolet (EUV) lithography technology. ASML’s EUV production tool, dubbed the NXE:3300B, has demonstrated resolutions of 13nm for lines and spaces and 18nm contact holes. In addition, ASML demonstrated a 40-Watt source with dose control and under good collector protection conditions in six 1-hour runs. It also demonstrated a 55-Watt source in a 1 hour run. But that’s a far cry from the eventual goal. By 2015, ASML hopes to deliver a 250-Watt source for the NXE:3300B, thereby enabling a throughput of 126 wafers an hour.

With the help of self-aligned double patterning (SADP), sometimes called spacer, ASML’s NXE:3300B also demonstrated the ability to print lines and spaces down to 9nm. The work was done in conjunction with ASML, Applied Materials and Imec.

At the International Semiconductor Strategy Symposium in Europe (ISS Europe) on Feb. 24-26, the European semiconductor industry discussed 450mm fabs and other chip topics. In addition, European Commissioner Neelie Kroes floated the idea of creating an “Airbus for chips,” a European initiative for the semiconductor industry comparable to the launch of the Airbus in the aviation industry.

Also at ISS Europe, Malcolm Penn, chairman and CEO of Future Horizons, said that the decline of the major European chip makers has been a result of a defeatist attitude, not necessarily fundamental structural issues. He suggests European chip makers should build a 450mm fab jointly and operate it as a foundry.

SEMI has announced the release of “Global Trade War and Peace: Unified Approaches to a Global Solar Energy Solution,” a white paper containing recommendations to move beyond trade litigation and encourage an accelerated path towards dispute resolution.

In case your calendar has turned into a blur, take note: Semicon is near! SEMI, in collaboration with leading investment groups, has announced the Silicon Innovation Forum (SIF). The forum will bridge funding gaps for new and early-stage companies with manufacturing and technology solutions. SIF will be held in conjunction with Semicon West, on July 9 at the Moscone Center in San Francisco.

At the Mobile World Congress in Barcelona, Peregrine Semiconductor rolled out its latest version of its UltraCMOS process technology, dubbed Semiconductor Technology Platform 8 (STeP8). UltraCMOS is a variant of silicon-on-insulator (SOI) technology called silicon-on-sapphire (SoS).

Also in Spain, Skyworks Solutions said it is ramping several antenna-tuning products with leading smartphone manufacturers. The tuning devices are based on SOI technology.

The RATP Group, the fifth-largest urban transport operator worldwide, has awarded Soitec and Philips/Step an LED lighting contract for its metro and network stations.

Soitec and Medina College of Technology have signed a cooperative agreement for concentrating photovoltaic technology in Saudi Arabia.

GT Advanced Technologies has entered into a development and licensing agreement with Soitec to develop and commercialize a hydride vapor phase epitaxy (HVPE) system for producing GaN template substrates.

Mentor Graphics announced record financial results for the company’s fiscal fourth quarter and year ended Jan. 31.

During a conference call, Walden Rhines, chairman and CEO of Mentor, said the quarter was an all-time revenue and EPS record. Rhines also has a mixed forecast for the overall IC industry in 2013. “For next year, the analysts project mid-single-digit growth, but the general attitude is less positive,” he said.

Mentor Graphics rolled out the Kronos Cell Characterization and Analysis platform.

A blogger discusses Applied Materials, saying the company is at the cyclical trough and its prospects should improve with an increase in equipment spending.

Applied Materials announced that Bob Halliday has been named senior vice president and chief financial officer. Halliday previously was executive vice president and chief financial officer of Varian Semiconductor Equipment Associates prior to Applied’s acquisition of the company in November 2011.

Micron Technology announced the Tokyo District Court’s issuance of an order approving Elpida’s plan of reorganization. Elpida’s plan of reorganization calls for Micron to acquire Elpida. In addition, mixed-signal foundry specialist LFoundry has acquired Micron’s fab in Italy.

Whatever happened to Conexant Systems? The chipmaker recently went private to avoid a takeover. Now, the company this week implemented a restructuring agreement. As part of the plan, Conexant voluntarily filed protection under Chapter 11 of the United States Bankruptcy Code.

Photomask maker Photronics has announced its intent to acquire the shares of its majority-owned Taiwan subsidiary, PSMC.

After a loss and a proxy battle, Aetrium is considering options that may include a sale or other disposition of one or both of its reliability test and test handler product groups.

According to IHS, the competitive landscape of the cell-phone integrated circuits business has completely transformed over the past five years, with Qualcomm and Samsung capitalizing on the rise of smartphones and 4G.

By Mark LaPedus
It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes.

Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC makers will likely use today’s 193nm immersion with multiple patterning at 14nm, 10nm and perhaps beyond. “10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries. “We have evidence that we can do 7nm with immersion.”

GlobalFoundries, for one, is laying the groundwork if EUV is ready by 10nm. “We are keeping our ground rules migrate-able to EUV,” added Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries.

Chipmakers are keeping their options open for good reason—extending optical comes with a penalty. The shift from single patterning at 28nm to multiple patterning at 20nm is projected to increase lithography costs by up to 56%, according to Barclays Capital. Consequently, the overall cost-per-transistor curve is in danger of slowing or derailing.

Lithographers, who seem to achieve miracles when the chips are down, are determined to stay on Moore’s Law. “The cost of processing might go up with multiple patterning, but cost-per-transistor does not,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.

The ability to stay on the critical cost-per-transistor curve puts enormous pressure on the lithographic supply chain, which includes the EDA houses, materials suppliers, mask shops, and tool vendors. In response, Nikon is quietly shipping a faster scanner for 10nm. Lithographers also may resort to some new patterning tricks. The wild card is directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers to enable fine pitches.

EUV woes
For years, there have been fears that optical lithography would run out of gas, prompting the need for a new next-generation lithography (NGL). EUV emerged as the leading NGL candidate. The other NGLs, maskless and nanoimprint, are also in the hunt.

EUV, a soft X-ray using 13.5nm technology, is attractive because it keeps the industry on a single-exposure path. But EUV has encountered several delays due to the lack of adequate power sources, defect-free photomasks and photoresists.

The current throughput for ASML’s EUV tools is less than 10 wafers an hour (wph). At one time, ASML hoped to ship an EUV scanner with a 150-watt source by mid-2012. A 150-watt source equates to a more acceptable throughput of 69 wph.

Recently, the 150-watt source was delayed again and pushed out to mid-2014. The source is being developed by Cymer, which itself is being acquired by ASML. Separately, Intel, Samsung and TSMC have recently invested in ASML to help fund ASML’s efforts in EUV and 450mm.

ASML is still targeting EUV for mass production in 2014, but the industry isn’t taking any chances and will extend 193nm immersion—at a price. On average, there are 37 lithography layers processed for 32nm/28nm chips, according to Barclays. Of those, there are 14 critical layers processed using 193nm immersion scanners.

In total, there are 38 lithography exposures at 32nm/28nm, 15 of which are immersion exposures, with only one multiple patterning step in the flow, according to Barclays. In terms of lithography equipment costs at 32nm/28nm, a foundry spends an estimated $17 million per 1,000 wafer starts per month (wspm).

In comparison, there are 40 lithography layers for at 22nm/20nm chips, 19 of which are critical layers. In total, there are 52 lithography exposures at 22nm/20nm, 31 of which are immersion exposures with 11 multiple patterning steps. All told, a foundry is expected to spend $27 million per 1,000 wspm in lithography costs, according to the firm.

Lithography steps and costs will soar at 14nm and beyond. In response, chipmakers already are prepared for the dreaded multiple patterning era. NAND flash vendors, for example, are using a multiple patterning technique called sidewall image transfer (SIT), sometimes called self-aligned double patterning.

In logic, vendors have or will implement one of the various flavors of multiple patterning: SIT, litho-etch-litho-etch (LELE) or self-aligned vias. Intel, for one, is embracing a concept called complementary lithography, which involves an SIT flow. Other logic vendors are following a similar path with various nuances.

Today, Intel is using 193nm immersion with multiple patterning at 22nm, with plans to extend that to 14nm. At 22nm, Intel’s processors are based on finFETs. “For the 22nm node, our fin is finer than what can be done with simple patterning. It’s done with pitch division. We still stay on an historical cost-per-transistor trend,” said Intel’s Borodovsky. “Our 14nm technology is also pitch-divided technology. We project our cost-per-transistor will remain on the trend.”

For 11nm, Intel is looking at quintuple exposure. As part of the process, there are two steps, gratings and line cuts, to pattern designs. Using 193nm immersion, the first exposure is used to make the gratings. The remaining four exposures are used to cut the pitch-divided lines.

To perform the cut step, Intel is evaluating several options: 193nm immersion; DSA, EUV; or direct-write e-beam. So far, there is no clear winner—193nm immersion is challenging, but DSA, EUV and maskless are not ready for mass production.

“I believe we can extend (193nm immersion) for many years,” Borodovsky said. “We also have a dual wave lithography roadmap. It means we will extend existing technology as long as possible. And we will bring in new technology when it is available and affordable.”

Using NGL has some advantages over optical. “If we use EUV, we will use one mask to do the gratings and another mask to break those continuities. If we use direct write, we don’t use any masks,” he said.

Another technology, DSA, potentially could extend 193nm lithography beyond 10nm. As before, the challenges for DSA are defects and the lack of a design infrastructure. The new gap for DSA is non-destructive metrology as a means to inspect the morphologies in the patterns.

DSA materials providers have said DSA would be ready at 10nm, but there are signs the technology may get pushed out. For example, IBM is targeting DSA for 7nm, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM.

“DSA is making progress,” said Intel’s Borodovsky. “But let’s say we use DSA. If you look at a SEM, you look at the top. Everything may appear perfect. But the cylinders could also change their shapes from top to bottom. You have to have a cross section. So, it’s very difficult to do a cross section of 15nm holes or cylinders. You can do complicated X-ray metrology. For this, you need a synchrotron source, which is not practical.”

Etch is another roadblock. Some of the cylinder morphologies in DSA structures are uniform while others are not. “Some would etch to the bottom. You might also have cylinders that are etched in the wrong place. That’s an edge-placement error,” he added.

The solutions
Until NGL is ready, chipmakers are stuck. “I don’t think the industry has given up on EUV. EUV will be in play, but it will be in limited use,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “But for 10nm, almost all logic vendors are looking at immersion technology. Customers are even looking at extending immersion beyond 10nm.”

To keep up with the increase in multiple patterning steps, ASML and Nikon are shipping faster scanners. Nikon, for one, has begun shipping the NSR-622D, a 193nm immersion scanner for the 10nm node. The tool has a throughput of 200 wph. In addition, Nikon is also developing a separate 193nm immersion tool for the 450mm wafer size.

Besides lithography scanners, there is an urgent need for new and faster e-beams in photomask production. Mask making itself is quickly turning into a fine and precise art. In quadruple patterning, for example, the patterns must be split into four masks.

“One mask has to be perfect in terms of CD uniformity, linearity and defects. The other three masks have to be exactly the same,” said Amitabh Sabharwal, general manager for mask etch products at Applied Materials. “When you start going down to the 16nm node, the CD uniformity targets become very, very tight. We’re talking in the range of 1nm. And on top of that, the defect levels might be very tight. Your systematic uniformity has to be zero. Essentially, everything must be flat.”

Looking into his crystal ball, lithography expert Chris Mack predicts that the industry will embrace new design methodologies such as 1D layouts. “We will see more interaction between lithography and design,” Mack said. “The reality of what we can accomplish lithographically will have more influence on the way designs are implemented. In fact, this might not be a bad thing. The switch from arbitrary designs to more (1D-like layouts) is turning out to have less impact on chip area than many people expected. And they are lithographically friendly.”

The industry also will embrace complementary lithography or hybrid approaches. “There is no doubt in my mind that optical will go forever,” he said. “But I do think there is a possibility of hybrid lithographic approaches that are optimized for specific types of patterns. Complementary lithography is a powerful technique and makes the most sense. All of the (NGLs) have a lot of potential, but they are not being developed in the timeline the industry needs.”

By Katherine Derbyshire
Get ready for 450mm wafers. First seriously considered in 2005, these supersized wafers, along with the equipment to handle, measure, and process them, have gradually made their way to the top of the semiconductor industry’s priority list.

But what exactly does that mean? What will 450mm fabs look like, and how will they differ from the 300-mm fabs being built today?

At first glance, according to Paul Farrar, general managerf of the G450C consortium, not much will change. 300mm fabs brought a major transition, from manual transport of wafer cassettes to automated transport of fully enclosed pods. The twin demands of heavier wafers and a cleaner process environment apply even more strongly now than they did then, and so the basic automation and handling model is unlikely to change.

On the other hand, bigger is still bigger. 450mm wafers will, according to Olaf Kievit of the Dutch research organization TNO, weigh 2.7 times as much as 300mm wafers, with just 1.2 times the thickness. They will be less rigid and more prone to sagging under their own weight. Wafer transport arms will need to move heavier weights over longer distances—and faster. Wafer transport pods will be bigger and heavier, both loaded and empty.

May Su of Crossing Automation, which is now part of Brooks, estimates that fully loaded 450mm transport pods will weigh more than 20 kgs. The potential need for vacuum-sealed or controlled-atmosphere pods for sensitive processes is unlikely to reduce overall weight.

The cumulative effect will be that all wafer transport components in 450mm fabs will need to be beefed up relative to their 300mm counterparts. Transport motors will need to be larger and stronger, robot arms will need to be more rigid, and so forth. Though the end result may resemble a scaled-up 300mm fab, most components are likely to require some degree of re-engineering.

This is especially true of individual wafer transport arms and end effectors. Edge gripping of wafers causes chips and other damage to the layers near the edge. This damage is believed to contribute to yield loss, especially in the near-edge region, and to be a source of particles generally. The emerging 450mm consensus depends instead on backside support and gripping, with only non-gripping constraint points allowed near the edge. This approach puts a new emphasis on control of vibrations in the transport arm, lest a loosely held wafer “bounces” out of position. Reduced vibrations mean heavier, more rigid transport arms. Backside handling may also be expected to increase backside particles. These are especially relevant to lithography, where they create bumps in the wafer surface and push affected regions out of the focal plane. With the depth of focus budget already very small for deep sub-wavelength lithography, backside particles pose a potentially serious yield hazard.

The sheer bigness of 450mm wafer fabs extends to every aspect of facility design— larger vacuum chambers require more pumping capacity, more power, and more cooling capacity. AMHS systems used to transport larger wafer pods will need longer tracks and larger turning radii. All of these factors will increase the overall footprint of the fab. Peter Csatáry of M+W Group estimates that a 450mm fab will require 30% more gross manufacturing area, with some tools consuming more than 50% more water or electricity. (See Table.) Facilities costs, as well as demands for “sustainable” operations from local governing authorities, will force fabs and equipment designers to consider conservation from the earliest design stages. The good news is that the same factors that multiply resource consumption also multiply savings. Any reduction in equipment power consumption will produce an additional 20% reduction in chillers and other fab infrastructure, Csatáry said.

Table: Impact of 450 mm wafers on fab facilities


Source: M+W Group, Semicon Europa 2012

While larger process chambers and larger transfer arms will be needed, most process equipment can expect to see economic benefits from the larger wafer size. If a single wafer takes approximately the same amount of time to process, but contains more than twice the device area, then the per-device cost should go down. That’s why the industry is planning the transition in the first place.

Lithographers, however, face an additional challenge. If the number of exposure fields goes up, and the time to expose each field stays the same or goes up, then overall throughput goes down and cost per die goes up. Increasing throughput requires some combination of more input power—a significant challenge for EUV lithography in particular—and faster wafer transport, alignment, and stage positioning. More rapid stage acceleration and deceleration make accurate stage placement more challenging. Nor does it help that the first 450mm wafers will probably be targeted to the 10nm device technology node, likely the first one to use EUV lithography for critical layers.

Most current predictions are that lithography tools will be the last sector to be ready for 450mm production, by a wide margin of as much as a year or two. Substantial investments in lithography leader ASML by Intel, Samsung, and TSMC were intended to help accelerate tool development, but it remains to be seen how feasible rapid development is. Volume production cannot begin without lithography. In the meantime, makers of other tools are in the uncomfortable position of facing unpredictable delays before they can begin to recover their own investments.

Update: An earlier version of this article misspelled May Su’s first name.