By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus
Has Apple finally hit the wall after years of sizzling growth? “Relatively soft sales of large-format iPads and iPhones are likely to drive FQ2 revenue to $41.1 billion and FQ3 revenue to $33.5 billion, both of which are below the Street estimates of $42.8 billion and $40.0 billion, respectively,” according to a research note from Pacific Crest Securities. “Among them, we consider the reduction to our large-format iPad estimates to be the most significant, as this appears likely to be a sustained trend as tablet demand shifts to smaller and less expensive models. The shifts to our iPhone estimates are largely related to the product cycle, which we consider to be a transitory issue. However, we continue to believe sell-through evidence supports our view that the high end of the smartphone market is quickly becoming saturated.”

The semiconductor equipment market continues to consolidate. Hitachi High-Technologies has completed its acquisition of SII NanoTechnology from Seiko Instruments. SII, a supplier of photomask repair tools, has been placed into a new subsidiary called Hitachi High-Tech Science. The move also propels Hitachi High-Tech into the mask repair equipment business.

The European Commission is funding yet another 450mm program. The project, called Enable450, includes Intel and fab tool vendors. It is aimed at 450mm wafer processing, specifically targeting European material and equipment companies. The group also consists of U.S. tool vendors, as well. ASM International is the coordinator of the group. Other members are Applied Materials Israel, ASML, CEA-LETI, Fraunhofer, Future Horizons, IMEC, RECIF, SEMI, Soitec, among others. At present, there is no news to report beyond the formation of this group. Stay tuned.

IC Insights has released its top-50 semiconductor supplier rankings. In the rankings, Qualcomm registered a 34% surge in sales and moved up three positions to replace TI as the fourth-largest semiconductor supplier in 2012. GlobalFoundries registered better than 30% growth last year, moving from 21st place in the rankings in 2011 to 15th last year.

Taiwan DRAM maker ProMOS Technologies has agreed to sell its 300mm wafer fab and equipment to GlobalFoundries, according to Reuters.

Peregrine Semiconductor has filed a new suit, alleging the infringement of its RF silicon-on-insulator (SOI) technology by RF Micro Devices. This new legal action is in addition to an existing suit filed by Peregrine against RFMD in February 2012. That case is still pending.

In a blog, Applied Materials’ venture capital arm discusses the lessons it has learned to ensure the mutual success of a startup company and a corporate investor.

In another blog, Applied Materials talks about the evolution of the semiconductor service model. Instead of just repairing the equipment as in the past model, the new idea is to make fab tools work better, with higher output and lower cost of ownership.

SEMI Europe honored four industry leaders for their accomplishments in developing standards for the photovoltaics (PV) industry. The SEMI Standards awards were recently announced at the SEMI PV Fab Manager Forum 2013.

Why is there a need for “best practices” in mixed-signal SoC verification, and what are some of those practices? Cadence provides some insights in a video.

Mentor Graphics said that its FloEFD computational fluid dynamics (CFD) simulation solution helped Skeleton Bobsleigh World Championship winner Shelley Rudman of Great Britain to her first world championship win on Feb. 1 in St. Moritz, Switzerland.

Analog Devices announced that CEO Jerald Fishman passed away suddenly from an apparent heart attack. ADI President Vincent Roche has been appointed CEO on an interim basis by ADI’s board. In a research note, Doug Freedman, an analyst with RBC, said: ”If Jerry Fishman did not touch your life personally, his work and that of ADI have surely touched your life. I had the pleasure of competing against ADI for 12 years, and writing investment research about ADI for another 11 years. While Jerry was given a great company to run he did so much more than could be expected. ADI has been the envy of the analog IC industry for as long as I can remember. In Silicon Valley, we watched ADI build and maintain a data convertor and amplifier franchise that is unmatched in our industry. All the while, competitors tried extremely hard to take away the market share ADI had, and at every turn Jerry, and his east coast based team, turned away the efforts from Silicon Valley and Texas. In one instance, a competitor hired a team of engineers away from ADI and was able to get a foot hold into a market. Jerry fought back and won, not just in the market but in the courts having found patents that were violated. The far reaching impact of Jerry and the work at ADI is being felt in the areas of driver safety, medical imaging, and mobile communication (none of which would be as advanced as they are today without Jerry and his team of analog engineers). In recent years he had turned his attention on making the best better, not just technically but financially. The path he sought was always clear and easy to see, for all those that wished to follow him. I always enjoyed my interactions with him and will miss his conviction, thoughts and guidance. Jerry, Your legacy lives on in your family and ADI.”

China’s move to corner the market for rare-earth minerals (REMs) has prompted manufacturers of low-voltage industrial motors to adopt alternative technologies that reduce or eliminate the use of these materials, spurring new growth in the motors market, according to IHS.

By Mark LaPedus

For years, the DRAM industry has been engulfed in a downturn. Sadly, vendors have grown accustom to overcapacity, falling ASPs and losses. Now, the tide is turning, at least based on the data from Micron Technology. Micron posted a loss this week, but the company provided some surprising and welcomed news about DRAMs. “Despite a weak PC environment and more DRAM capacity from the revised Inotera agreement, Micron is allocating DRAM to some channel and OEM customers. DRAM capacity continues to go offline or transition to NAND, and Micron envisions no new capacity coming online in either 2013 or 2014. This suggests to us that the recent ASP dynamic is here to stay,” said Hans Mosesmann, an analyst with Raymond James. Another chip analyst, Jagadish Iyer of Piper Jaffray, said: “Micron articulated that DRAM capacity likely remains constrained for the next two years as near-term allocation prevails.”

What about NAND flash? “We expect industry supply to be far more rational than years past. Expect NAND ASP trends to strengthen through 2Q ‘13 with handset ramps pending,” said Doug Freedman, an analyst with RBC Capital Markets. Added Monika Garg, an analyst with Pacific Crest: “During our meetings with semiconductor capital equipment companies last month, all companies highlighted that they have not yet received any NAND capacity orders. These comments lend conviction that we should see strong NAND supply-demand balance in 2013.”

Richard Hill, the former chairman and CEO of Novellus, is back in the news. Hill, an outspoken executive who left Novellus after it was acquired by Lam, is leading a committee of independent directors for troubled Tessera. The committee is refocusing Tessera’s DigitalOptics unit. This follows a move by an investment firm to oust Tessera’s CEO and the board.  This week, the board began a search for a new chief executive to replace Robert A. Young, who was ousted. And Hill is the new chairman.

The Saratoga County Industrial Development Agency has approved about $387 million in sales tax exemptions for GlobalFoundries, according to the Saratogian. The tax breaks are for an R&D center and a proposed fab in New York.

In a blog, an investment site discusses its price estimates for Applied Materials. It also gives a fair and balanced analysis of the company.

RF Micro Devices will phase out manufacturing in its Newton Aycliffe, U.K.-based GaAs pHEMT facility and transition most GaAs manufacturing to its GaAs HBT manufacturing facility in Greensboro, N.C. RFMD will also partner with leading GaAs foundries for additional capacity. The U.K.-based GaAs pHEMT facility had been RFMD’s primary source for cellular switches. However, RFMD has transitioned to higher-performance, lower-cost silicon-on-insulator (SOI) technology for the cellular switch.

North American-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.10 in February, according to SEMI. This compares to a ratio of 1.11 in January.

SEMI has released the 4th edition of the International Technology Roadmap for PV (ITRPV), the global collaborative process that informs PV cell, module and system manufacturers, equipment and materials suppliers, and other industry stakeholders on key technology trends in the solar field.

Mentor Graphics and Mercedes-Benz Trucks announced the application of the Mentor Capital software suite to the development of Daimler’s flagship heavy truck, the new Actros.

TEL’s Q3 orders were up 27%, above the firm’s original guidance of “slightly up,” according to Chips and Dips, a blog site.

Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies. In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena. In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology.

Samsung’s new Galaxy S4 smartphone is causing a buzz. In a blog DisplaySearch answered a pressing question: How Did Samsung achieve full HD in the AMOLED display?

Spansion and XMC, a Chinese foundry, announced an expanded partnership to develop and manufacture Spansion’s 32nm NOR flash memory. The agreement expands XMC’s current 300mm manufacturing of Spansion’s 65nm and 45nm flash memory technology.

VLSI Research is raising its 2013 fab tool growth forecast to minus 4.6%. Previously, the 2013 forecast was minus 5.3%. “Memory suppliers are beginning to loosen their purse strings. The orders are technology buys. Capacity expansions are not in the radar. Foundry is cooling due to the pull back by Apple along with some inventory buildups,” according to the firm.

Global PC shipments were expected to decline by 7.7% in the first quarter, according to IDC. However, IDC’s February monthly data suggest that the market could see a drop touching double-digits in the first quarter, according to the firm.

A predicted surge of smaller, lower-priced devices in the tablet market has led IDC to increase its 2013 forecast for the worldwide tablet market to 190.9 million, up from its previous forecast of 172.4 million units.

Samsung catapulted to the top of the optoelectronics supplier ranking in 2012 from 12th place in 2011 after it gained full ownership of Samsung LED, a 50-50 joint venture in light-emitting diodes that was created in 2009 between Samsung Electronics and affiliate Samsung Electro-Mechanics, according to IC Insights.

By Ed Sperling
So many warnings about data overload have been issued over the past decade that people generally have stopped paying attention to them. The numbers are so astronomical that increases tend to lose meaning.

Nowhere is this more evident than in the semiconductor metrology world, where files are measured in gigabytes. And at each new process node, as the number of transistors and features increase—and the number of measurements increase—so does the amount of data that has to be stored and processed.

At the extreme edge of this barrage of data is critical dimension-scanning electron microscopy. Its files are measured in tens or hundreds of gigabytes. Just being able to decipher this much data requires a higher level of abstraction. There is no equipment powerful enough to process it within a reasonable time frame, and no way to retrieve that data quickly. In data terminology, it has to be mined just to be useful.

A scanning electron microscope, or SEM, takes measurements by sending out an electron beam, which interacts with electrons in the material being scanned. That sends back signals, which are mapped by the equipment. The more critical dimensions that need to be mapped, the greater the amount of data that needs to be processed and stored.

Source of the problem
“Everyone wants to use in-line characterization because you can see what you’re measuring,” said Carol Gustafson, metrology sector manager at IBM. “Other tools can’t show what it looks like. With CD-SEM you get numbers and images. A characterization lab can’t produce the quality of information that we can, but it’s a lot of data. And in the development phase, integrators and engineers like to look at in-chip information because it expands the number of targets you can look at.”

A lot of data is an understatement. Even IBM, which is credited with inventing data mining, won’t tackle this problem without help.

“In an area like this within IBM, at a 300mm wafer fab, with partners going in and out all the time, along with their customers, IT likes to keep a high view of the world,” said Gustafson. “But at 22nm we have more mask levels, and we have to measure more things. That also gives us the opportunity metrology, and that increases the amount of data because now we’re dealing with the complexity of developing and understanding an OPC cycle or budgeting in litho patterning and yields issues. There are also more locations to look at what’s going on.”

IBM isn’t alone in trying to navigate this sea of data. What’s new, though, is trying to make sense out of the data to improve everything from a chip’s performance and power to yield.

“Since you’re already taking the image, it’s a question of how you take full use of that data,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries. “We’ve been able to do traditional measurements of a feature or a line width. We’ve also seen some progress to 2D information or being able to add a contour around a feature, so you get the entire feature instead of a point. But it would be nice if we also could get height information with that. Right now you can partially get there with signal modeling or by tilting, or a combination of both.”

That’s more data, though. Add in more mask layers and increased density and the amount of data goes up yet again.

Solutions
Both Applied Materials and Hitachi have been working to provide solutions to the data overload problem in CD-SEM. Of the two, Applied is the only one to bundle it with a multi-core machine. That machine contains 1 TB of RAM, which is large even by supercomputer standards.

Applied’s new data mining software, called TechEdge Prizm, provides CD-SEM tool/recipe/process issue identification, issue diagnosis, and toolfleet matching. That delivers the abstraction layer necessary for critical insights within a reasonable period of time. What used to take days or weeks now can be done in seconds, and that’s particularly important because metrology increasingly is moving into the realm of distributions rather than hard numbers.

Consider line-edge roughness (LER), for example, where fixed numbers no longer exist. Rather than just reporting the data, Prizm also provides the context necessary to utilize that data in a meaningful way. “When you’re dealing with line-edge roughness, there is not just one number,” said Paul Llanos, product development manager for Prizm data mining software at Applied. “You can apply different algorithms and get different numbers. Even in production, it requires more work for optimizing measurement strategies.”

LER was never an issue at older nodes because the measurement technology was sufficient to take readings that were accurate enough. But as feature sizes continue to shrink, even minor fluctuations in LER can impact performance for a device layer. There is a direct correlation between LER and resolution of a lithographic image, and like 193nm lithography, the entire manufacturing industry has been searching for a better solution. This is easier said than done, however. CD-SEM so far has proved to be the least damaging technology, which renders it the most trusted choice at current process nodes. Other technologies can take measurements more accurately, but frequently at the expense of the features being measured.

“At 20nm the data is not as clean as it was at older nodes,” said Llanos. “For challenging levels such as via-intrench, you can rebuild the target offline to consider different measurement strategies but only if the source data exists and can be accessed quickly.. This capability was being drowned out by the volume of data. What we’ve done is get smarter about aggregating the data, so you can get a more granular look at the wafer—what makes it run well versus poorly.”

This kind of data is being used in other portions of the manufacturing process, as well. “When we first rolled this out, it was only the CD-SEM engineers who had access,” said Dana Tribula, vice president and chief marketing officer for Applied Global Services at Applied Materials. “Now there are more than 100 engineers who use it on a regular basis.”

The genesis of a commercial version of this technology was less about a product than solving problems, though. Applied originally developed the technology as an internal tool, and IBM has been working with a variant of this approach for some time.

“Prizm puts lots of CD-SEM parameters together for us,” said IBM’s Gustafson. “We can look at multiple levels at the same time and multiple levels for the same litho level. We also can look at CD-SEM images that show changing aspects, patterns, SIT quality, and you can look at the parameters and images.”

The future
While this is a major step forward in managing the data, the reality is that resolution is falling short at advanced nodes. Lithography is both the key—and the stumbling block—to continued feature shrinks.

Approaches such as scatterometry are promising, but they have their own set of problems. The future also may entail a combination of what are now highly proprietary technologies. GlobalFoundries submitted a paper at SPIE that focused on combining measurements from multiple tools.

“The more tools interact the better,” said Gustafson. “The question is whether the vendors are willing to do that or whether IT will have to make it happen. At least we have industry standards on formatting these days. That’s good, because while the resolution is okay at 22nm, at 14nm certain levels are going to struggle. In particular, the critical levels are going to start to fall apart. And as we continue to shrink, measurements will become more critical and more complicated.”

She’s not alone in seeing that. GlobalFoundries’ Allgair said there are serious questions about what happens beyond 14nm. “CD-SEM is still our most frequently used of any tool out there, but if you look at the papers submitted this year there are concerns about its evolution and the improvements that will be possible.”

But no matter what technology ultimately wins out, the reality is that the amount of data will continue to increase significantly with every new tweak and every new technology hurdle. Just managing that data will be a growing problem. Effectively using it will be even tougher.

By Mark LaPedus
At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969.

This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo over the potential use of DSA, an alternative patterning technology that enables fine pitches through the use of block copolymers.

A year later, DSA has joined the lithography establishment. Amazingly, within a short time span, DSA has moved from a mere curiosity item into the R&D mode at GlobalFoundries, IBM, Intel, Samsung and TSMC. “Companies are taking DSA seriously,” said Bencher, a DSA expert. “If you compared it to last year, we are now in the pre-competitive stage with DSA. The people in DSA have all grown up and are now wearing suits and ties.”

For some time, most chipmakers have kept their DSA efforts shrouded in secrecy. At the recent SPIE event, however, chipmakers finally provided the first glimpse of their initial work and results.

Based on the early findings, DSA still has a way to go before it moves into IC production. Chipmakers are just getting their arms around the problems. And they are still experimenting with an assortment of fab tools, flows, chemistries and design methodologies.

Still, the initial findings are also promising, providing a clue to where DSA is heading. For example, using DSA, Intel demonstrated 28nm structures. Separately, GlobalFoundries devised 28nm fins with DSA. IBM developed a silicon-on-insulator (SOI) DSA flow. And Samsung may have found the path towards sub-20nm DRAMs.

It’s still unclear when DSA will reach production. The projections range from the 14nm to 7nm nodes. “If you ask different people, you will get different answers,” said Joy Cheng, a research staff member at IBM.

DSA: From the lab to the fab?
DSA is not a next-generation lithography (NGL) tool per se, but rather it is a complementary and double-patterning scheme. DSA is also disruptive and threatens the status quo, because the process isn’t dependent on traditional and costly lithography. Many of the key processing steps are conducted in an existing wafer track system.

There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

In theory, DSA is attractive because it could reduce the overall cost of lithography. And compared to EUV, DSA requires less R&D funding.

“We don’t need billions of dollars,” said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications. “Materials development is inherently cheaper than tool development. The current funding is probably adequate to get the industry going for the 14nm node with DSA. If we’re talking about high chi polymers, which will be needed for the 10nm node and beyond, the industry should think about different funding mechanisms. But even so, we are not talking about huge sums.”

Meanwhile, over the last year, Albany Nanotech, CEA-Leti and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations. “Basically, DSA is still in the R&D stage,” said Charles Pieczulewski, director of strategic marketing for Sokudo, a wafer track supplier. “The industry is still working through the bugs with the materials.”

Going forward, the challenge is to bring DSA into the IC design and production phases. “The main challenge is device integration,” said Ben Rathsack, strategic marketing and technology manager at Tokyo Electron Ltd., the world’s largest wafer track supplier.

Last year, Applied’s Bencher listed defectivity as the top challenge for DSA, followed in order by registration, design flexibility and positional accuracy. For 2013, positional accuracy—or the ability to align the block copolymers in the proper place—has moved to the biggest challenge for DSA, Bencher said.

Bencher expects memory makers will be the early adopters for DSA, followed by logic and foundry vendors. The prediction is based on the ability to generate IC designs using DSA. “You hear people saying: ‘We need a whole design ecosystem to enable DSA.’ That might be true for logic, but these are the last people that would implement DSA. This is because you need the most flexible designs in logic,” Bencher said. “Memory makers don’t really need that whole design ecosystem. They need maybe 1% of the EDA ecosystem, compared to the logic people.”

Currently, there are several design approaches for DSA. One idea is using 1D gridded arrays, but the problems are obvious. “Designers don’t want to be restricted to having contacts only on a grid or vias on a grid,” Bencher said.

Another concept is laying down a sea of holes or fins on a pattern. “In the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which ones you want to keep and which ones you want to get rid of. But the problem is that the aerial image can be very sloppy,” he said.

And in another approach, Stanford University is developing an arbitrary design methodology for DSA using an alphabet soup of characters. In this approach, positional accuracy with the contact holes is the biggest challenge.

Chipmakers tip DSA efforts
Design is just one of the many challenges facing silicon foundries with DSA. For example, GlobalFoundries has set up a DSA R&D line at Albany Nanotech. Using chemical epitaxy, the company demonstrated three-stack, 28nm silicon fin structures. It also is experimenting with a graphoepitaxy flow.

“The advantage for using chemical epitaxy is that there is no loss for aerial density,” said Richard Farrell, a principal engineer at GlobalFoundries. “The advantage in working with graphoepitaxy is that it involves a relatively simple process. Some of the challenges that we face for graphoepitaxy is the translation of the edge roughness into the DSA pattern itself. For line/space, we need temperatures above 200 degrees. This has additional constraints on the lithographic performance of the resists.”

Bringing up DSA in a fab is another issue. “First, we have to deal with fab-compatibility in DSA processing,” he said. “There are contamination issues. In pattern transfer, we need to think about balance reflectivity and the use of planarization.”

Despite the challenges, chipmakers are moving full speed ahead with DSA—and for good reason. For example, NAND flash vendors are pushing 193nm immersion and multi-patterning to the limits, but suppliers are in dire need of a new solution. “EUV lithography and double patterning are widely known (to handle) sub-20nm patterning,” said Jaewoo Nam, a lithography engineer at Samsung, at the recent SPIE conference. “But EUV has some limitations. The pattern resolution for EUV is 16nm only. The cost is huge. Double patterning is also very complicated.”

Using DSA, Samsung is exploring the possibility of developing DRAMs at 18nm. Samsung’s initial goal with DSA is to devise 20nm contact holes. In a DSA R&D line, the company has implemented a graphoepitaxy flow using block PS-b-PMMA materials. With a proprietary treatment process, Samsung has improved the CD distribution by 28%, Nam said.

Like Samsung, Intel also is bullish about DSA. “DSA sparks off a dozen different ideas,” said Sam Sivakumar, a fellow and director of lithography at Intel. The possible applications for DSA include contact holes, vias, and the back-end-of-the-line (BEOL) flow, he said.

Intel is conducting its DSA R&D at IMEC. Last year, IMEC set up a 300mm DSA R&D line, which consists of TEL’s track systems. Using the University of Wisconsin flow, Intel devised a three-layer, 28nm stack. The stack includes an interconnect, via and a metal 1 layer.

Intel started with staggered contact hole arrays on a grid at 50nm to 55nm. After the pattern transfer process, the holes were reduced to 26nm to 22nm, representing a 35% shrink. With a blended DSA formula from JSR, Intel obtained the targeted resolutions with good results, said Todd Younkin, a lithography materials researcher at Intel. However, the results were less conclusive with traditional block copolymers, which are provided by both AZ Electronic Materials and Dow.

Another R&D organization, CEA-Leti, last year set up a 300mm DSA pilot line, which uses Sokudo’s track systems. Using PS-b-PMMA from Arkema and a graphoepitaxy process flow, CEA-Leti achieved resolutions from 35nm to 10nm, said Raluca Tiron, a senior scientist at CEA-Leti. “We showed good uniformity with three sigma around 2nm,” she said. “After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts.”

PS-b-PMMA is expected to hit the wall at 10nm, meaning the industry must develop next-generation high chi DSA materials. Others see it differently. “We think we can extend PS-b-PMMA down to the 7nm node,” said Laurent Pain, lithography lab manager at CEA-Leti.

Another player, IBM, is involved in several different DSA efforts. In one effort, IBM demonstrated a larger-pitch 42nm flow, which could one day enable the development of smaller chips based on SOI. In this experiment, IBM used both the Almaden and University of Wisconsin flows, which enabled 42nm and 28nm resolutions. “If we can do self-assembly at 42nm, we can do assembly at smaller pitches,” said Chi-Chun Liu, a research staff member at IBM.

By Mark LaPedus
The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing.

Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology.

For years, inspection and metrology tool vendors have managed to stay one step ahead of the defect curve. But as chipmakers migrate toward finFETs, 2.5D/3D chips and other complex structures, process control will become even more challenging and costly.

In fact, three key process control tools, CD-SEMs, brightfield defect inspection and optical scatterometry, may soon run out of steam, prompting the need for a new class of 3D metrology gear. “When we get to the 14nm node, we may be able to get by with what we have,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries. “As you get to 10nm, we might need a new technology.”

Next-generation 3D metrology tools exist to some degree, but the industry must make substantial investments to bring these technologies into production. And that’s precisely where the problem, and tension, exists between chipmakers and tool vendors. To develop new tools, equipment vendors want a bigger piece of the R&D pie and want customers to assume more of the risk.

“Different business models are definitely needed,” said Chris Talbot, senior director of strategic licensing at Applied Materials. “As the industry consolidates, with 450mm and EUV on the horizon, the amount of R&D that needs to be done not just in metrology and inspection, but right across the equipment industry, is enormous.”

One idea is to replicate ASML Holding’s recent and blockbuster business deal. Intel, Samsung and TSMC recently invested millions of dollars in ASML to speed up the development of extreme ultraviolet (EUV) lithography and 450mm tools. The three chipmakers also took minor stakes in ASML.

“The investments made by Intel and others in ASML are huge to solve an enormous problem,” Talbot said. “This is maybe one of the things we need to look at for other segments of the industry.”

Wanted: New business models
It’s unlikely that the inspection/metrology industry, or other fab tool sectors, will garner the same level of funding as the ASML deal. Lithography is considered the key manufacturing technology in IC scaling, and it will require a substantial investment to propel the development of EUV and 450mm lithography tools.

In the process control sector, the industry is providing substantial funding to KLA-Tencor, Zeiss and others for the development of EUV mask inspection tools. But beyond EUV, the industry may need to rethink the R&D funding model.

For years, chipmakers, consortia, venture capitalists and even governments have provided various levels of funding to equipment vendors for the development of new fab tools. Generally, the fab tool vendors themselves have assumed a larger percentage of the R&D bill and assumed more of the risk.

Today, however, tool vendors can no longer afford to develop a system on a whim and foot the R&D bill. The development costs, and the risks, are too high. After all, only a handful of chipmakers buy advanced tools today.

As before, there are no guarantees that a proposed tool will move into production. At times, equipment makers also fail to deliver the promised goods. But the real problem surfaces when a chipmaker demands a new system for a future node. An equipment maker complies and develops the system.

Then, in some cases, the IC maker decides not to insert the proposed tool. Instead, the company ends up extending the current technology. For this reason and others, the equipment maker ends up holding the bag. “If you look at the last 10 years, there are very few examples where a technology that we talked about was actually converted into a tool that we could put in our fabs,” acknowledged Alok Vaid, senior member of the technical staff at GlobalFoundries.

So, the time is ripe for a new R&D and risk-sharing model, although don’t look for an immediate change. “The industry has invested in time, resources and materials in process control,” said GlobalFoundries’ Allgair. “You’ve seen some investments through research consortiums. But we’re probably reaching the point where it needs to extend a little bit further than that. We should try to explore some different funding models.”

Given the enormous risks involved in tool development, chipmakers also must open the lines of communication and do a better job in conveying the exact types of technologies needed for a given node, he added.

Wanted: New metrology tools
Chipmakers are finally addressing the problems with the current R&D funding model, as some of today’s process control tools may soon hit the scaling wall. Fortunately, there are some promising next-generation candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging; meanwhile, multi-beam e-beam inspection could displace brightfield inspection. And X-ray scattering (CD-SAXS) could succeed optical scatterometry.

In one area, Applied and KLA-Tencor are among the major suppliers of optical-based brightfield inspection tools. Used to find defects during transistor fabrication, brightfield is a technique that collects light reflected from a defect. In turn, the defect appears dark against a white background. Brightfield is often used in conjunction with single-beam e-beam inspection, which detects even smaller defects.

As chips move to finer feature sizes, brightfield may have trouble seeing smaller defects. “It’s believed that 20nm is a critical particle size in which scattering falls off,” said Benjamin Bunday, senior technical staff member at Sematech. “E-beam inspection can see 5nm particles. But, of course, the throughput is too slow.”

Still, the death of optical and single-beam e-beam inspection is greatly exaggerated, said Mingwei Li, director of product marketing at KLA-Tencor. “Even with today’s wavelengths in optical inspection, we are detecting defects in the range of 10nm,” Li said. “We are not very far off with the ITRS roadmap, which specifies 5nm defects. We also think e-beam has a place.”

One possible successor to brightfield is multi-beam e-beam inspection technology. Multiple beams can boost inspection throughputs, but the technology is difficult to develop and control.

One startup, Multibeam, is developing a 100-column e-beam inspection system. Multibeam’s technology will not replace today’s optical and single-beam e-beam inspection, but rather it is a complementary approach, said David Lam, a venture capitalist and chairman of Multibeam. “We’re focusing on detecting small physical defects that are almost indistinguishable to noise,” Lam said.

Perhaps the biggest challenge for startups like Multibeam is clear—getting funding. “It is indeed very difficult to get funding,” Lam said. “Semiconductor equipment, in particular, is considered passé. It’s something that’s takes too much money. You can’t go IPO. It’s a very unattractive investment for investors.”

Multibeam is not looking for a handout, but the startup needs some backing to advance its tool. “I don’t think it will take $3 billion or $4 billion in funding like EUV. I’d say tens of millions of dollars,” he added.

Besides a new inspection technology, the IC industry is also looking for a next-generation scatterometry tool. Scatterometry analyzes changes in the intensity of light in a device, but the shift towards finFETs presents a challenge for the technology.

As a replacement, the industry is looking at CD-SAXS, a technique that uses a shorter wavelength to measure structures. The downfall with CD-SAXS is that it makes use of a synchrotron radiation source. “CD-SAXs is too slow,” said GlobalFoundries’ Allgair. “We need a new high-brightness source and faster measurement times.”

Another tool under stress is the scanning electron microscope (CD-SEM), which measures critical dimensions in chip structures. “The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said Eric Solecky, senior manufacturing engineer at IBM.

There is one solution on the table. In 2006, Carl Zeiss acquired Alis, a supplier of helium ion microscopy. The technology was supposed to provide better resolutions than CD-SEMs. “We thought we would go to the semiconductor market and solve all of their problems,” said Bipin Singh, product manager for Zeiss. “It turns out the traditional CD-SEM was good enough. The list price for a helium ion microscope was $2.1 million. The industry wasn’t willing to bear the costs.”

Last year, Zeiss decided to focus its helium ion microscopes for nanotechnology fabrication. But as the IC industry moves towards finFETs, some are once again looking at helium ion as a possible replacement for CD-SEMs.

Applied, Hitachi and other CD-SEM suppliers are not throwing in the towel just yet. “The case for helium ion is a bit fuzzy,” said Applied’s Talbot. “Conventional CD-SEMs are getting older, but they are still doing the job and are extendable.”

By Mark LaPedus
Sara Volz, 17, of Colorado Springs, Colo., won $100,000—the top award—from the Intel Foundation for her research on algae biofuels. Algae produces oil that can be converted into a sustainable, renewable fuel. Volz, who built a home lab under her loft bed, sleeps on the same light cycle as her algae.

For years, the investment community has demanded that ASM International (ASMI) should break up the company into two pieces. This week, ASMI finally caved in, leaving some to wonder if the company is the next takeover target in the semiconductor equipment business. ASMI intends to sell a stake in ASM Pacific Technology, valued at between 8% to 12%. Following the planned divestment, ASMI will own between 40% and 44% of the shares in ASM Pacific, a supplier of wirebonders.

A TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in a cross section. What does this all mean? According to Applied, it’s a breakthrough in reflow to push interconnect boundaries beyond 20nm.

Applied Materials was named by the Ethisphere Institute, a business ethics think-tank, as one of the 2013 world’s most ethical companies.

MEMC, a supplier of silicon and SOI wafers, announced a plan, subject to shareholder approval, to change its name to SunEdison. The name change reflects its recent efforts in the solar industry. MEMC competes in both the semiconductor and solar industries. Does the name change reflect that semis are passé or does MEMC have an identity crisis?

Specialty foundry TowerJazz is seeing significant customer engagements and market share gain in the fast growing RF front-end module market. For Skyworks and others, TowerJazz is providing RF SOI, RF CMOS and SiGe processes.

ALTIS Semiconductor announced the finalization of a foundry agreement with IBM Microelectronics. Under the terms, ALTIS will be the foundry partner for the IBM 180nm RF SOI technology.

SEMI reported that worldwide sales of semiconductor manufacturing equipment totaled $36.93 billion in 2012, representing a year-over-year decrease of 15%.

Cadence has agreed to buy Tensilica, setting the battle over IP into high gear among EDA vendors.

Mentor Graphics announced the Nucleus SmartFit product, a cost-effective, binary version of the Nucleus RTOS optimized to fit the limited internal memory of 32-bit MCUs.

ST-Ericsson, a joint venture of STMicroelectronics and Ericsson, announced that Didier Lamouche, president and chief executive, has decided to resign from the company to pursue other opportunities. And following those events, Ericsson and STMicroelectronics this week announced an agreement on the fate of ST-Ericsson. Ericsson will take on the design, development and sales of the LTE multimode thin modem products, including 2G, 3G and 4G multimode. ST will take on the existing ST-Ericsson products, other than LTE multimode thin modems, and related business as well as certain assembly and test facilities. The companies will close down the remaining parts of ST-Ericsson.

China’s Advanced Micro-Fabrication Equipment (AMEC) will make its solid-state lighting market debut with a new multi-reactor metal organic chemical vapor deposition (MOCVD) cluster tool. The Prismo D-Blue MOCVD platform enables high-volume manufacturing of GaN, InGaN and AlGaN structures required for high-brightness LEDs.

Nanoplas announced a new dry-etch process that offers unlimited etch selectivity for removing dielectric films. Nanoplas’s new Atomic-Layer Downstream Etching (ALDE) processing allows etching rate and selectivity to be controlled independently.

According to IHS, the steady increase in PC capabilities that has justified the upgrade cycle and fueled the long-term growth of the PC market is undergoing a historical deceleration.

Household adoption and spending on consumer technology products is shifting faster than expected in favor of gadgets and services that are portable or mobile, according to a recent survey by Gartner.

By Mark LaPedus
For years, Brazil has been trying to get a semiconductor industry off the ground. A government-backed entity called Ceitec operates a small-scale fab in Brazil. There are also several IC design centers in that nation. Last November, SIX Semiconductors emerged and announced plans to build a fab in Brazil. The venture includes a partnership between IBM and SIX Soluções Inteligentes, a technology company of EBX Group, and others. The group will invest R$1 billion, or US$513 million, to a fab in Ribeirão Neves. Recently, the group was on a job-recruiting mission in the United States. In total, there are 300 job positions available at SIX Semiconductors in Brazil.

Starboard Value LP, together with its affiliates, currently owns 7.4% of the outstanding common shares of chip-packaging IP provider Tessera. The investment firm wants to shake up the board and oust the CEO. This follows allegations that Tessera’s CEO may have been engaged in inappropriate behavior.

Front-end fab equipment spending is expected to be flat in 2013, remaining around $31.7 billion, according to SEMI. Front-end fab equipment spending is projected to hit $39.3 billion in 2014, a 24% increase, according to SEMI.

Semiconductor industry growth drivers and European market strategies were featured topics at the recent SEMI Industry Strategy Symposium (ISS) Europe 2013. In one area of growth, NXP believes that by 2022, about 20% to 25% of global passenger vehicles will be connected to intelligent traffic management infrastructure and/or in-vehicle networks.

The flexible and printed electronics community reports encouraging progress in the materials and process ecosystem needed for commercial production, according to SEMI.

RDA Microelectronics has begun volume shipments of its GPS LNAs for use in Samsung’s 3G handsets. Developed on silicon-on-insulator (SOI) CMOS process technology, RDA’s GPS LNA is a high-gain, small-size amplifier ideally suited for GPS, Galileo and GLONASS applications in 2G and 3G handsets.

RF chipmaker Skyworks Solutions said that its SOI switching technology is now being utilized by European, Japanese, Korean and North American car manufacturers for advanced infotainment systems.

Peregrine Semiconductor will collaborate with Murata on a multisource arrangement for RF switches and other components based on Peregrine’s UltraCMOS technology. UltraCMOS is based on a variant of SOI.

Cadence introduced design and verification IP supporting the new Mobile PCI Express (M-PCIe) specification.

Mentor Graphics announced several new capabilities for its Flowmaster simulation software solution for thermo-fluid systems. Mentor also intends to pay an annual cash dividend of $0.18 per share on its common stock.

Applied Materials has approved an 11% increase in the quarterly cash dividend from $0.09 to $0.10 per share, payable on June 13.

Spansion and United Microelectronics Corp. announced the joint development of a 40nm process that integrates UMC’s 40nm LP logic process with Spansion’s embedded charge trap flash memory technology. As part of the non-exclusive agreement, UMC is licensed to manufacture products based on this technology for Spansion.

Cortus, a provider of 32-bit processor IP, and speciality foundry Dongbu HiTek are teaming up to offer platform solutions. The design platforms will be based on the Dongbu HiTek 0.13-micron eFlash technology and Cortus APS3R processor and peripheral IP.

IDT has transferred the assets and design team of its smart-metering IC product lines to Atmel in an all-cash transaction.

Significant reductions in capital equipment spending among DRAM makers are expected to stabilize DRAM prices at a minimum, but more likely will help drive prices further upward throughout the balance of the year, according to IC Insights.

Capex budgets are also being trimmed for NAND flash (though not nearly as much as DRAM), and that, along with ongoing unit demand, has put upward pressure on ASPs for these memory devices as well.

By Mark LaPedus
Altera has entered into an agreement for the future manufacturing of its FPGAs based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant. That puts the processor giant on a collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC

The Altera-Intel deal could change the landscape in the foundry business, in which Intel will likely become a much bigger player in the arena. But does Intel have staying power to remain in the foundry business? Added John Vinh, an analyst from Pacific Crest Securities: Altera’s “foundry agreement with Intel is exclusive for the foreseeable future. We believe Altera will have exclusive access versus Xilinx at 14nm and effectively have the right of first refusal at 10nm. Strategically, we believe this is likely the most significant aspect of this agreement in that it prevents Xilinx from having access.”

At SPIE, ASML Holding disclosed various milestones with its extreme ultraviolet (EUV) lithography technology. ASML’s EUV production tool, dubbed the NXE:3300B, has demonstrated resolutions of 13nm for lines and spaces and 18nm contact holes. In addition, ASML demonstrated a 40-Watt source with dose control and under good collector protection conditions in six 1-hour runs. It also demonstrated a 55-Watt source in a 1 hour run. But that’s a far cry from the eventual goal. By 2015, ASML hopes to deliver a 250-Watt source for the NXE:3300B, thereby enabling a throughput of 126 wafers an hour.

With the help of self-aligned double patterning (SADP), sometimes called spacer, ASML’s NXE:3300B also demonstrated the ability to print lines and spaces down to 9nm. The work was done in conjunction with ASML, Applied Materials and Imec.

At the International Semiconductor Strategy Symposium in Europe (ISS Europe) on Feb. 24-26, the European semiconductor industry discussed 450mm fabs and other chip topics. In addition, European Commissioner Neelie Kroes floated the idea of creating an “Airbus for chips,” a European initiative for the semiconductor industry comparable to the launch of the Airbus in the aviation industry.

Also at ISS Europe, Malcolm Penn, chairman and CEO of Future Horizons, said that the decline of the major European chip makers has been a result of a defeatist attitude, not necessarily fundamental structural issues. He suggests European chip makers should build a 450mm fab jointly and operate it as a foundry.

SEMI has announced the release of “Global Trade War and Peace: Unified Approaches to a Global Solar Energy Solution,” a white paper containing recommendations to move beyond trade litigation and encourage an accelerated path towards dispute resolution.

In case your calendar has turned into a blur, take note: Semicon is near! SEMI, in collaboration with leading investment groups, has announced the Silicon Innovation Forum (SIF). The forum will bridge funding gaps for new and early-stage companies with manufacturing and technology solutions. SIF will be held in conjunction with Semicon West, on July 9 at the Moscone Center in San Francisco.

At the Mobile World Congress in Barcelona, Peregrine Semiconductor rolled out its latest version of its UltraCMOS process technology, dubbed Semiconductor Technology Platform 8 (STeP8). UltraCMOS is a variant of silicon-on-insulator (SOI) technology called silicon-on-sapphire (SoS).

Also in Spain, Skyworks Solutions said it is ramping several antenna-tuning products with leading smartphone manufacturers. The tuning devices are based on SOI technology.

The RATP Group, the fifth-largest urban transport operator worldwide, has awarded Soitec and Philips/Step an LED lighting contract for its metro and network stations.

Soitec and Medina College of Technology have signed a cooperative agreement for concentrating photovoltaic technology in Saudi Arabia.

GT Advanced Technologies has entered into a development and licensing agreement with Soitec to develop and commercialize a hydride vapor phase epitaxy (HVPE) system for producing GaN template substrates.

Mentor Graphics announced record financial results for the company’s fiscal fourth quarter and year ended Jan. 31.

During a conference call, Walden Rhines, chairman and CEO of Mentor, said the quarter was an all-time revenue and EPS record. Rhines also has a mixed forecast for the overall IC industry in 2013. “For next year, the analysts project mid-single-digit growth, but the general attitude is less positive,” he said.

Mentor Graphics rolled out the Kronos Cell Characterization and Analysis platform.

A blogger discusses Applied Materials, saying the company is at the cyclical trough and its prospects should improve with an increase in equipment spending.

Applied Materials announced that Bob Halliday has been named senior vice president and chief financial officer. Halliday previously was executive vice president and chief financial officer of Varian Semiconductor Equipment Associates prior to Applied’s acquisition of the company in November 2011.

Micron Technology announced the Tokyo District Court’s issuance of an order approving Elpida’s plan of reorganization. Elpida’s plan of reorganization calls for Micron to acquire Elpida. In addition, mixed-signal foundry specialist LFoundry has acquired Micron’s fab in Italy.

Whatever happened to Conexant Systems? The chipmaker recently went private to avoid a takeover. Now, the company this week implemented a restructuring agreement. As part of the plan, Conexant voluntarily filed protection under Chapter 11 of the United States Bankruptcy Code.

Photomask maker Photronics has announced its intent to acquire the shares of its majority-owned Taiwan subsidiary, PSMC.

After a loss and a proxy battle, Aetrium is considering options that may include a sale or other disposition of one or both of its reliability test and test handler product groups.

According to IHS, the competitive landscape of the cell-phone integrated circuits business has completely transformed over the past five years, with Qualcomm and Samsung capitalizing on the rise of smartphones and 4G.

By Mark LaPedus
It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes.

Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC makers will likely use today’s 193nm immersion with multiple patterning at 14nm, 10nm and perhaps beyond. “10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries. “We have evidence that we can do 7nm with immersion.”

GlobalFoundries, for one, is laying the groundwork if EUV is ready by 10nm. “We are keeping our ground rules migrate-able to EUV,” added Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries.

Chipmakers are keeping their options open for good reason—extending optical comes with a penalty. The shift from single patterning at 28nm to multiple patterning at 20nm is projected to increase lithography costs by up to 56%, according to Barclays Capital. Consequently, the overall cost-per-transistor curve is in danger of slowing or derailing.

Lithographers, who seem to achieve miracles when the chips are down, are determined to stay on Moore’s Law. “The cost of processing might go up with multiple patterning, but cost-per-transistor does not,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.

The ability to stay on the critical cost-per-transistor curve puts enormous pressure on the lithographic supply chain, which includes the EDA houses, materials suppliers, mask shops, and tool vendors. In response, Nikon is quietly shipping a faster scanner for 10nm. Lithographers also may resort to some new patterning tricks. The wild card is directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers to enable fine pitches.

EUV woes
For years, there have been fears that optical lithography would run out of gas, prompting the need for a new next-generation lithography (NGL). EUV emerged as the leading NGL candidate. The other NGLs, maskless and nanoimprint, are also in the hunt.

EUV, a soft X-ray using 13.5nm technology, is attractive because it keeps the industry on a single-exposure path. But EUV has encountered several delays due to the lack of adequate power sources, defect-free photomasks and photoresists.

The current throughput for ASML’s EUV tools is less than 10 wafers an hour (wph). At one time, ASML hoped to ship an EUV scanner with a 150-watt source by mid-2012. A 150-watt source equates to a more acceptable throughput of 69 wph.

Recently, the 150-watt source was delayed again and pushed out to mid-2014. The source is being developed by Cymer, which itself is being acquired by ASML. Separately, Intel, Samsung and TSMC have recently invested in ASML to help fund ASML’s efforts in EUV and 450mm.

ASML is still targeting EUV for mass production in 2014, but the industry isn’t taking any chances and will extend 193nm immersion—at a price. On average, there are 37 lithography layers processed for 32nm/28nm chips, according to Barclays. Of those, there are 14 critical layers processed using 193nm immersion scanners.

In total, there are 38 lithography exposures at 32nm/28nm, 15 of which are immersion exposures, with only one multiple patterning step in the flow, according to Barclays. In terms of lithography equipment costs at 32nm/28nm, a foundry spends an estimated $17 million per 1,000 wafer starts per month (wspm).

In comparison, there are 40 lithography layers for at 22nm/20nm chips, 19 of which are critical layers. In total, there are 52 lithography exposures at 22nm/20nm, 31 of which are immersion exposures with 11 multiple patterning steps. All told, a foundry is expected to spend $27 million per 1,000 wspm in lithography costs, according to the firm.

Lithography steps and costs will soar at 14nm and beyond. In response, chipmakers already are prepared for the dreaded multiple patterning era. NAND flash vendors, for example, are using a multiple patterning technique called sidewall image transfer (SIT), sometimes called self-aligned double patterning.

In logic, vendors have or will implement one of the various flavors of multiple patterning: SIT, litho-etch-litho-etch (LELE) or self-aligned vias. Intel, for one, is embracing a concept called complementary lithography, which involves an SIT flow. Other logic vendors are following a similar path with various nuances.

Today, Intel is using 193nm immersion with multiple patterning at 22nm, with plans to extend that to 14nm. At 22nm, Intel’s processors are based on finFETs. “For the 22nm node, our fin is finer than what can be done with simple patterning. It’s done with pitch division. We still stay on an historical cost-per-transistor trend,” said Intel’s Borodovsky. “Our 14nm technology is also pitch-divided technology. We project our cost-per-transistor will remain on the trend.”

For 11nm, Intel is looking at quintuple exposure. As part of the process, there are two steps, gratings and line cuts, to pattern designs. Using 193nm immersion, the first exposure is used to make the gratings. The remaining four exposures are used to cut the pitch-divided lines.

To perform the cut step, Intel is evaluating several options: 193nm immersion; DSA, EUV; or direct-write e-beam. So far, there is no clear winner—193nm immersion is challenging, but DSA, EUV and maskless are not ready for mass production.

“I believe we can extend (193nm immersion) for many years,” Borodovsky said. “We also have a dual wave lithography roadmap. It means we will extend existing technology as long as possible. And we will bring in new technology when it is available and affordable.”

Using NGL has some advantages over optical. “If we use EUV, we will use one mask to do the gratings and another mask to break those continuities. If we use direct write, we don’t use any masks,” he said.

Another technology, DSA, potentially could extend 193nm lithography beyond 10nm. As before, the challenges for DSA are defects and the lack of a design infrastructure. The new gap for DSA is non-destructive metrology as a means to inspect the morphologies in the patterns.

DSA materials providers have said DSA would be ready at 10nm, but there are signs the technology may get pushed out. For example, IBM is targeting DSA for 7nm, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM.

“DSA is making progress,” said Intel’s Borodovsky. “But let’s say we use DSA. If you look at a SEM, you look at the top. Everything may appear perfect. But the cylinders could also change their shapes from top to bottom. You have to have a cross section. So, it’s very difficult to do a cross section of 15nm holes or cylinders. You can do complicated X-ray metrology. For this, you need a synchrotron source, which is not practical.”

Etch is another roadblock. Some of the cylinder morphologies in DSA structures are uniform while others are not. “Some would etch to the bottom. You might also have cylinders that are etched in the wrong place. That’s an edge-placement error,” he added.

The solutions
Until NGL is ready, chipmakers are stuck. “I don’t think the industry has given up on EUV. EUV will be in play, but it will be in limited use,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “But for 10nm, almost all logic vendors are looking at immersion technology. Customers are even looking at extending immersion beyond 10nm.”

To keep up with the increase in multiple patterning steps, ASML and Nikon are shipping faster scanners. Nikon, for one, has begun shipping the NSR-622D, a 193nm immersion scanner for the 10nm node. The tool has a throughput of 200 wph. In addition, Nikon is also developing a separate 193nm immersion tool for the 450mm wafer size.

Besides lithography scanners, there is an urgent need for new and faster e-beams in photomask production. Mask making itself is quickly turning into a fine and precise art. In quadruple patterning, for example, the patterns must be split into four masks.

“One mask has to be perfect in terms of CD uniformity, linearity and defects. The other three masks have to be exactly the same,” said Amitabh Sabharwal, general manager for mask etch products at Applied Materials. “When you start going down to the 16nm node, the CD uniformity targets become very, very tight. We’re talking in the range of 1nm. And on top of that, the defect levels might be very tight. Your systematic uniformity has to be zero. Essentially, everything must be flat.”

Looking into his crystal ball, lithography expert Chris Mack predicts that the industry will embrace new design methodologies such as 1D layouts. “We will see more interaction between lithography and design,” Mack said. “The reality of what we can accomplish lithographically will have more influence on the way designs are implemented. In fact, this might not be a bad thing. The switch from arbitrary designs to more (1D-like layouts) is turning out to have less impact on chip area than many people expected. And they are lithographically friendly.”

The industry also will embrace complementary lithography or hybrid approaches. “There is no doubt in my mind that optical will go forever,” he said. “But I do think there is a possibility of hybrid lithographic approaches that are optimized for specific types of patterns. Complementary lithography is a powerful technique and makes the most sense. All of the (NGLs) have a lot of potential, but they are not being developed in the timeline the industry needs.”