Posts Tagged ‘Applied Materials’
By Ed Korczynski, Sr. Technical Editor
At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.
Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:
- Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
- Michael Guillorn, Ph.D. – research staff member, IBM,
- Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
- Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
- Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.
Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.
Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.
Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm: gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.
Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.
Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:
- everything is an interface requiring precision materials engineering,
- film depositions are either atomic-layer or selective films or even lattice-matched,
- pattern definition using dry selective-removal and directed self-assembly, and
- architecture in 3D means high aspect-ratio processing and non-equilibrium processing.
An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.
“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.
There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.
However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”
A new hardmask material and process was introduced this month by Applied Materials. Designed for advanced logic and memories, including DRAM and vertical NAND, the hardmask is transparent, which simplifies processing. It also exhibits very high selectivity, low stress and good mechanical strength. It’s also ashable, so that it can be removed after etching is completed. Called Saphira, the process was developed in conjunction with Samsung and other customers. An Applied Materials-developed process for stripping the hardmask was licensed to Korea-based PSK.
Hardmasks are used for etching deep, high aspect ratio (HAR) features that conventional photoresists cannot withstand. Applied Materials first introduced an amorphous carbon hardmask in 2006, and now has a family of specialized films. The Advanced Patterning Films (APF) family now includes APFe, which enables deposition of thicker layers than APF (e.g., in capacitor formation and metal contacts for memory devices), and APFx, design to address patterning of metal lines and contacts at 5xnm and beyond.
The new Saphira APF process – which runs on the Applied Materials Producer XP Precision CVD chamber and works with PSK’s OMNIS Asher systems — introduces new film properties that include greater selectivity and transparency. The Saphira APF deposition and resolve major issues to improve patterning of more complex device structures at advanced technology nodes. “It’s a materials solutions,” said Terry Lee, vice president of strategy and marketing for the dielectrics systems and modules group at Applied Materials. “It’s delivered with the patterning film itself, Saphira, as well as the combination of technologies and processes, whether it’s in the CVD chamber or etch chamber, reducing process steps and simplifying process complexity.
Applied Materials isn’t saying exactly what the Saphira hardmask is composed of, but a recent patent filing describes it as boron-rich amorphous carbon layer. The patent notes that, compared to carbonaceous masking layers, boron-doped carbonaceous layers, which include between 1 wt. % and 40 wt. % boron provide even greater etch resistance.
Lee said the Saphira film “In general behaves very much like a ceramic. But unlike most ceramics, it’s ashable. It’s structurally hard like a ceramic, but it’s ashable like our standard carbon hard mask,” he said.
In general, the selectivity of Saphira is twice the conventional masking materials on the open market, Lee said.
The new process reduces process complexity and cost in a couple of different ways. Because it’s transparent, no extra step is needed to open the mask to find the alignment mark. And because the film has high selectivity, fewer masking steps are required. That all reduces the process complexity. Lee said that with conventional masks, in order to mask these high aspect ratio features, a thicker mask material is often needed. “When you have a thicker mask and you need to etch fine features, what you wind up with is a very narrow mask. In order to prevent the mask itself from collapsing or titling, you need very strong mechanical strength. With Saphira, we have that high mechanical strength and it resists the deformation,” he said.
Saphira can also reduce the need for multiple hardmasks. “Instead of having the hardmask, oxide and poly (see figure), it drops down to a one mask that’s thinner because the selectivity is higher,” Lee explained. “What we’re seeing is that we can reduce around 20 steps. When you reduce steps, you reduce cost. What we’re seeing based on our calculations is something like 35% reduction in cost of this one module. Across multiple modules, that adds up to a lot of money,” he added.
By Jeff Dorsch, contributing editor
Gary Dickerson, Applied’s president and CEO, told analysts that the combination with TEL has just received unconditional approval from Germany’s competition authority. Without disclosing details, he added that the regulatory process is potentially pushing closing of the transaction into the new year.
Applied and TEL previously said that they expected to complete the mega-merger during the second half of calendar 2014. Shareholders of both companies have approved the transaction, leaving the process in the hands of antitrust regulators in several countries.
Last July, the two companies announced that the combined company will be called Eteris B.V.
Applied also reported today the financial results of its fiscal fourth quarter and fiscal year ended October 26. In Q4, Applied posted net income of $290 million on revenue of $2.26 billion, compared with the year-ago figures of $183 million in net income and revenue of $1.99 billion.
For the full year, Applied posted net income of $1.1 billion on revenue of $9.07 billion, compared with fiscal 2013’s net income of $256 million on revenue of $7.51 billion.
Applied had orders of $2.26 billion in the fourth quarter and of $9.65 billion in the fiscal year.
For its fiscal first quarter, the company is forecasting its net sales will be flat to up 5 percent from the fiscal fourth quarter.
Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.
Phil Garrou blogs that most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers. NANIUM also has extensive volume manufacturing experience in WB multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.
Gabe Moretti says it is always a pleasure to talk to Dr. Lucio Lanza and I took the opportunity of being in Silicon Valley to interview Lucio since he has just been awarded the 2014 Phil Kaufman award. Dr. Lanza poses this challenge: “The capability of EDA tools will grow in relation to design complexity so that cost of design will remain constant relative to the number of transistors on a die.”
Are we at an inflection point with silicon scaling and homogeneous ICs? Bill Martin, President and VP of Engineering, E-System Design thinks so. I lays out the case for considering Moore’s Law 2.0 where 3D integration becomes the key to continued scaling.
Congratulations to Applied Materials Executive Chairman Mike Splinter on receiving the Silicon Valley Education Foundation’s (SVEF) Pioneer Business Leader Award for driving change in business and education philanthropy by using his passion and influence to make a positive impact on people’s lives.
At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. As Adele Hars reports, speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM.
Siobhan Kenney of Applied Materials reports that The Tech Museum of Innovation announced the ten recipients of the Tech Awards. Presented by Applied Materials, this is a global program honoring innovators who use technology to benefit humanity. These incredible Laureates are addressing some of the world’s most critical problems with creativity – in naming their organizations and in designing solutions to improve the way people live.
Jean-Pierre Aubert, RF Marketing Manager, STMicroelectronics says RF-SOI is good for more than integrating RF switches. Other key functions typically found inside RF Front-End Modules (FEM) like power amplifiers (PA), RF Energy Management, low-noise amplifiers (LNA), and passives also benefit from integration.
Phil Garrou blogs Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.
Stephen Whalley, Chief Strategy Officer, MEMS Industry Group, blogs about the inaugural MIG Conference Shanghai, September 11-12th, with their local partners, the Shanghai Industrial Technology Research Institute (SITRI) and the Shanghai Institute of Microsystem and Information Technology (SIMIT). The theme was the Internet of Things and how the MEMS and Sensors supply chain needs to evolve to address the explosive growth in China.
SEMI praised the bipartisan effort in the United States House of Representatives to pass H.R. 2996, the Revitalize American Manufacturing and Innovation (RAMI) Act. SEMI further urged the Senate to move quickly on the legislation that would create public private partnerships to establish institutes for manufacturing innovation.
Jeff Wilson, Mentor Graphics, writes that in integrated circuit (IC) design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.
Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs that at the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.
By Ed Korczynski, Sr. Technical Editor
Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem
Q1: The fabless-foundry relationship in commercial IC manufacturing was established during an era of fab technology predictability—clear litho roadmaps for smaller and cheaper devices—but the future of fab technology seems unpredictable. The complexity which must be managed by a fabless company has already increased to justify leaders such as Apple or Qualcomm investing in technology R&D with foundries and with EDA- and OEM-companies. With manufacturing process technology integrating more materials with ever smaller nodes, how do we manage such complexity?
ANSWER: Gregg Bartlett, Senior Vice President, Product Management, GLOBALFOUNDRIES
The vast majority of Integrated Device Manufacturers (IDMs) have either gone completely fabless or partnered with foundries for their leading-edge technology needs instead of making the huge investments necessary to keep pace with technology. The foundry opportunity is increasingly concentrated at the leading edge; this segment is expected to drive 60 percent of the total foundry market by 2016, representing a total of $27.5 billion. Yet there are fewer high-volume manufacturers that have the capabilities to offer leading-edge technologies beyond 28nm, even as the major companies have accelerated their technology roadmaps at 20nm and 14nm and added new device architectures.
This has led to a global capacity challenge. Leading-edge fabs are more expensive and fewer than ever. At the 130nm node, the cost to build a fab was just over $1B. For a 28nm fab, the cost is about $6B and a 14nm fab is nearly $10B. Technology development costs are rising at a similar rate, growing from a few $10M’s at 130nm to several $100M’s at 28nm.
On top of these technology and manufacturing challenges, product life cycles are shrinking and end users are expecting more and more from their devices in terms of performance, power-efficiency, and features. Competing on manufacturing expertise alone is no longer a viable strategy in today’s semiconductor industry, and solutions developed in isolation are not adequate. The industry must work closer across all levels of the supply chain to understand these dynamics and how they put demands on the silicon chip.
Fortunately, the fabless/foundry model is evolving to accommodate these changing dynamics. We have been promoting this idea for years with what we like to call “Foundry 2.0.” In the 1970s/1980s, the industry was dominated by the IDM. Then the foundry model was invented and grew to prominence in the 1990s and early 2000s, but it was much more of a contract manufacturing model. A fabless company developed a design in isolation and then “threw it over the wall” to the foundry for manufacturing. There was not much need for interplay between the two companies. Of course, as technology complexity has increased in the past decade, this dynamic has changed dramatically. We have entered the era of collaborative device manufacturing. Collaboration is a buzz word that gets thrown around a lot, but today it really is critical and it needs to happen across all vectors, including design flow development, manufacturing supply chain, and customer engagement.
Q2: 3D in packaging started with wire-bonded-chip-stacks and now includes silicon-interposers (a.k.a. “2.5D”) and the memory-cube using through-silicon via (TSV). How about the complexity of 3D products using chip-package co-design, and many players in the ecosystem being needed hroughout design-ramp-HVM?
ANSWER: Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Silicon Systems Group of Applied Materials
Enabling 3D requires the participation of the extended ecosystem. These include contributions from CAD, design tools for die architecture, floor plan, and layout circuit design test structures, as well as methodology wafer level process equipment and materials, wafer-level test assembly and packaging stacked die and package level testing.
Q3: Due to challenges with lithographic scaling below 45nm half-pitch, how does the need to integrate new materials and device structures change the fabless-foundry relationship? How much of fully-depleted channels using SOI wafers and/or finFETs, followed by alternate channels can the industry afford without commited damand from IDMs and major fabless players for specific variants?
ANSWER: Adam Brand, Director of Transistor Technology, Silicon Systems Group of Applied Materials
New materials and device structures are going to play a key role in advancing the technology to the next several nodes.
With EUV delayed, multi-patterning is growing in use, and new materials are enabling the sophisticated and precise extension of multi-patterning to the 7nm node and beyond. The multi-patterning schemes however bring specific restrictions on layout which will affect the design process.
For device structures, Epi in particular is going to enable the next generation of complex device designs with improved mobility and by supporting very thin precisely defined channel structures to scale to smaller gate length and pitch. For these next generation devices, the R&D challenges will be high, but the industry cannot afford to skimp on R&D to find the winning solution to the low power transistor technology required for the 7nm and 5nm and beyond nodes.
Q4: Mobile consumer devices now seem to drive the leading edge of demand for many ICs. However, the Internet-of-Things (IoT) is often spoken of needing just 65nm node chips to keep costs as low as possible, and these designs are expected to run in high volume for many years. How will these different devices that will continue to evolve in different ways get integrated together?
ANSWER: Michael Buehler-Garcia, Senior Director of Marketing, Calibre Design Solutions of Mentor Graphics
IOT has become the new industry buzz word. What it has done is spotlight the multiple elements of a complete solution that do not require emerging process technologies for their chip design. Moreover, while a chip may use a well established process node, the actual design may be very complex. For example Mentor is participating in the German RESCAR program to increase the reliability of automotive electronics using our Calibre PERC solution. The initial reliability checks written are targeted for 180nm and older process nodes. Why? Because today’s 180nm and older node designs are much more complex than when these nodes were mainstream digital nodes and as such require more advanced verification solutions. Bottom line: as opposed to a strategy of only moving to the next process node, chip design companies today have multiple options. It is up to the ecosystem to provide solutions that allow the designers be able to make trade-offs without major changes in their design flows.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.