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The Week in Review: May 30, 2014

Friday, May 30th, 2014

Applied Materials, Inc. introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package, a packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

The Semiconductor Industry Association announced that global semiconductor industry leaders reached an agreement at the 18th annual meeting of the World Semiconductor Council (WSC) last week on a series of policy proposals to strengthen the industry through international cooperation.

The 60th annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

SEMI announced that SEMICON West 2014 will feature Bob Metcalfe, professor at the University of Texas at Austin, as the Silicon Innovation Forum’s keynote speaker.

The Week in Review: May 16, 2014

Friday, May 16th, 2014

On May 14, 2014, it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

Applied Materials announced its Applied Endura Volta CVD Cobalt system, the only tool capable of encapsulating copper interconnects in logic chips beyond the 28nm node by depositing precise, thin cobalt films.. The introduction of cobalt as a superior metal encapsulation film marks the most significant materials change to the interconnect in over 15 years.

Dow Corning introduced Dow Corning EE-3200 Low-Stress Silicone Encapsulant – the latest addition to its portfolio of advanced solutions designed to expand performance and durability of solar micro-inverters, power optimizers and other high value components.

Element Six today announced that its Gallium Nitride (GaN)-on-Diamond wafers have been proven by Raytheon Company to significantly outperform industry standard Gallium Nitride-on-Silicon Carbide (GaN-on-SiC) in RF devices.

A newly finalized Department of Defense (DoD) rule reduces the risk of counterfeit semiconductor products being used by our military by implementing needed safeguards in the procurement of semiconductors and other electronic parts.

Noel Technologies, a Silicon Valley specialty foundry offering process development and substrate fabrication, is now offering services for nanoimprint technology that reduce the costs of the nanoimprint stamps.

SEMATECH announced that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

Mentor Graphics Corporation this week announced the new MicReD Industrial Power Tester 1500A for power cycling and thermal testing of electronics components to simulate and measure lifetime performance. The MicReD Industrial Power Tester 1500A tests the reliability of power electronic components that are increasingly used in industries such as automotive and transportation including hybrid and electrical vehicles and trains, power generation and converters, and renewable energy applications such as wind turbines.  It is the only commercially available thermal testing product that combines both power cycling and thermal transient measurements with structure function analysis while providing data for real-time failure-cause diagnostics.

Solid State Watch: May 9-15, 2014

Friday, May 16th, 2014
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Blog review May 5, 2014

Monday, May 5th, 2014

Jeremy Read of Applied Materials writes that while some consumer IoT applications will require semiconductors manufactured using cutting-edge technologies the vast majority of chips will be used in client-side applications. These chips, such as a sensor monitoring room temperature in a connected HVAC system, require processing capabilities that can be met using legacy process (90 and 45nm) technologies manufactured on 200mm wafers.

Ali Khakifirooz of Spansion notes that body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.

Frank Feng of Mentor Graphics blogs that transistor and gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic discharge (ESD), latch-up, electrical overstress (EOS), and dielectric breakdown. However, when designers assemble transistors and gates into intellectual property (IP), blocks, or whole chip designs, they encounter a variety of reliability problems generated across interconnect layers or across device regions of PSUB and NWELL bodies.

Phil Garrou has not been predicting the end of the world, but rather the end of electronics as we know it, i.e.,relying on CMOS scaling. He blogs that it was with great anticipation that he perused the 2013 ITRS roadmap that was released a few weeks ago. He is happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

Pete Singer writes that the newly revamped International Technology Roadmap for Semiconductors was released in early April. It’s actually called the 2013 ITRS, which makes it seem already out of date, but that’s the way the numbering has always been. The latest ITRS highlights 3D power scaling, system level integration and a new chapter on big data.

Blog review March 31, 2014

Monday, March 31st, 2014

Ofer Adan of Applied Materials blogs about his keynote presentation at the recent SPIE Advanced Lithography conference, which focused on how improvements in metrology, multi-patterning techniques and materials can enable 3D memory and the critical dimension (CD) scaling of device designs to sub-10nm nodes.

Soitec’s Bich-Yen Nguyen and Christophe Maleville detail why the fully-depleted SOI device/circuit is a unique option that can satisfy all the requirements of smart handheld devices and remote data storage “in the cloud.” Devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. Demonstrated benefits of FDSOI, including simpler fabrication and scalability are covered.

This year’s IMAPS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. Phil Garrou takes a look at some of those and several key presentations from the conference. Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.

Karen Lightman of the MEMS Industry Group writes about the recent MEMS Executive Congress Europe 2014. She describes how every panelist shared not only the “everything’s-coming-up-MEMS” perspective but also some real honest discussion about the remaining challenges of getting MEMS devices to market on-time, and at (or below) cost.

Pete Singer shares some details of the upcoming R&D Panel Session at The ConFab this year. The session, to be moderated by Scott Jones of Alix Partners, will include panelists Rory McInerny of Intel, Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst and Lode Lauwers of imec.

Roll over flat panel displays

Tuesday, March 25th, 2014

By Sara Ver-Bruggen, contributing editor

Flexible displays is a technological field that has been in R&D and pre-commercial development for several years, but what needs to happen to make volume production a reality, in areas including substrates, materials and production processes? Semiconductor Manufacturing & Design discussed the issues with Max McDaniel, Director and Chief Marketing Officer, Display Business Group, Applied Materials, Michael Ciesinski, MD of the Flextech Alliance, and Keri Goodwin, Principal Scientist from the Centre for Process Innovation (CPI), in the UK.

SemiMD: Taking a step back and looking at the timeline for flexible display R&D and achievements so far, where is the industry in terms of entering volume production – how close is the industry to resolving those outstanding challenges to volume production, such as cost-effective barrier technologies, for example?

McDaniel: Curved displays are here as evidenced by several curved smartphones and TVs showcased at the Consumer Electronics Show (CES) in January 2014. People are ready for flexible displays, but production volume will take some more time. As the smartphone market matures, brands are embattled in a ‘resolution arms race’. The key challenge for the brand makers is to come up with the next big thing that will differentiate their products and spur new demand from consumers. The display plays a key role in defining the device, and a new form factor – like flexible displays – can bring new opportunities to the market, but the technology is not ready for the mass market because of cost and technology challenges.

Ciesinski: FlexTech initiated its R&D program into flexible displays in 1998 with substantial project funding beginning in 2002 and continuing today. We’ve worked with companies and R&D organizations in the areas of substrates, encapsulation, barrier coating, roll-to-roll (R2R) manufacturing and other key areas. Generally, the supply chain for flexible electronics is adequate but not yet robust, which will occur once large volume production is achieved. In building flat panel displays (FPDs) that industry could build on IC manufacturing strengths and simply scale the equipment. For volume manufacturing on a flexible substrate, many new tools and processes have to be developed from scratch, such as metrology, as experts must build a system to account for a substrate that can shrink or expand depending on temperature, and move in multiple directions. As for barriers, several solutions are available and ready for production. The extreme requirements for OLED thin film barriers have been achieved in production and the main focus now is on cost reduction. The materials industry is quite competitive and ready for volume. In order to obtain better utilization of these materials in production new printing equipment is being developed.

Goodwin: There are still significant challenges to overcome in flexible display volume production. A cost-effective flexible barrier with a very low water transmission vapor rate (WVTR) is still to be developed, this will be required if OLED frontplanes are to be used. Typically these barriers are still multilayer structures with a mix of inorganic and organic coatings to minimize defect levels. While this can be achieved R2R, perhaps via a combination of sputter deposition and solution processing such as slot die, the cost will ultimately be set by the number of multiple coatings required.

An alternative method may be to use R2R atomic layer deposition (ALD), which should yield a significantly lower level of defects, thereby improving the barrier capability of a single layer and reducing, or removing, the need for multiple coatings. However, process scale up is required. CPI envisages that R2R ALD will play important roles in various aspects of flexible printable electronics, where highly conformal nanoscale thin films are required. CPI has been evaluating ALD technology for several years and recently signed an agreement with Beneq to deliver an ALD system to CPI for pilot scale production.

Layer-to-layer registration is another major challenge to overcome in volume production with flexible substrates typically distorting during processing. This issue can be overcome in several ways such as development of lower temperature processes or development of lamination materials to allow sheet-to-sheet (S2S) production without distortion.

And, in terms of commercialization for flexible (as opposed to curved) displays what time frame are we talking?

McDaniel: The approach for early adopters of flexible displays has been a production process that adheres the flexible substrate onto glass, running it through what’s mostly the normal rigid OLED processing, and then delaminating that flexible substrate from the rigid one at the end of processing. What remains is a flexible substrate that has all the transistor structures built onto it. However, this is still a complex process, and due to the cost and complexity involved in manufacturing on a high-volume scale, it is still a ways off from full mass production.

Goodwin: Overall, there are multiple approaches to volume production of flexible displays but all require scale up towards a commercialization solution, therefore it would be expected that the timeline for a product is still five years away. What is important in the short term is to demonstrate controlled processes that can yield products with good lifetime and performance, which then can be scaled up for commercialization.

Ciesinski: Displays in a conformable format have been produced and exhibited; a truly flexible and foldable display is much more than that and there are many approaches to achieving this result in the next few years.

Various flexible display R&D has focused on different substrates, different thin film transistor (TFT) materials and so on. Is there likely to be one approach that will make it to volume production?

Ciesinski: Multiple approaches are currently being considered by the market. For example, plastic substrate films from DuPont Teijin and other suppliers have a strong a presence. Corning’s introduction of flexible glass provides a competitive choice. As for the display technology, LCDs, OLEDs and electrophoretic displays have all been built in a flexible format. Materials will continue to improve and there will be multiple TFT materials for the next few years.

McDaniel: Materials have a key role to play in the R&D efforts for enabling flexible displays. OLED is promising as the rigid glass encapsulation required to protect the organic material from moisture and air can be replaced by thin film. You can make flexible LCD displays but maintaining the required cell gap between the color filter and backplane is very difficult to do. Both OLED and LCD require a TFT backplane. A major challenge for the industry is how to move away from rigid glass while not compromising the operation of the TFT when flexed, folded, or bent.

We have discussed the backplane and encapsulation; but for OLED to get to mass production (especially in large sizes); the industry also has to address challenges in EL evaporation such as lifetime of organic materials, low deposition efficiency, low yield from defects and scalability of evaporation technology which affect the cost of volume production but are not necessarily related to the issues around flexibility. All display technologies, including OLED displays, require very high levels of precision in film uniformity and particle control to maintain yield. There is the potential for OLED display production to become less expensive, and Applied Materials is leveraging its expertise in precision materials engineering to help solve these technology hurdles to reduce the cost and complexity.

Goodwin: It is likely that there will be multiple options for volume production. This will depend on final product requirements, such as limits of flexibility, level of resolution of display and cost of display. For example, metal oxide-based TFT displays already demonstrate high performance in terms of the TFT, and therefore can achieve high resolution displays, but ultimately will be very limited in the flexibility.

Organic electronics show excellent flexibility, but historically have tended to have a lower performance for OLED display backplanes and therefore may not achieve the same level of display resolution as metal oxide in the short term. More recently this gap in performance has been closed substantially making organic TFT backplanes a good candidate for a wide variety of display formats and resolutions. In addition OTFT backplanes may ultimately be a lower cost of production. Overall, it is likely that the different TFT technologies will independently develop the substrate types suitable for their processes, for example metal oxide on high temperature substrates and for organics the substrates are likely to be more flexible and suitable for lower temperature processes.

SemiMD: In terms of production equipment and tool advances, which technologies are most promising for enabling volume production of flexible displays?

Goodwin: Metal oxide is currently deposited via industrially used techniques/tools in the display industry, such as sputter deposition. This makes it a likely candidate for early adoption in the display industry, with moderate investment required to enable scale-up. However, solution-processing of organic based materials is likely to provide a lower cost of manufacture via the route of additive printing and R2R manufacture. CPI is working with a number of SMEs in building scale up capability across a range of printed and plastic electronics technology areas such as OLED, OTFT and barrier encapsulation, to help take forward new research ideas into technology prototypes and then into manufacturing demonstrators.

McDaniel: Flexible and other future bendable form factors in display will require precision engineered materials including thin film technologies that deliver performance with stringent uniformity and defect requirements at lower cost and less power. Advances in CVD and PVD systems for LTPS and metal oxide will play an important role in achieving high resolution but even these processes will require materials modification to support the full promise of flexible displays. One example of a required modification is indium tin oxide (ITO), a mainstay process step in TFT-LCD but as a material may prove to be too brittle in the production of more flexible displays.

Applied is also looking to help display makers mass produce larger scale, more efficient manufacturing processes and advanced materials as a means of gaining economies of scale at the factory.

Ciesinksi: FlexTech has funded and successfully completed projects for key steps in flex display manufacturing, such as lithography and deposition. Clearly various printing technologies and RTR additive manufacturing processes are capable of achieving major advances in flexible display production which will be seen over the next few years.

SemiMD: New display technologies that commercialise successfully have done so because they have enabled new products. The mass volume production of LCDs has helped to initiate smart phones, tablet devices, for example, while e-paper (E-Ink) display technology is largely responsible for e-reader devices such as the ubiquitous Kindle. So what potential new class of consumer/portable electronic device might flexible display technology enable? On the other hand, will the technology, in the nearer term, be more beneficial for enabling rugged/unbreakable display-based electronic devices?

McDaniel: There is a lot of potential. Think about what our phones looked like six or seven years ago. Now we’re seeing HD-quality screens on a device we can slip into our pockets. We could see flexible displays enabling devices that can be rolled up or folded into more compact shapes. Some studies have said that for a tablet, people prefer semi-rigid displays to something that is flopping around, to provide structure while they’re reading it. In the public environment flexible could bring the possibility of more immersive or interactive displays at airports or on billboards, or even on the sides of buildings. There are a lot of possibilities.

Goodwin: Rugged displays are likely to have military applications and so may attract funding support from this sector and therefore this may be a route to the first marketable products. However, the learning from the production of those rugged displays can likely be used within new mainstream product development. Many major display manufacturers are already trying to patent areas of interest such as smart watches and early products may focus on these smaller displays. Ultimately, if volume production is possible and large area displays can be produced then there is a vast range of products that can be envisaged from clothing applications, rollable/foldable phones, large scale advertising hoarding or even replacement of aircraft windows with lightweight displays.

Ciesinski: Technology adopters fall into several categories. For example, early adopters are those with the first cellular phone, the first tablet, etc. These users are willing to sacrifice elegance or product maturity for functionality. Other adopters waited until smart phones became fully functional before consolidating to a primary device from a combination of a PC, cell phone, and pager. Wearable electronics, as a class, represents a game-changing technology. A wearable device – even with limited functionality – is attractive, for example, to competitive athletes if it can help improve performance even modestly. Once wearable technology matures, it can explode into other markets to monitor the chronically ill, aged/infirm, or paediatric patients. Then, it jumps to the packaging or automotive or aerospace markets in the form of sensors.

Once flexible display technologies reach volume production, how fast might the technology establish itself – evolve from niche to mainstream?

Ciesinski: Successful technologies ramp quickly and displace incumbent technologies ruthlessly. Just consider the displacement of CRTs by FPDs or CCFL backlights by LED backlights. FlexTech believes that flexible electronics – of which flexible displays is a subset – will grow rapidly in multiple markets, led by disposable and wearable electronics. Our recent user survey indicated substantial purchases of flexible electronics by key end users within three years; adoption by large contract manufacturers is already taking place due to their customer demands.

Goodwin: This is likely to be dependent on the product uptake. For example the rise of tablets and smart phones drove the development of OLED frontplane and materials development. The same is likely to happen with flexible displays. Early products may have limited flexibility, for example the already available curved display products from LG and Samsung, but later products will need to show the truly flexible nature of these advanced displays. Once market pull is established a range of products are likely to be developed that will aid the flexible display to become a mainstream product. CPI can play a vital role in the move from niche to mainstream by providing the infrastructure and environment for companies to de-risk and scale up their innovative ideas from concept to market.

McDaniel: Five years ago, when display manufacturers wanted to start bending and curving the design, they faced a new set of struggles. Applied Materials had insights on where the market was heading and was already working on technologies to address the challenges. We have seen similar waves of technology with laptops and smartphones, and the acceleration of flexible or curved display devices or other form factors could take off in a similar manner. Display analyst firms are anticipating strong growth for the flexible and curved displays market over the next several years. For instance, Touch Display Research has forecast flexible and curved displays to achieve 16% of the global display revenue market by 2023 compared with 1% in 2013.

The Week in Review: March 21, 2014

Friday, March 21st, 2014

Research from University of California, Berkeley scientists sponsored by Semiconductor Research Corporation (SRC) promises to revolutionize portable radio frequency (RF) electronics and communication systems via advancements in on-chip inductors by leveraging embedded nanomagnets. The UC Berkeley research focuses on using insulated nano-composite magnetic materials as the filling material to shrink the size and improve the performance of high frequency on-chip inductors, thereby enabling a new wave of miniaturized electronics and wireless communications devices.

North America-based manufacturers of semiconductor equipment posted $1.29 billion in orders worldwide in February 2014 (three-month average basis) and a book-to-bill ratio of 1.00, according to the February EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

Dr. Tzu-Yin Chiu, Chief Executive Officer & Executive Director of SMIC presented the SEMICON China 2014 opening keynote yesterday and was given a SEMI Outstanding EHS Achievement Award.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has opened a new, wholly owned subsidiary in Shanghai, called EV Group China Ltd., which will serve as regional headquarters for all of EVG’s operations in China.  The new subsidiary, which houses a local service center and spare parts management facility, will further strengthen EVG’s presence in the region and support the company’s ongoing efforts to improve service and response times to local customers.

ChaoLogix, Inc., a semiconductor technology provider focused on developing embedded security and low-power design intellectual property, today introduced ChaoSecure technology that deters side channel attacks on semiconductor chips and contributes a superior layer of security compared to existing solutions. ChaoLogix’s ChaoSecure technology is a hardware-based solution designed to provide optimal performance at the nexus of security and power. Proven in silicon and validated by an independent security lab, ChaoSecure is a secure standard cell library that can be easily integrated into an existing integrated circuit (IC) — making it the ideal security solution in terms of cost and performance for designing complex applications ranging from smart cards to smart phones.

Applied Materials, Inc. this week announced that it was named a 2014 World’s Most Ethical Company by the Ethisphere Institute, an independent center of research promoting best practices in corporate ethics and governance. This is the third consecutive year Applied Materials has received the annual award, which recognizes organizations that continue to demonstrate ethical leadership and corporate behavior.

Blog review March 17, 2014

Monday, March 17th, 2014

Pete Singer is delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th.

Phil Garrou takes a look at what was reported at SEMI’s 2.5/3D IC Summit held in Grenoble, focusing on presentations from Gartner, GLOBALFOUNDRIES, TSMC and imec. He writes that GLOBALFOUNDRIES has been detailing their imminent commercialization of 2.5/3D IC for several years, and provide a chart showing the current status report. TSMC offered a definition of their supply chain model where OSATS are now integrated.

Bharat Ramakrishnan of Applied Materials writes about the importance of wearable electronics in the Internet of Things (IoT) era, and the role that precision materials engineering will play. He note that one key part of the wearables ecosystem that is still in need of new innovations is the battery. Two of the biggest challenges to overcome are the thick form factor due to battery size, and the lack of adequate battery life, thus requiring frequent recharging.

Blog review March 10, 2014

Monday, March 10th, 2014

Pete Singer is pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, and has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances.

Nag Patibandla of Applied Materials describes a half-day workshop at Lawrence Berkeley Lab that assembled experts to discuss challenges and identify opportunities for collaboration in semiconductor manufacturing including EUV lithography, advanced etch techniques, compound semiconductors, energy storage and materials engineering.

Adele Hars of Advanced Substrate News reports on a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during SEMI’s recent ISS Europe Symposium. FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law, she writes.

Phil Garrou reports on the RTI- Architectures for Semiconductor Integration & Packaging (ASIP) conference, which is focused on commercial 3DIC technology. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing. In addition Tezzaron’s Robert Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly.

Vivek Bakshi, EUV Litho, Inc., blogs that most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of January 2014, an increase of 8.8% from January 2013 when sales were $24.2 billion. After adding in semiconductor sales from excluded companies such as Apple and Sandisk, that total is even higher, marking the industry’s highest-ever January sales total and the largest year-to-year increase in nearly three years. These results are in-line with the Semico IPI index which has been projecting strong semiconductor revenue growth for the 1st and 2nd quarters of 2014.

Experts At The Table: Commercial potential and production challenges for 3D NAND memory technology

Thursday, February 6th, 2014

The last six months have seen several developments concerning 3D memory concepts moving into production, from companies such as Samsung, Micron, Toshiba and Sandisk. What follows are excerpts from a roundtable discussion with SemiMD, Samsung Electronics (SE) in South Korea, which has begun production of its proprietary 3D NAND technology, Bradley Howard, Vice President of Advanced Technology Group, Etch Business Unit, at Applied Materials and Jim Handy from Objective Analysis, which specialises in coverage of the memory industry.

SemiMD: Where does 3D NAND fit into the long-term roadmap for memory technology and is there one technology most likely to dominate?

SE: We successfully came out with the industry’s first 3D NAND (V-NAND) in August 2013, which offers 128 GB on a chip and vertically stacks cell layers that make use of charge trap flash (CTF) technology. The V-NAND has already been used in 960 GB solid state drives (SSDs) for server and enterprise applications.

The V-NAND technology is expected to replace planar NAND market gradually, starting from the high-end enterprise market. We will continue to come up with more advanced V-NAND products with higher density and reliability. The company has also been working on a diversity of next-generation memory technologies including RRAM (or ReRAM) while strengthening its future business competence.

Howard: All major memory customers have 3D NAND transition in their roadmap. We’ll soon see the first generation of 24-layer 3D cell array devices enter the market. RRAM and STT-MRAM technologies are further out from the market as there are still critical process and manufacturing challenges for both the materials and patterning.

Handy: NAND will dominate. 3D NAND is less disruptive than alternative technologies, like RRAM, since it involves the same materials that have been used to produce NAND for its entire lifetime, while RRAM, MRAM, FRAM and so on require new materials that are not as well understood. After 3D NAND has reached a limit and can no longer place increasing numbers of transistors onto a wafer then the door is opened for alternative technologies like RRAM, but that won’t happen until 2023.

How is the semi industry (such as foundries and designers) preparing for the transition to 3D memory?

Handy: The bulk of the semiconductor industry doesn’t need to transition since these technologies are only being used for the highest-density discrete memory chips. The most significant impact should be to the capital equipment market, where a move to 3D could increase materials equipment usage while decreasing spending on lithography tools.

SE: We are working closely with global IT companies in a wide range of fields to expand the market base and application of 3D V-NAND, and we expect that the market will grow rapidly throughout the year. The 3D V-NAND is expected to be adopted in many different applications including SSDs, high-density memory cards and other applications for consumer electronics. While Samsung will work on more V-NAND based applications, the company also will contribute to global IT companies’ development of next-generation IT systems using our 3D V-NAND products.

Are there specific tooling challenges that must be overcome?

SE: The key technologies for V-NAND would be applying 3D CTF structure for individual cells and constructing vertically interconnected cell arrays. We have mastered these technological challenges and will continue to come up with more advanced V-NAND products.

Howard: Fabricating vertically to build multilayer stacks of 3D NAND cells reduces the historical reliance on lithography as the dominant and limiting factor in scaling, and increases the role of materials-enabled deposition and etch to drive vertical scaling. This shift brings formidable device performance and yield challenges for deposition and etch technologies including distortion-free high aspect ratio etching, complex staircase patterning with precise step-width control, and uniform and repeatable deposition.

From a 3D NAND fab perspective, the changing balance of tool types toward significantly more deposition and etch equipment will have a substantial impact on tool footprint and fab layout to enable optimum manufacturing efficiency. Moreover, this new tool balance compromises the capability to adjust manufacturing capacity between NAND and DRAM since planar NAND and DRAM share a high level of commonality with regard to the balance of tool types and lithography.

Handy: For 3D NAND there are significant challenges in putting down layers that have uniform thickness across the entire wafer. There are also issues with pull-back etching for stairsteps that currently increase the lithography load more than was originally anticipated, but this issue should eventually be solved. For alternative technologies there will be issues in bringing new materials into the fab, some of which are antagonistic to the underlying silicon.

To what extent can 3D memory chips be scaled and what challenges does this pose?

Howard: Scaling for the first few generations, from 32 to 48 to 64 and higher cell layer stacks will largely be a matter of adding more vertical layers. The general consensus is that this is sustainable to around 100 device layers, and this will likely require some amount of reduction on the layer thicknesses to control the aspect ratios that must be etched. Even small reductions in thickness are critical, because any reduction gets multiplied by the number of layers. Scaling beyond this will likely require more effort towards thinning the layers through advancements on the device architecture.

Lithographic-based horizontal scaling will continue, but instead of the historical 15-20 percent CD reduction per generation, we expect planar scaling to slow dramatically, equivalent to a CD shrink more on the order of ~5 percent per generation. In addition, layout changes in the peripheral circuits to achieve more efficiency, along with more efficient designs for the complex staircase structure to allow for access to the different layers, are expected. These will all play a role in overall die size efficiency.

For deposition, major challenges to effectively scale vertically are advanced thickness and uniformity controls layer to layer. Any non-uniformity in a film layer will propagate throughout the stack as subsequent layers are deposited on top of it. With more layers in the device stack, this results is more devices potentially impacted by topography.

The challenge for etch is growing high aspect ratios despite a thinning down of individual layers in the stack. Aspect ratios today are already at 60:1. Achieving etch fidelity at such aspect ratios puts pressure on getting higher selectivity to the mask material which already is very thick. In some cases, the aspect ratio for the hard mask is already greater than 20:1, and this is the aspect ratio before even starting the etch into the device stack. While thinning the hard mask layer reduces the overall aspect ratio of the feature, new more resilient patterning films will be required. Higher selectivity will be through a combination of new materials with higher etch resistance and improvements to the etch process chemistry.

SE: We have core technologies to develop more advanced high-density V-NAND devices and are seeking to define manufacturing technologies for stacking more than 24-cell-layer structure which was applied to our first 3D V-NAND device.

The most advanced process technology for conventional NAND using floating gate would be 10 nm-class technology. However, process technology refers to the width of integrated circuitry that is used for NAND on a conventional planar structure. Applying the same considerations to our V-NAND would not be appropriate because the cell array structure has been totally changed.

For example, if we compare the wafer productivity of Samsung’s new 128 GB V-NAND to previous products, it has the approximate chip size of a conventional NAND that was built using approximately mid-10nm-class process technology.

The 3D V-NAND has its strength in scalability. There are plans to continue developing more advanced V-NAND products and applications including 1 TB and higher-density SSDs for servers and enterprise systems and other next-generation memory storage which should lead to the growth of the overall NAND flash market.

Handy: 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will probably find ways of placing these strings closer to each other through more aggressive lithography. There is a lot of room for scaling in 3D.

Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer. This is also true of the layers that are deposited on the walls of the hole. The entire issue of 3D is its phenomenal complexity.

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